CN115996522A - Buried resistor structure and manufacturing method thereof - Google Patents
Buried resistor structure and manufacturing method thereof Download PDFInfo
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- CN115996522A CN115996522A CN202111223404.3A CN202111223404A CN115996522A CN 115996522 A CN115996522 A CN 115996522A CN 202111223404 A CN202111223404 A CN 202111223404A CN 115996522 A CN115996522 A CN 115996522A
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Abstract
The application provides a manufacturing method of an embedded resistor structure, which comprises the following steps: providing a substrate layer, wherein the substrate layer comprises a first surface and a second surface, and the first surface and the second surface are arranged opposite to each other and are provided with copper-plated material layers; etching the copper plating material layer to form a copper plating layer, wherein the copper plating layer comprises a first copper plating layer and a second copper plating layer, the first copper plating layer is formed on the first surface, and the second copper plating layer is formed on the second surface; forming a plurality of through holes on the substrate layer along the direction perpendicular to the copper plating layer; forming a resistive material layer at least on an inner sidewall of the via; and forming a protective layer to obtain the embedded resistor structure. In addition, the application also provides an embedded resistor structure which is manufactured by the manufacturing method of the embedded resistor structure.
Description
Technical Field
The application relates to the field of circuit board manufacturing, in particular to an embedded resistor structure and a manufacturing method thereof.
Background
In the conventional circuit board with the embedded resistor structure, only a small part of the alloy layer used as the resistor is covered with the resistor material under the direct contact of the conductive material (such as copper) due to the manufacturing process. These resistive materials not only do not function as resistors, but also cause transmission loss in other lines at the same layer, thereby affecting the transmission speed of the overall line. Meanwhile, the existing embedded resistors existing in the form of lines are arranged on the surface of the circuit board, and occupy a large amount of surface space of the circuit board.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a buried resistor structure and a method for manufacturing the same, which can increase the transmission speed of an overall circuit and reduce the space occupied by the buried resistor on the surface of the circuit board.
A manufacturing method of an embedded resistor structure comprises the following steps: providing a substrate layer, wherein the substrate layer comprises a first surface and a second surface, and the first surface and the second surface are arranged opposite to each other and are provided with copper-plated material layers; etching the copper plating material layer to form a copper plating layer, wherein the copper plating layer comprises a first copper plating layer and a second copper plating layer, the first copper plating layer is formed on the first surface, and the second copper plating layer is formed on the second surface; forming a plurality of through holes on the substrate layer along the direction perpendicular to the copper plating layer; forming a resistive material layer at least on an inner sidewall of the via; and forming a protective layer to obtain the embedded resistor structure.
Optionally, the step of forming a resistive material layer at least on an inner sidewall of the through hole includes: forming a layer of resistive material on an inner sidewall of the via, on at least a portion of a surface of the first copper plating layer remote from the substrate layer, and on at least a portion of a surface of the second copper plating layer remote from the substrate layer;
the step of forming a protective layer to obtain the buried resistor structure includes: and forming a protective layer on the first surface, the second surface and the through hole to obtain the embedded resistor structure.
Optionally, before the step of forming a plurality of through holes in the substrate layer in a direction perpendicular to the copper plating layer, the method includes: a plurality of grooves are formed in the surface of the base material; forming a partial resistance material layer on the inner side wall of the groove and at least part of the surface of the copper plating layer far away from the substrate layer;
the step of forming a protective layer to obtain the buried resistor structure includes: and forming a protective layer on the first surface, the second surface, the through hole and the groove to obtain the embedded resistor structure.
Optionally, the step of forming a plurality of grooves on the surface of the substrate includes: attaching a dry film to the surface of the substrate layer at the position where grooves are not required to be formed; plasma etching is carried out on the surface of the substrate layer so as to form the groove; and removing the dry film.
Optionally, after the step of forming a part of the resistive material layer on the inner sidewall of the groove and on the surface of at least part of the copper plating layer away from the base material layer, the method further comprises: and calculating the resistance value of the current embedded resistor formed by the current resistance material layer and the copper plating layer, and determining the number of the through holes according to the resistance value of the current embedded resistor and the resistance value of the required resistor.
Optionally, the step of forming a resistive material layer at least on an inner sidewall of the through hole includes: forming a layer of resistive material on an inner sidewall of the via, on at least a portion of a surface of the first copper plating layer remote from the substrate layer, and on a surface of the second copper plating layer exposed within the via;
the step of forming a protective layer to obtain the buried resistor structure includes: and forming a protective layer on the first surface, the second surface and the through hole to obtain the embedded resistor structure.
Optionally, the resistive material layer comprises nickel, chromium, tungsten, nickel-phosphorus alloy, and titanium-tungsten alloy.
A manufacturing method of an embedded resistor structure comprises the following steps: providing a substrate layer, wherein the substrate layer comprises a first surface and a second surface, and the first surface and the second surface are arranged opposite to each other and are provided with copper-plated material layers; etching the copper plating material layer to form a copper plating layer on the first surface; a plurality of copper plating layers are arranged on the substrate layer along the direction perpendicular to the copper plating layer; forming a first protective layer on the second surface of the substrate layer; forming a resistive material layer on an inner sidewall of the via, at least a portion of a surface of the copper plating layer remote from the substrate layer, and a surface of the first protective layer exposed within the via; and forming a second protective layer on the first surface of the substrate layer.
The embedded resistor structure is manufactured by the manufacturing method of the embedded resistor structure.
Compared with the prior art, the application has at least the following beneficial effects: by forming the resistive material layer in the through hole, or in the groove, or above a portion of the copper plating layer, it is avoided that all of the copper plating layer is in direct contact with the resistive material layer, and further, the line that is not in direct contact with the resistive material layer is prevented from unnecessary transmission loss, and the transmission speed of the overall line is improved. Meanwhile, most of the resistor material layers are not directly formed on the surface of the substrate layer, so that the space occupied by the embedded resistor on the surface of the circuit board is reduced.
Drawings
Fig. 1a to 1e are schematic diagrams illustrating a first embodiment of the present application for manufacturing a buried resistor structure.
Fig. 2a to 2h are schematic diagrams illustrating a manufacturing of a buried resistor structure according to a second embodiment of the present application.
Fig. 3a to 3e are schematic diagrams illustrating a manufacturing of a buried resistor structure according to a third embodiment of the present application.
Fig. 4a to 4f are schematic diagrams illustrating a manufacturing of a buried resistor structure according to a fourth embodiment of the present application.
The following detailed description will further illustrate the application in conjunction with the above-described figures.
Description of the main reference signs
Buried resistor structure 100
Copper-plated material layer 201
First copper plating layer 21
Second copper plating layer 22
First protective layer 41
Second protective layer 42
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Referring to fig. 1a to 1e, a first embodiment of the present application provides a method for manufacturing a buried resistor structure, which includes the following steps:
in the first step, referring to fig. 1a, a substrate layer 10 is provided. The substrate layer 10 includes a first surface 11 and a second surface 12 opposite to the first surface 11. The first surface 11 and the second surface 12 are both provided with a copper-plated material layer 201.
It will be appreciated that the first step provides a double-sided copper-clad substrate.
The substrate layer 10 may be any insulating material with a bearing function.
In this embodiment, the material of the substrate layer 10 may be one of Polyimide (PI), polyethylene (PE), teflon (Teflon), liquid crystal polymer (liquid crystal polymer, LCP), polyvinyl chloride (polyvinyl chloride polymer, PVC), and the like.
In other embodiments, the material of the substrate layer 10 may be polyethylene terephthalate (polyethylene terephthalate, PET), polyethylene naphthalate (polyethylene paphthalate, PEN), or other resin hard materials.
In the second step, referring to fig. 1b, the copper plating material layer 201 is etched to form a copper plating layer 20. The copper plating layer 20 includes a first copper plating layer 21 and a second copper plating layer 22.
Wherein the first copper plating layer 21 is formed on the first surface 11, and the second copper plating layer 22 is formed on the second surface 12.
In the third step, referring to fig. 1c, a plurality of through holes 13 are formed in the substrate layer 10 along a direction perpendicular to the copper plating layer 20.
The plurality of through holes 13 may be formed by laser drilling, for example.
Wherein, a first copper plating layer 21 is disposed on the first surface 11 corresponding to the position where the through hole 13 is opened, and a second copper plating layer 22 is disposed on the second surface 12 corresponding to the position where the through hole 13 is opened.
It will be appreciated that the through hole 13 is opened from one side of the substrate layer 10 (e.g. the side of the first surface 11) to the other side (e.g. the side of the second surface 12), and penetrates the first copper plating layer 21, the substrate layer 10 and the second copper plating layer 22 in sequence.
It will be appreciated that the number of the through holes 13 is determined according to the required resistance of the embedded resistor.
Fourth, referring to fig. 1d, a resistive material layer 30 is formed on the inner sidewall of the through hole 13, at least a portion of the surface of the first copper plating layer 21 away from the substrate layer 10, and at least a portion of the surface of the second copper plating layer 22 away from the substrate layer 10 by selective electroplating. That is, the resistance material layer 30 covers at least a part of the first copper plating layer 21, the inner sidewall of the through hole 13, and a part of the second copper plating layer 22. The main components of the resistive material layer 30 are nickel, chromium, tungsten, nickel-phosphorus alloy, titanium-tungsten alloy, etc.
It will be appreciated that since the routing of the traces will follow the path of the low resistance material (i.e., copper plated layer 20), only the resistive material layer 30 that is not directly covered by the copper plated layer 20 or directly covers the copper plated layer 20 will act as an embedded resistor.
In the conventional process of manufacturing the embedded resistor, the resistor material layer 20 is disposed below the copper plating layer 30, so that the resistor material layer 30 is directly covered below the copper plating layer 20. Since the transmission path of the circuit is along the copper plating layer 20, the resistor material layer 30 disposed below the copper plating layer 20 does not only function as an embedded resistor, but also affects the transmission speed of the circuit of the copper plating layer 20 directly covered thereabove.
In the present method (i.e., the first embodiment), the resistive material layer 30 is formed only on a portion of the copper plating layer 20 or in the through hole 13, and the copper plating layer 20 on which the resistive material layer 30 is not disposed can perform the line transmission without affecting the line transmission speed by the resistive material layer 30.
It will be appreciated that the formation of a majority of the resistive material layer 30 within the via 13 avoids the use of substantial amounts of space on the surface of the substrate layer 10 (e.g., the first surface 11 or the second surface 12) compared to the prior art, thereby allowing more space on the surface of the substrate layer 10 to accommodate other electronic components.
It will be appreciated that the resistive material layer 30 may be formed only on the inner side walls of the through holes 13 in some embodiments, but the resistive material layer 30 formed on the inner side walls of the through holes 13 needs to be in direct contact with the corresponding copper plating layer 20 (in this embodiment, by forming the resistive material layer 30 on a part of the first copper plating layer 21 or the second copper plating layer 22) in order to ensure connection to the wiring.
Fifth, referring to fig. 1e, a passivation layer 40 is formed on the first surface 11, the second surface 12 and the through hole 13. Thus, the buried resistor structure 100 is formed.
It is understood that the protective layer 40 is formed on the outside of the buried resistor structure 100. The protective layer 40 may be a coverlay or a solder mask.
Referring to fig. 2a to 2h, a second embodiment of the present application provides a method for manufacturing a buried resistor structure 100, for manufacturing the buried resistor structure of the second embodiment, including the following steps:
in the first step, referring to fig. 2a, a substrate layer 10 is provided, the substrate layer 10 includes a first surface 11 and a second surface 12 opposite to the first surface 11, and a copper-plated material layer 201 is disposed on the first surface 11 and the second surface 12.
In the second step, referring to fig. 2b, the copper plating material layer 201 is etched to form a copper plating layer 20. The copper plating layer 20 includes a first copper plating layer 21 and a second copper plating layer 22.
Wherein the first copper plating layer 21 is formed on the first surface 11, and the second copper plating layer 22 is formed on the second surface 12.
In the third step, referring to fig. 2c, a dry film 50 is attached to the surface of the substrate layer 10 at a position where the grooves 14 (see fig. 2 d) are not required.
It will be appreciated that the copper plating layer 20 has been formed on the surface of the base material layer 10. Taking the substrate layer 10 side (i.e., the first surface 11) as an example, the first copper plating layer 21 is already formed on the first surface 11. The preset position of the groove 14 is located in the gap of the first copper plating layer 21. The dry film 50 is disposed at a predetermined position of the groove 14 on the first surface 11.
Fourth, referring to fig. 2d, plasma etching is performed on the surface of the substrate layer 10 where the dry film 50 is not disposed, so as to form the grooves 14.
It will be appreciated that the purpose of the third and fourth steps of the method is to form the grooves 14, and that in other embodiments, the method of forming the grooves 14 is not limited to plasma etching, and other methods of drilling holes at constant depth may be used.
Fifth, referring to fig. 2e, the dry film 50 is removed, and a portion of the resistive material layer 30 is formed on the inner sidewall of the recess 14 and at least a portion of the copper plating layer 20 away from the surface of the substrate layer 10 by selective electroplating. That is, the resistive material layer 30 at least partially covers the first copper plating layer 21, the inner sidewall of the recess 14, and a portion of the second copper plating layer 22.
It is understood that the first copper plating layer 21 or the second copper plating layer 22 covered with the dry film 50 is not unnecessarily transmitted as a wire because it is not plated with the resistive material layer 30.
In the sixth step, referring to fig. 2f, a plurality of through holes 13 are formed in the substrate layer 10 along a direction perpendicular to the copper plating layer 20.
Wherein, a first copper plating layer 21 is disposed on the first surface 11 corresponding to the position where the through hole 13 is opened, and a second copper plating layer 22 is disposed on the second surface 12 corresponding to the position where the through hole 13 is opened.
It will be appreciated that the recess 14 and the through hole 13 are both formed to form the resistive material layer 30 inside the substrate layer 10, so as to reduce the space occupied by the surface of the substrate layer 10. Therefore, the opening position of the through hole 13 is different from the existing opening position of the groove 14.
It will be appreciated that since the partial embedded resistor has been formed in the third step, it is necessary to determine the number of openings of the through holes 13 by measuring and calculating the resistance value of the embedded resistor to be formed. Specifically, it is necessary to measure the resistance of the current embedded resistor (i.e. the embedded resistor formed by the current resistive material layer 30 and the copper-plated layer 20), calculate the difference between the resistance of the current embedded resistor and the resistance of the required resistor, and calculate the number of the required through holes 13 according to the difference.
Seventh, referring to fig. 2g, the resistive material layer 30 is formed on the inner sidewall of the through hole 13 by selective electroplating.
It will be appreciated that when the selective plating is performed in the seventh step on the part of the resistive material layer 30 that has been formed in the fifth step, there is no need to further perform the plating on the resistive material layer 30 that has been formed. Therefore, the selective plating in the seventh step is only required to form the resistive material layer 30 on the inner side walls of the through holes 13.
In the eighth step, referring to fig. 2h, a passivation layer 40 is formed on the first surface 11, the second surface 12, the through hole 13 and the recess 14, so as to obtain a buried resistor structure 100.
It is apparent that the manufacturing method of the embedded resistor structure 100 according to the second embodiment of the present application is different from the manufacturing method of the first embodiment mainly in that the third, fourth and fifth steps of the method need to form the grooves 14 on the substrate layer 10. Other steps are similar to those of the first embodiment of the present application, and will not be described again.
Referring to fig. 3a to 3e, a third embodiment of the present application provides a method for manufacturing a buried resistor structure 100, which includes the following steps:
in the first step, referring to fig. 3a, a substrate layer 10 is provided, the substrate layer 10 includes a first surface 11 and a second surface 12 opposite to the first surface 11, and a copper-plated material layer 201 is disposed on the first surface 11 and the second surface 12.
In the second step, referring to fig. 3b, the copper plating material layer 201 is etched to form a copper plating layer 20. The copper plating layer 20 includes a first copper plating layer 21 and a second copper plating layer 22.
Wherein the first copper plating layer 21 is formed on the first surface 11, and the second copper plating layer 22 is formed on the second surface 12.
In the third step, referring to fig. 3c, a plurality of through holes 13 are formed in the substrate layer 10 along a direction perpendicular to the copper plating layer 20.
Wherein, a first copper plating layer 21 is disposed on the first surface 11 corresponding to the position where the through hole 13 is opened, and a second copper plating layer 22 is disposed on the second surface 12 corresponding to the position where the through hole 13 is opened. The through hole 13 is opened such that a side of the second copper plating layer 22 close to the base material layer 10 is exposed in the through hole 13.
It will be appreciated that the through hole 13 is opened from one side of the substrate layer 10 (e.g. the side of the first surface 11) to the other side (e.g. the side of the second surface 12), and sequentially passes through the first copper plating layer 21 and the substrate layer 10.
Fourth, referring to fig. 3d, a resistive material layer 30 is formed on the inner sidewall of the through hole 13, at least a portion of the surface of the first copper plating layer 21 away from the substrate layer 10, and the surface of the second copper plating layer 22 exposed in the through hole 13 (close to the substrate layer 10) by selective electroplating. That is, the resistive material layer 30 at least partially covers the surface of the first copper plating layer 21 remote from the base material layer 10, the inner side wall of the through hole 13, and the surface of the second copper plating layer 22 exposed inside the through hole 13.
It will be appreciated that the portions of the second copper plating layer 22 not directly exposed to the through-holes 13 (e.g., the second copper plating layer 22 on both sides in fig. 3 e) are not unnecessarily lost in transmission due to the fact that the resistive material layer 30 is not plated.
Fifth, referring to fig. 3e, a passivation layer 40 is formed on the first surface 11, the second surface 12 and the through hole 13, so as to obtain a buried resistor structure 100.
Obviously, the manufacturing method of the embedded resistor structure 100 according to the third embodiment of the present application is different from the manufacturing method of the first embodiment mainly in that, in the third step, the side of the through hole 13, which is opened with the second copper plating layer 22 close to the substrate layer 10, is exposed in the through hole 13, and further, when selective electroplating is performed, the resistor material layer 30 is further formed on the surface of the second copper plating layer 22 exposed in the through hole 13. Other steps are similar to those of the first embodiment of the present application, and will not be described again.
Referring to fig. 4a to 4f, a fourth embodiment of the present application provides a method for manufacturing a buried resistor structure 100, which includes the following steps:
in the first step, referring to fig. 4a, a substrate layer 10 is provided, the substrate layer 10 includes a first surface 11 and a second surface 12 opposite to the first surface 11, and a copper-plated material layer 201 is disposed on the first surface 11.
It will be appreciated that the first step in this embodiment provides a single-sided copper-clad substrate.
In the second step, referring to fig. 4b, the copper plating material layer 201 is etched to form a copper plating layer 20. Wherein the copper plating layer 20 is located on the first surface 11 or the second surface 12, the copper plating layer 20 is formed on the first surface 11 in this embodiment.
In the third step, referring to fig. 4c, a plurality of through holes 13 are formed in the substrate layer 10 along a direction perpendicular to the copper plating layer 20.
Wherein, the first surface 11 is provided with a first copper plating layer 21 corresponding to the position where the through hole 13 is opened.
It will be appreciated that the through hole 13 is opened from one side of the substrate layer 10 (e.g. the side of the first surface 11) to the other side (e.g. the side of the second surface 12), and sequentially passes through the first copper plating layer 21 and the substrate layer 10.
In a fourth step, referring to fig. 4d, a first protection layer 41 is formed on the second surface 12 of the substrate layer 10.
It will be appreciated that the first protective layer 41 is disposed such that the side of the first protective layer 41 adjacent to the substrate layer 10 is exposed within the through hole 13.
Fifth, referring to fig. 4e, a resistive material layer 30 is formed on the inner sidewall of the through hole 13, at least a portion of the surface of the copper plating layer 20 away from the substrate layer 10, and the surface of the first protection layer 41 exposed in the through hole 13 (close to the substrate layer 10) by selective electroplating. That is, the resistance material layer 30 at least partially covers the surface of the copper plating layer 20 away from the base material layer 10, the inner side wall of the through hole 13, and the surface of the first protective layer 41 exposed inside the through hole 13.
In a sixth step, referring to fig. 4f, a second passivation layer 42 is formed on the first surface 11 of the substrate layer 10.
It can be understood that the method for manufacturing the embedded resistor structure 100 according to the fourth embodiment of the present application is different from the method for manufacturing the embedded resistor structure according to the first embodiment mainly in that only one surface of the substrate layer 10 provided in the first step of the method is provided with the copper-plated material layer 201, and the method needs to form the first protection layer 41 first and then form the resistor material layer 30, so that a portion of the resistor material layer 30 is formed on the surface of the first protection layer 41 exposed in the through hole 13. Other steps are similar to those of the first embodiment of the present application, and will not be described again.
It is apparent that this embodiment (i.e., the fourth embodiment) is applicable not only to a single-sided board (i.e., a wiring board including only one of the copper plating layers 20) but also to one-sided board (i.e., a wiring board including two of the copper plating layers 20) or a multi-layered board (i.e., a wiring board including a plurality of the copper plating layers 20).
Referring to fig. 1e again, the present application provides a buried resistor structure 100, which is manufactured by the manufacturing method of the buried resistor structure provided in the first embodiment of the present application.
It will be appreciated that in this embodiment, the buried resistor structure 100 is a double-sided buried resistor structure.
Specifically, as shown in fig. 1e, the embedded resistor structure 100 includes: a base material layer 10, a copper plating layer 20, a resistance material layer 30, and a protective layer 40.
The substrate layer 10 includes a first surface 11 and a second surface 12 opposite to the first surface 11.
The material of the base material layer 10 may be one of a flexible material such as PI, PET, PEN, PE, teflon, LCP, PVC and other hard materials such as glass fiber board. In the present embodiment, the material of the base material layer 10 is PI.
The copper plating layer 20 includes a first copper plating layer 21 and a second copper plating layer 22, the first copper plating layer 21 being formed on the first surface 11, and the second copper plating layer 22 being formed on the second surface 12.
The substrate layer 10 is provided with a plurality of through holes 13, and the resistance material layer 30 is formed on the inner side walls of the through holes 13, at least part of the surface of the first copper plating layer 21 away from the substrate layer 10, and at least part of the surface of the second copper plating layer 22 away from the substrate layer 10.
The protective layer 40 is formed on the first surface 11, the second surface 12 and in the through hole 13.
Referring to fig. 2h again, the present application provides a buried resistor structure 100, which is manufactured by the manufacturing method of the buried resistor structure provided in the second embodiment of the present application. The main difference from the buried resistor structure 100 manufactured by the method of the first embodiment is that the substrate layer 10 is provided with a plurality of grooves 14 in addition to a plurality of through holes 13. The resistive material layer 30 is formed on the inner sidewall of the through hole 13, the inner sidewall of the groove 14, and at least a portion of the surface of the copper plating layer 20 remote from the base material layer 10.
Referring to fig. 3e again, the present application provides a buried resistor structure 100 fabricated by the method for fabricating a buried resistor structure according to the third embodiment of the present application. The main difference from the buried resistor structure 100 fabricated using the method of the first embodiment is that at least a portion of the second copper plating layer 22 remains exposed within the via 13. The resistive material layer 30 is formed on the inner side wall of the through hole 13, at least a portion of the surface of the first copper plating layer 21 remote from the base material layer 10, and the surface of the second copper plating layer 22 exposed inside the through hole 13 (near the base material layer 10).
Referring to fig. 4f again, the present application provides a buried resistor structure 100 fabricated by the method for fabricating a buried resistor structure according to the third embodiment of the present application.
In this embodiment, the embedded resistor structure 100 is a single-sided embedded resistor structure.
Specifically, as shown in fig. 4f, the embedded resistor structure 100 includes: a base layer 10, a copper plating layer 20, a resistive material layer 30 and a protective layer 40.
The substrate layer 10 includes a first surface 11 and a second surface 12 opposite to the first surface 11. The resistive material layer 30 is formed on the first surface 11 of the substrate layer 10.
The protective layer 40 includes a first protective layer 41 and a second protective layer 42. The base material layer 10, the copper plating layer 20 and the resistive material layer 30 are all located between the first protective layer 41 and the second protective layer 42.
The substrate layer 10 is provided with a plurality of through holes 13. The resistive material layer 30 is formed on the inner sidewall of the through hole 13 and at least a portion of the copper plating layer 20 is formed on the surface remote from the base material layer 10.
It can be understood that the manufacturing method of the embedded resistor structure 100 according to the second embodiment of the present application is different from the manufacturing method of the first embodiment mainly in that the third, fourth and fifth steps of the method need to first form the grooves 14 on the substrate layer 10. Other steps are similar to those of the first embodiment of the present application, and will not be described again.
By forming the resistance material layer 30 in the through hole 13, or in the groove 14, or above a part of the copper plating layer 20, the application avoids that all copper plating layers 20 are in direct contact with the resistance material layer 30 (including being covered on the resistance material layer 30 or being covered by the resistance material layer 30), so that unnecessary transmission loss is avoided for the circuit which is not in direct contact with the resistance material layer 30, and the transmission speed of the whole circuit is improved. Meanwhile, since most of the resistor material layer 30 is not directly formed on the surface of the substrate layer 10, the space occupied by the embedded resistor on the surface of the circuit board is reduced.
It will be appreciated by persons skilled in the art that the above embodiments have been provided for the purpose of illustration only and not as a definition of the limits of the application, and that appropriate modifications and variations of the above embodiments should be within the scope of the application as claimed.
Claims (10)
1. The manufacturing method of the embedded resistor structure is characterized by comprising the following steps of:
providing a substrate layer, wherein the substrate layer comprises a first surface and a second surface, and the first surface and the second surface are arranged opposite to each other and are provided with copper-plated material layers;
etching the copper plating material layer to form a copper plating layer, wherein the copper plating layer comprises a first copper plating layer and a second copper plating layer, the first copper plating layer is formed on the first surface, and the second copper plating layer is formed on the second surface;
forming a plurality of through holes on the substrate layer along the direction perpendicular to the copper plating layer;
forming a resistive material layer at least on an inner sidewall of the via; a kind of electronic device with high-pressure air-conditioning system
And forming a protective layer to obtain the embedded resistor structure.
2. The method of fabricating a buried resistor structure of claim 1, wherein said step of forming a layer of resistive material on at least an inner sidewall of said via comprises:
forming a layer of resistive material on an inner sidewall of the via, on at least a portion of a surface of the first copper plating layer remote from the substrate layer, and on at least a portion of a surface of the second copper plating layer remote from the substrate layer;
the step of forming a protective layer to obtain the buried resistor structure includes:
and forming a protective layer on the first surface, the second surface and the through hole to obtain the embedded resistor structure.
3. The method of claim 1, wherein prior to the step of forming a plurality of through holes in the base material layer in a direction perpendicular to the copper plating layer, comprising:
a plurality of grooves are formed in the surface of the base material;
forming a partial resistance material layer on the inner side wall of the groove and at least part of the surface of the copper plating layer far away from the substrate layer;
the step of forming a protective layer to obtain the buried resistor structure includes:
and forming a protective layer on the first surface, the second surface, the through hole and the groove to obtain the embedded resistor structure.
4. The method of claim 3, wherein the step of forming a plurality of grooves in the surface of the substrate comprises:
attaching a dry film to the surface of the substrate layer at the position where grooves are not required to be formed;
plasma etching is carried out on the surface of the substrate layer so as to form the groove; a kind of electronic device with high-pressure air-conditioning system
And removing the dry film.
5. The method of claim 3, wherein after the step of forming a portion of the resistive material layer on the inner sidewall of the recess and on the surface of at least a portion of the copper plating layer remote from the substrate layer, further comprising:
and calculating the resistance value of the current embedded resistor formed by the current resistance material layer and the copper plating layer, and determining the number of the through holes according to the resistance value of the current embedded resistor and the resistance value of the required resistor.
6. The method of manufacturing of claim 1, wherein the step of forming a resistive material layer on at least an inner sidewall of the via comprises:
forming a layer of resistive material on an inner sidewall of the via, on at least a portion of a surface of the first copper plating layer remote from the substrate layer, and on a surface of the second copper plating layer exposed within the via;
the step of forming a protective layer to obtain the buried resistor structure includes:
and forming a protective layer on the first surface, the second surface and the through hole to obtain the embedded resistor structure.
7. The method of claim 1, wherein the resistive material layer comprises nickel, chromium, tungsten, nickel-phosphorus alloy, and titanium-tungsten alloy.
8. The manufacturing method of the embedded resistor structure is characterized by comprising the following steps of:
providing a substrate layer, wherein the substrate layer comprises a first surface and a second surface, and the first surface and the second surface are arranged opposite to each other and are provided with copper-plated material layers;
etching the copper plating material layer to form a copper plating layer on the first surface;
forming a plurality of through holes on the substrate layer along the direction perpendicular to the copper plating layer;
forming a first protective layer on the second surface of the substrate layer;
forming a resistive material layer on an inner sidewall of the via, at least a portion of a surface of the copper plating layer remote from the substrate layer, and a surface of the first protective layer exposed within the via;
a second protective layer is formed on the first surface of the substrate layer.
9. A buried resistor structure, characterized in that the buried resistor structure is manufactured by the manufacturing method of the buried resistor structure according to any one of claims 1 to 7.
10. A buried resistor structure, wherein the buried resistor structure is manufactured by the manufacturing method of the buried resistor structure according to claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111223404.3A CN115996522A (en) | 2021-10-20 | 2021-10-20 | Buried resistor structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111223404.3A CN115996522A (en) | 2021-10-20 | 2021-10-20 | Buried resistor structure and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN115996522A true CN115996522A (en) | 2023-04-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111223404.3A Pending CN115996522A (en) | 2021-10-20 | 2021-10-20 | Buried resistor structure and manufacturing method thereof |
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| Country | Link |
|---|---|
| CN (1) | CN115996522A (en) |
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2021
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