CN115996200A - 3D-IC baseband chip, stacked chip and data processing method - Google Patents

Abstract

The invention discloses a 3D-IC baseband chip, a stacked chip and a data processing method, wherein network topology structures are built in logic units to connect network nodes, so that communication among the network nodes does not depend on bus arbitration any more, communication among the network nodes is performed by utilizing the nodes, and the network nodes can establish respective communication paths in parallel in the network topology structures to access storage arrays corresponding to other network nodes without interference and queuing waiting, thereby improving the data processing efficiency. In addition, the storage unit is integrated in a chip and divided into a plurality of storage arrays, and the network node can directly access the storage array corresponding to the network node through the corresponding bump array to perform access operation, so that the efficiency of accessing data from the storage unit is improved, and the calculation performance of the whole 3D-IC baseband chip is further improved.

Description

3D-IC baseband chip, stacked chip and data processing method

Technical Field

The application relates to the technical field of chips, in particular to a 3D-IC baseband chip, a stacked chip and a data processing method.

Background

In the prior art, the baseband chip is typically a lumped baseband chip. For example, in fig. 1, the computing units such as CPU110, soft core array 120, accelerator 130, etc. are interconnected in a lumped manner by a bus within a chip, and a separate memory (not shown) is employed to store data outside the chip.

Based on the structural design, if a plurality of computing units in the chip access the memory outside the chip at the same time, the memory must be queued at the bus, and the memory can be accessed in sequence after waiting for bus arbitration, so that the data processing efficiency of each computing unit is reduced, and the performance of the baseband chip is poor. In addition, the use of off-chip discrete memory has low data access efficiency and high delay, further limiting the performance of the baseband chip.

Disclosure of Invention

The invention provides a 3D-IC baseband chip, a stacked chip and a data processing method, which are used for solving the technical problem of poor performance of the baseband chip caused by low data processing efficiency in the prior art.

According to a first aspect of the present invention, there is provided a 3D-IC baseband chip comprising: the memory unit comprises a plurality of memory arrays, and each memory array is provided with a bump array;

the logic unit comprises a plurality of routing nodes and a plurality of network nodes, wherein the routing nodes are interconnected to form a network topology structure, each routing node is correspondingly connected with one network node, and the network nodes are connected with the corresponding storage arrays through the corresponding bump arrays.

According to a preferred embodiment of the 3D-IC baseband chip of the invention, said logic unit further comprises a memory controller for controlling at least part of said memory array of said memory unit, said memory controller being connected to at least part of said routing nodes and/or at least part of said network nodes, at least part of said network nodes sharing the same memory controller memory access to at least part of said memory array.

According to a preferred embodiment of the 3D-IC baseband chip of the present invention, the logic unit further includes a plurality of memory controllers, each of the routing nodes and/or each of the network nodes is connected to one of the memory controllers, and the network nodes respectively use the respective corresponding memory controllers to access the memory arrays correspondingly controlled by the memory controllers.

According to a preferred embodiment of the 3D-IC baseband chip of the invention, said logic unit further comprises: the buffer is connected with the storage unit through a corresponding bump array and is used for converting the voltage of the storage unit into the voltage of the logic unit; or converting the voltage of the logic cell to the voltage of the memory cell.

According to a preferred embodiment of the 3D-IC baseband chip of the invention, the network node is one of: soft core, accelerator, soft core cluster, accelerator cluster.

According to a preferred embodiment of the 3D-IC baseband chip of the present invention, any one of the network nodes accesses the storage arrays corresponding to the other network nodes in a storage manner through the routing node connected to itself and the routing nodes connected to the other network nodes; or alternatively

And any network node stores and accesses at least one of soft cores, accelerators, soft core clusters and accelerator clusters corresponding to other network nodes through the routing node connected with the network node and the routing nodes connected with other network nodes.

According to a preferred embodiment of the 3D-IC baseband chip of the present invention, the memory unit includes: DRAM cells and NVM cells;

the network node is connected with the storage array corresponding to the DRAM unit through a first bump array, and is connected with the storage array corresponding to the NVM unit through a second bump array;

the memory controller includes: the memory system comprises a DRAM controller and an NVM controller, wherein the DRAM controller controls a memory array corresponding to the DRAM unit, and the NVM controller controls a memory array corresponding to the NVM unit.

According to a preferred embodiment of the 3D-IC baseband chip of the invention,

the network node utilizes the corresponding DRAM controller to store and access a storage array in the DRAM unit correspondingly controlled by the DRAM controller;

the network node uses the corresponding NVM controller to store and access a storage array in the NVM cells correspondingly controlled by the NVM controller.

In a second aspect of the present invention, there is provided a stacked chip comprising a 3D-IC baseband chip of any of the above aspects;

and the processor is connected with the 3D-IC baseband chip of any scheme in a three-dimensional stacking way.

In a third aspect of the present invention, a data processing method is provided, where the data processing method is applied to the 3D-IC baseband chip in any one of the above schemes, and the data processing method includes:

each network node receives the respective data processing request;

based on the data processing requests, each network node accesses the corresponding storage array through the corresponding bump array; and/or

And each network node establishes a respective communication path in a network topology structure to access a storage array corresponding to the respective data processing request based on the respective data processing request.

According to a preferred embodiment of the data processing method according to the present invention, if at least part of the network nodes are connected to the same storage controller, the method further comprises:

at least part of the network nodes arrive at the same storage controller through respective communication paths based on the respective data processing requests, and access the storage arrays corresponding to the respective data processing requests by using the same storage controller.

According to a preferred embodiment of the data processing method of the present invention, if the network nodes are respectively connected to respective storage controllers, the method further comprises:

and each network node arrives at a storage controller corresponding to each data processing request through each communication path based on each data processing request, and accesses a storage array corresponding to each data processing request by using the storage controller corresponding to each data processing request.

According to a preferred embodiment of the data processing method according to the invention, the method further comprises:

if the storage array corresponding to the data processing request belongs to a DRAM unit, the network nodes access the storage arrays corresponding to the data processing requests in the DRAM unit through a first bump array under the drive of a DRAM controller;

and if the storage array corresponding to the data processing request belongs to the NVM unit, the network nodes access the storage arrays corresponding to the data processing requests in the NVM unit through the second bump array under the drive of the NVM controller.

Through one or more technical schemes of the invention, the invention has the following beneficial effects or advantages:

the invention provides a 3D-IC baseband chip, a stacked chip and a data processing method, wherein network topology structures are built in logic units to connect network nodes, so that communication among the network nodes does not depend on bus arbitration any more, communication among the network nodes is performed by utilizing the nodes, and the network nodes can establish respective communication paths in parallel in the network topology structures to access storage arrays corresponding to other network nodes without mutual interference and queuing waiting, thereby improving the data processing efficiency. In addition, the storage unit is integrated in a chip and divided into a plurality of storage arrays, and the network node can directly access the storage array corresponding to the network node through the corresponding bump array to perform access operation, so that the efficiency of accessing data from the storage unit is improved, and the calculation performance of the whole 3D-IC baseband chip is further improved.

The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

fig. 1 shows a schematic diagram of the structure of a lumped baseband chip in the prior art;

FIG. 2A shows a structure of a 3D-IC baseband chip in an embodiment of the invention;

FIG. 2B shows another configuration of a 3D-IC baseband chip in an embodiment of the invention;

FIG. 3A illustrates a network topology in a logical unit in an embodiment of the present invention;

FIG. 3B illustrates a combination of network nodes in a network topology in accordance with an embodiment of the present invention;

FIG. 3C illustrates another combination of network nodes in a network topology in accordance with an embodiment of the present invention;

FIG. 4A illustrates a structure of a logic unit based on the network topology of FIG. 3A in accordance with an embodiment of the present invention;

FIG. 4B illustrates another architecture of a logic unit based on the network topology of FIG. 3A in accordance with an embodiment of the present invention;

figure 4C shows a connection structure of different kinds of memory controllers in a logic unit in an embodiment of the invention,

FIG. 4D illustrates a configuration of logic elements based on the network topology of FIG. 3C in accordance with an embodiment of the present invention;

fig. 5 shows a flow chart of data processing in an embodiment of the invention.

Reference numerals illustrate: CPU110, soft core array 120, accelerator 130, baseboard 200, logic unit 210, routing node 2101, network node 2102, soft core 21021, soft core cluster 21022, accelerator cluster 21023, memory controller 2103, dram controller 21031, nvm controller 20132, buffer 2104, memory unit 220, dram unit 2201, nvm unit 2202.

Detailed Description

In order to solve the technical problem of low data processing efficiency in the prior art, the invention provides a 3D-IC baseband chip, a stacked chip and a data processing method. Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be understood that the description is only illustrative and is not intended to limit the scope of the invention. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the present invention.

Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.

In the context of the present invention, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.

In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.

The technical scheme of the invention is further described in detail through the attached drawings and specific embodiments.

The embodiment discloses a 3D-IC (three-dimensional integrated) baseband chip, wherein the processing bandwidth is more than 1 TB/s. The 3D-IC baseband chip includes: a logic unit 210 and a storage unit 220; the logic unit 210 is used for accessing data from the storage unit 220. The storage unit 220 is used to store data. Fig. 2A shows a structure of the 3D-IC baseband chip of the present embodiment. In fig. 2A, a logic unit 210 is packaged on a substrate 200, and a memory unit 220 is stacked in a vertical direction of the logic unit 210. The logic unit 210 and the memory unit 220 exist in the form of a "wafer" in the chip of the present embodiment. Further, the logic unit 210 and the memory unit 220 are stacked and integrated by bonding.

In the present embodiment, the memory unit 220 includes a plurality of memory arrays, such as two or more memory arrays. Each memory array is provided with a bump array. It is noted that the following embodiments of the present application relate to a number of descriptions, two or more of which are taken as examples. The logic unit 210 includes a plurality of routing nodes 2101 and a plurality of network nodes 2102, where the plurality of routing nodes 2101 are interconnected to form a network topology structure, each routing node 2101 is correspondingly connected to one network node 2102, and the network nodes 2102 are connected to a corresponding storage array through a corresponding bump array. The network topology in the logic unit 210 is described with reference to fig. 3A-3C and is not described here. Since the storage unit 220 allocates a corresponding storage array for each network node 2102 in the chip, the network nodes 2102 do not need to access data by accessing the off-chip memory any network node 2102 can directly access the corresponding storage array through the corresponding bump array to perform data access operation, thereby improving the efficiency of accessing data. In addition, on the basis of the network topology in the logic unit 210 of the present embodiment, when any network node 2102 accesses a storage array other than itself, the storage arrays corresponding to the remaining network nodes 2102 may be stored and accessed in the network topology by the routing node 2101 connected to itself and the routing node 2101 connected to the remaining network node 2102. It can be seen that, in the 3D-IC baseband chip of this embodiment, each network node 2102 may directly access its own corresponding storage array through the corresponding bump array, or may establish respective communication paths in parallel in the network topology structure to access the storage arrays corresponding to other nodes, where access between each network node 2102 is not interfered with each other, and no queuing is required.

As an alternative embodiment, the memory unit 220 in the 3D-IC baseband chip contains a plurality of memory types. Fig. 2B shows another structure of the 3D-IC baseband chip. In fig. 2B, the Memory unit 220 includes a DRAM (Dynamic Random Access Memory) unit 2201 and a NVM (Non-Volatile Memory) unit 2202, but is not limited in type and number. DRAM cell 2201 and NVM cell 2202 are stacked in the vertical direction of logic cell 210, and NVM cell 2202 passes through DRAM cell 2201 and is bonded to logic cell 210 by TSV (Through Silicon Via ) technology. Specifically, DRAM cell 2201 includes a plurality of corresponding memory arrays, each of which has a first bump array disposed thereon. Accordingly, NVM cell 2202 includes a plurality of corresponding memory arrays, each having a second bump array disposed thereon. Based on this configuration, DRAM cell 2201 and NVM cell 2202 are each assigned a corresponding memory array to each network node 2102. Network node 2102 is coupled to a corresponding memory array of DRAM cell 2201 via a first bump array and is capable of performing data access operations by directly accessing the corresponding memory array of DRAM cell 2201 via the first bump array. Accordingly, network node 2102 is coupled to a corresponding memory array of NVM cell 2202 via a second bump array and can directly access its corresponding memory array in NVM cell 2202 via the second bump array for data access operations. While the network node 2102 accesses the storage arrays corresponding to the remaining network nodes 2102, reference may be made to the related description of the foregoing embodiment, which is not repeated here.

The above embodiment describes a specific structure of the memory unit 220, and the following embodiment describes the logic unit 210 in detail.

Fig. 3A shows a network topology in the logic unit 210, which is formed by interconnecting a plurality of routing nodes 2101, and each routing node 2101 is connected to a network node 2102. Since the network node 2102 is one of the following: the soft cores 21021, the accelerators 130, the soft core clusters 21022 and the accelerator clusters 21023 are various combinations of the network nodes 2102 in the network topology structure, and any combination of the soft cores 21021, the accelerators 130, the soft core clusters 21022 and the accelerator clusters 21023 can be adopted. When communicating, any network node 2102 stores and accesses at least one of the soft core 21021, the accelerator 130, the soft core cluster 21022 and the accelerator cluster 21023 corresponding to the other network nodes 2102 through the routing node 2101 connected to the network node 2102 and the routing node 2101 connected to the other network nodes 2102. Fig. 3B shows a combination of network nodes 2102 in a network topology, but without limitation. In the first direction of the network topology, two adjacent routing nodes 2101, one routing node 2101 is connected to the soft core 21021, and the other routing node 2101 is connected to the accelerator 130. The soft core 21021 and the accelerator 130 are spaced apart in a first direction. Based on this structure, any soft core 21021 (or any accelerator 130) can directly access the storage array corresponding to itself, or can access the storage array corresponding to other soft cores 21021 (or other accelerators 130) through its own routing node 2101 and the routing nodes 2101 of other soft cores 21021 (or other accelerators 130). Of course, there are other combinations of network nodes 2102 in the network topology. For example, all routing nodes 2101 are correspondingly connected to their respective soft cores 21021; or each routing node 2101 randomly connects to a soft core 21021 or accelerator 130, etc. The combination mode of the network node 2102 in the network topology structure of this embodiment is flexible and changeable, and can be selected according to actual situations. Fig. 3C shows another combination of network nodes 2102 in a network topology, but without limitation. In a first direction in the network topology, two adjacent routing nodes 2101, one routing node 2101 is connected with a soft core cluster 21022, the other routing node 2101 is connected with an accelerator cluster 21023, and the soft core cluster 21022 and the accelerator cluster 21023 are arranged at intervals in the first direction. Preferably, the soft cores 21021 in each soft core cluster 21022 are interconnected by a first bus through which the soft cores 21021 in the soft core cluster 21022 can access the storage array. Similarly, the accelerators 130 in each accelerator cluster 21023 are interconnected by a second bus through which the accelerators 130 in the accelerator cluster 21023 can access the storage array. Since each soft core 21021 (or each accelerator 130) under the soft core cluster 21022 (or the accelerator cluster 21023) belongs to a small-scale close-range communication node, communication efficiency can be ensured by using a bus. Therefore, the communication mode combining the network topology structure and the bus provides flexible and various communication modes on the basis of ensuring the communication efficiency. Of course, there are other combinations of network nodes 2102 in the network topology. For example, all routing nodes 2101 are correspondingly connected to respective soft core clusters 21022; or two adjacent routing nodes 2101, one routing node 2101 is connected with the soft core cluster 21022, and the other routing node 2101 is connected with the soft core 21021 or the accelerator 130. It should be noted that any combination of network nodes 2102 in the network topology is intended to be within the scope of the present invention.

In the logic unit 210, a memory controller 2103 and a buffer 2104 are also included.

The storage controller 2103 is a "middleware" for the network node 2102 to access the storage arrays, the storage controller 2103 being used to control at least part of the storage arrays in the storage unit 220, or when the logic unit 210 comprises a plurality of storage controllers 2103, each routing node 2101 and/or each of said network nodes 2102 has a corresponding storage controller 2103, the network node 2102 storing access to the corresponding storage array using the storage controller 2103. In this embodiment, the storage controller 2103 and the network node 2102 may have a one-to-many correspondence relationship, or may have a one-to-one correspondence relationship. The correspondence of the storage controller 2103 and the routing node 2101 is similar to that described above.

The storage controller 2103 is configured to control at least a portion of the storage array of the storage units 220 when the storage controller 2103 corresponds to at least a portion of the routing node 2101 and/or at least a portion of the network node 2102. In particular, the storage controller 2103 is connected to at least a portion of the routing nodes 2101 and/or at least a portion of the network nodes 2102, which architecture design can relieve layout wiring stress while ensuring chip computing performance. At least a portion of the network nodes 2102, when accessing the storage array, share the same storage controller 2103 for storage access to at least a portion of the storage array. Fig. 4A illustrates a structure of the logic unit 210 based on the network topology of fig. 3A, but is not limited thereto, and the network nodes 2102 connected to the routing node 2101 in the last row in fig. 3A are taken as an example. In this configuration, each network node 2102 to which the routing node 2101 in the last row is connected is commonly connected to one storage controller 2103. The memory controller 2103 is connected to the buffers 2104 corresponding to the network nodes 2102, and the buffers 2104 corresponding to the network nodes 2102 are connected to the memory array corresponding to the memory unit 220 by bump arrays.

When the storage controllers 2103 are in one-to-one correspondence with the routing nodes 2101 and/or the network nodes 2102, specifically, each routing node 2101 and/or each network node 2102 is connected with one storage controller 2103, so that when the network node 2102 accesses a storage array, the storage controller 2103 is used for storing the storage array which is controlled by the access storage controller 2103 correspondingly. Fig. 4B illustrates another structure of the logic unit 210 based on the network topology of fig. 3A, but is not limited thereto, and the network nodes 2102 connected by the routing node 2101 in the last row in fig. 3A are taken as an example. In this configuration, each network node 2102 to which the routing node 2101 in the last row is connected to one storage controller 2103. The memory controller 2103 is connected to the buffers 2104 corresponding to the network nodes 2102, and the buffers 2104 corresponding to the network nodes 2102 are connected to the memory array corresponding to the memory unit 220 by bump arrays.

It is noted that the different kinds of storage units 220 correspond to the different kinds of storage controllers 2103. Referring to FIG. 4C, which illustrates one connection structure of a heterogeneous memory controller 2103 in a logic unit 210, the memory controller 2103 includes, based on the structure in which the memory unit 220 includes a DRAM cell 2201 and an NVM cell 2202: a DRAM controller 21031 and an NVM controller 20132.DRAM controller 21031 controls the memory array corresponding to DRAM cell 2201 and NVM controller 20132 controls the memory array corresponding to NVM cell 2202.

Further, since the different kinds of storage units 220 correspond to the different kinds of storage controllers 2103, when accessing the different kinds of storage units 220, the network node 2102 uses the corresponding storage controllers 210 to access. Specifically, the network node 2102DRAM controller 21031 stores access to a memory array in a DRAM cell 2201 that the DRAM controller 21031 controls accordingly. The network node 2102 utilizes the corresponding NVM controller 20132 to store access to the storage array in the NVM cells 2202 that the NVM controller 20132 is to control. Thus, since the network node 2102 does not interfere with each other when accessing each storage unit 220, each storage unit 220 can be accessed in parallel to process data, thereby improving the efficiency of data processing.

Since there is a communication manner in which the network topology and the bus are combined in the logic unit 210, fig. 4D shows a structure of the logic unit 210 based on the network topology of fig. 3C, but the structure is not limited thereto, and an arbitrary soft core cluster 21022 connected to the routing node 2101 in the last row in fig. 3C is taken as an example, and other soft core clusters 21022 or accelerator clusters 21023 are similar. In this structure, three soft cores 21021 are included in the soft core cluster 21022, and one soft core 21021 corresponds to one memory controller 2103. The router corresponding to the soft core cluster 21022, three soft cores 21021 in the soft core cluster 21022, and the memory controllers 2103 corresponding to the three soft cores 21021 are interconnected through a first bus. Since the memory controller 2103 includes a DRAM controller 21031 and an NVM controller 20132. So a soft core 21021 is connected to a DRAM controller 21031 and an NVM controller 20132, respectively. The DRAM controller 21031 is connected to a corresponding buffer 2104, the buffer 2104 being connected to a corresponding memory array of DRAM cells 2201 through a corresponding first bump array. NVM controller 20132 connects to corresponding buffers 2104, the buffers 2104 connecting to corresponding memory arrays of NVM cells 2202 through corresponding second bump arrays.

The buffer 2104 is connected between the memory controller 2103 and the memory unit 220. Referring to fig. 4A-4D, in particular, buffers 2104 connect the memory arrays in memory cells 220 through corresponding bump arrays. A buffer 2104 is connected to a memory array by a corresponding bump array. Specifically, based on the structure that memory cell 220 includes DRAM cell 2201 and NVM cell 2202, buffer 2104 is connected to the memory array corresponding to DRAM cell 2201 through a first bump array, and buffer 2104 is connected to the memory array corresponding to DRAM cell 2201 through a second bump array. Since the voltages required for both memory cell 220 and logic cell 210 may be different, buffer 2104 has the effect of voltage coordination. For example, converting the voltage of the memory cell 220 into the voltage of the logic cell 210; or converts the voltage of the logic cell 210 into the voltage of the memory cell 220. The buffer 2104 adapts the memory unit 220 and logic unit 210 unit voltages to each other to reduce the risk of baseband chip burn-out.

The above is a specific structural description of the logic unit 210. The present embodiment connects the network nodes 2102 by constructing a network topology in the logic unit 210, so that the communication between the network nodes 2102 does not depend on bus arbitration any more, but uses the communication between the nodes. Thus, each network node 2102, upon receiving a respective data processing request, is able to independently and concurrently construct a respective communication path in the network topology to access the storage array corresponding to the respective data processing request. Further, since the memory controllers 2103 and the network nodes 2102 are in a one-to-one correspondence, when each network node 2102 accesses a corresponding memory array of a respective data processing request, the corresponding memory array can be independently accessed in parallel by using the respective corresponding memory controller 2103, so that the data processing efficiency is improved, and the computing performance of the 3D-IC baseband chip is further improved.

Based on the same inventive concepts as one or more of the above embodiments, this embodiment also provides a stacked chip including the 3D-IC baseband chip and the processor described in accordance with any of the above embodiments. The processor is connected with the 3D-IC baseband chip three-dimensional stack described in any of the embodiments above.

Based on the same inventive concept as one or more embodiments described above, this embodiment also provides a data processing method, which is applied to the 3D-IC baseband chip described in any one of the embodiments described above. Referring to fig. 5, the method specifically comprises the steps of:

in step 501, each network node 2102 receives a respective data processing request.

Specifically, the data processing request is specifically: requesting to perform read-write operation on a storage array corresponding to the network node 2102; or requests to read and write operations to the storage arrays corresponding to other network nodes 2102. Each network node 2102 has different access patterns according to different data processing requests. Further, if all the data processing requests in each network node 2102 are requests to perform read/write operations on the storage array corresponding to the request, step 502 is executed. If all the data processing requests in each network node 2102 are requests to perform read/write operations on the storage arrays corresponding to other network nodes 2102, step 503 is executed. Of course, if the data processing request in each network node 2102 is a request to perform a read/write operation on a storage array corresponding to itself, and is a request to perform a read/write operation on a storage array corresponding to another network node 2102, step 502 and step 503 are executed in parallel.

In step 502, each network node 2102 accesses its corresponding storage array through its corresponding bump array based on its respective data processing request. As can be seen, since the storage unit allocates a corresponding storage array for each network node 2102 in the chip, the bump array corresponding to each network node 2102 directly accesses the corresponding storage array to perform the access operation, so that the efficiency of accessing data from the storage unit is improved, and the computing performance of the whole 3D-IC baseband chip is further improved.

In step 503, each network node 2102 establishes a respective communication path in the network topology based on the respective data processing request to access the storage array corresponding to the respective data processing request. Because the network topology changes the communication manner between the network nodes 2102, the communication between the network nodes 2102 does not rely on bus arbitration, but uses the communication between the nodes. Therefore, based on the respective data processing requests, each network node 2102 can independently and parallelly establish respective communication paths in the network topology structure to access the storage arrays corresponding to the respective data processing requests, accesses among the network nodes 2102 are not interfered with each other, queuing is not needed, and therefore data processing efficiency is improved, and computing performance of the 3D-IC baseband chip is further improved.

Since the memory unit 220 of the present embodiment 3D-IC baseband chip includes a DRAM unit 2201 and an NVM unit 2202. While DRAM cell 2201 and NVM cell 2202 are each assigned a corresponding memory array for each network node 2102. Since the memory arrays corresponding to different memory cells 220 are accessed, their corresponding memory controllers 2103 need to be utilized, while DRAM cell 2201 corresponds to DRAM controller 21031 and NVM cell 2202 corresponds to NVM controller 20132. Therefore, if the memory array corresponding to the data processing request belongs to the DRAM unit 2201, each network node 2102 accesses the memory array corresponding to the data processing request in the DRAM unit 2201 through the first bump array under the driving of the DRAM controller 21031; if the storage array corresponding to the data processing request belongs to the NVM unit 2202, each network node 2102 accesses the storage array corresponding to the data processing request in the NVM unit 2202 through the second bump array under the driving of the NVM controller 21032. Thus, since the network node 2102 does not interfere with each other when accessing each storage unit 220, each storage unit 220 can be accessed in parallel to process data, thereby improving the efficiency of data processing.

As an alternative embodiment, the memory controller 2103 and the network node 2102 may be a "one-to-many" correspondence, or a "one-to-one" correspondence, as in the 3D-IC baseband chip. And the correspondence of the storage controller 2103 and the routing node 2101 is similar to that described above.

When the storage controller 2103 and the network node 2102 are in a "one-to-many" correspondence, if at least some of the network nodes 2102 are connected to the same storage controller 2103. Based on this configuration, since the same memory controller 2103 needs to respond to the data processing requests of at least some of the network nodes 2012 in each network node 2102 one by one, at least some of the network nodes 2102 need to be queued if the memory controller 2103 is in a busy state when the memory controller 2103 is utilized. In particular implementations, at least some of network nodes 2102 arrive at the same memory controller 2103 directly and/or via respective communication paths based on respective data processing requests and queue and utilize the same memory controller 2103 to access respective memory arrays corresponding to the respective data processing requests.

When the storage controllers 2103 and the network nodes 2102 are in a one-to-one correspondence, each network node 2102 is connected to a respective storage controller 2103. Because the storage controllers 2103 and the network nodes 2102 are in one-to-one correspondence with each other, when each network node 2102 reaches the storage controller 2103 corresponding to each data processing request directly and/or through each communication path based on each data processing request, each storage controller 2103 is used to independently and parallelly access the storage array corresponding to each data processing request. It can be seen that, in this embodiment, each network node 2102 can access the related storage array by using the corresponding storage controller 2103 on the basis of establishing the communication paths in parallel, so that the 3D-IC baseband chip of this embodiment can support each network node 2102 to process data in parallel, thereby improving the data processing efficiency of each network node 2102 and further improving the computing performance of the 3D-IC baseband chip.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims (13)

1. A 3D-IC baseband chip, comprising: the memory unit comprises a plurality of memory arrays, and each memory array is provided with a bump array;

the logic unit comprises a plurality of routing nodes and a plurality of network nodes, wherein the routing nodes are interconnected to form a network topology structure, each routing node is correspondingly connected with one network node, and the network nodes are connected with the corresponding storage arrays through the corresponding bump arrays.

2. The 3D-IC baseband chip of claim 1, wherein the memory is configured to store, in the memory,

the logic unit further comprises a memory controller for controlling at least part of the memory array of the memory unit, the memory controller being connected to at least part of the routing nodes and/or at least part of the network nodes, at least part of the network nodes sharing the same memory controller memory access to at least part of the memory array.

3. The 3D-IC baseband chip of claim 2, wherein,

the logic unit further comprises a plurality of storage controllers, each routing node and/or each network node is connected with one storage controller, and the network nodes respectively use the corresponding storage controllers to store and access the storage arrays correspondingly controlled by the storage controllers.

4. The 3D-IC baseband chip of claim 2 or 3, wherein the logic unit further comprises: the buffer is connected with the storage unit through a corresponding bump array and is used for converting the voltage of the storage unit into the voltage of the logic unit; or converting the voltage of the logic cell to the voltage of the memory cell.

5. The 3D-IC baseband chip of claim 4, wherein the network node is one of: soft core, accelerator, soft core cluster, accelerator cluster.

6. The 3D-IC baseband chip of claim 5, wherein any one of the network nodes stores and accesses a storage array corresponding to the remaining network nodes through the routing node connected to itself and the routing nodes connected to the remaining network nodes; or alternatively

And any network node stores and accesses at least one of soft cores, accelerators, soft core clusters and accelerator clusters corresponding to other network nodes through the routing node connected with the network node and the routing nodes connected with other network nodes.

7. The 3D-IC baseband chip of claim 6, wherein the memory unit comprises: DRAM cells and NVM cells;

the network node is connected with the storage array corresponding to the DRAM unit through a first bump array, and is connected with the storage array corresponding to the NVM unit through a second bump array;

the memory controller includes: the memory system comprises a DRAM controller and an NVM controller, wherein the DRAM controller controls a memory array corresponding to the DRAM unit, and the NVM controller controls a memory array corresponding to the NVM unit.

8. The 3D-IC baseband chip of claim 7, wherein the memory is configured to store, in the memory,

the network node utilizes the corresponding DRAM controller to store and access a storage array in the DRAM unit correspondingly controlled by the DRAM controller;

the network node uses the corresponding NVM controller to store and access a storage array in the NVM cells correspondingly controlled by the NVM controller.

9. A stacked chip comprising a 3D-IC baseband chip according to any of the preceding claims 1-8;

a processor in three-dimensional stacked connection with the 3D-IC baseband chip of any of the preceding claims 1-8.

10. A data processing method, wherein the data processing method is applied to the 3D-IC baseband chip of any one of claims 1 to 8, and the data processing method comprises:

each network node receives the respective data processing request;

based on the data processing requests, each network node accesses the corresponding storage array through the corresponding bump array; and/or

And each network node establishes a respective communication path in a network topology structure to access a storage array corresponding to the respective data processing request based on the respective data processing request.

11. The data processing method of claim 10, wherein if at least some of the network nodes are connected to the same storage controller, the method further comprises:

at least part of the network nodes arrive at the same storage controller through respective communication paths based on the respective data processing requests, and access the storage arrays corresponding to the respective data processing requests by using the same storage controller.

12. A data processing method according to claim 10 or 11, wherein if the network nodes are each connected to a respective storage controller, the method further comprises:

and each network node arrives at a storage controller corresponding to each data processing request through each communication path based on each data processing request, and accesses a storage array corresponding to each data processing request by using the storage controller corresponding to each data processing request.

13. The data processing method of claim 10, wherein the method further comprises:

if the storage array corresponding to the data processing request belongs to a DRAM unit, the network nodes access the storage arrays corresponding to the data processing requests in the DRAM unit through a first bump array under the drive of a DRAM controller;

and if the storage array corresponding to the data processing request belongs to the NVM unit, the network nodes access the storage arrays corresponding to the data processing requests in the NVM unit through the second bump array under the drive of the NVM controller.

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