CN115996048B - Switching circuit, control method and chip of field effect transistor - Google Patents

Switching circuit, control method and chip of field effect transistor Download PDF

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Publication number
CN115996048B
CN115996048B CN202310102324.5A CN202310102324A CN115996048B CN 115996048 B CN115996048 B CN 115996048B CN 202310102324 A CN202310102324 A CN 202310102324A CN 115996048 B CN115996048 B CN 115996048B
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Prior art keywords
field effect
effect transistor
voltage
current
detection
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CN202310102324.5A
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CN115996048A (en
Inventor
罗冬哲
蔡月冰
刘勇
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Shenzhen Siyuan Semiconductor Co ltd
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Shenzhen Siyuan Semiconductor Co ltd
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Priority to CN202310102324.5A priority Critical patent/CN115996048B/en
Priority to CN202311170874.7A priority patent/CN117155366A/en
Priority to CN202311169811.XA priority patent/CN117155365A/en
Publication of CN115996048A publication Critical patent/CN115996048A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H03K17/04106—Modifications for accelerating switching without feedback from the output circuit to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0081—Power supply means, e.g. to the switch driver
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The embodiment of the invention discloses a switching circuit, a control method and a chip of a field effect transistor, wherein the switching circuit comprises a charge pump, the field effect transistor and an opening degree detection circuit; the opening degree detection circuit is used for detecting the voltage of the grid electrode of the field effect transistor. When the field effect transistor needs to be controlled to be conducted, the charge pump is used for starting current to charge the grid electrode of the field effect transistor so as to control the field effect transistor to be conducted; if the opening degree detection circuit detects that the voltage of the grid electrode of the field effect tube is larger than a grid voltage threshold value, the charge pump is converted from the opening current to the maintaining current to charge the grid electrode of the field effect tube so as to maintain the field effect tube to be kept on; wherein the sustain current is less than the on current. The embodiment of the invention gives consideration to the opening speed and the power consumption of the field effect transistor.

Description

Switching circuit, control method and chip of field effect transistor
Technical Field
The invention relates to the technical field of field effect transistors, in particular to a switching circuit, a control method and a chip of a field effect transistor.
Background
Field effect transistors are widely used in integrated circuits.
In the prior art, when a field effect transistor needs to be started, the grid voltage of the field effect transistor is loaded to a certain high level through a driving circuit, so that the field effect transistor is started; when the field effect transistor needs to be turned off, the grid voltage of the field effect transistor is pulled down to 0 through the driving circuit, so that the field effect transistor is turned off.
However, the driving circuit consumes more power when the fet is maintained in an on state.
Disclosure of Invention
Based on the above-mentioned current situation, a main objective of the embodiments of the present invention is to provide a switching circuit, a control method and a chip of a field effect transistor, so as to consider the opening speed and the power consumption of the field effect transistor.
In order to achieve the above object, the embodiment of the present invention adopts the following technical scheme:
a switching circuit of a field effect transistor comprises a charge pump, the field effect transistor and an opening degree detection circuit; the opening degree detection circuit is used for detecting the voltage of the grid electrode of the field effect transistor. When the field effect transistor needs to be controlled to be conducted, the charge pump is used for starting current to charge the grid electrode of the field effect transistor so as to control the field effect transistor to be conducted; if the opening degree detection circuit detects that the voltage of the grid electrode of the field effect tube is larger than a grid voltage threshold value, the charge pump is converted from the opening current to the maintaining current to charge the grid electrode of the field effect tube so as to maintain the field effect tube to be kept on; wherein the sustain current is less than the on current.
A control method of a switching circuit of a field effect transistor, wherein the switching circuit comprises a charge pump and the field effect transistor, and the switching circuit further comprises an opening degree detection circuit for detecting the voltage of a grid electrode of the field effect transistor. When the field effect transistor needs to be controlled to be conducted, the charge pump is used for starting current to charge the grid electrode of the field effect transistor so as to control the field effect transistor to be conducted; if the opening degree detection circuit detects that the voltage of the grid electrode of the field effect tube is larger than a grid voltage threshold value, the charge pump is converted from the opening current to the maintaining current to charge the grid electrode of the field effect tube so as to maintain the field effect tube to be kept on; wherein the sustain current is less than the on current.
A chip comprising any one of the switching circuits of the field effect transistor.
In this embodiment, since the on current is larger, charging of the gate of the fet can be completed in a shorter time, so that the fet is opened faster; after the field effect transistor is turned on, the conduction of the field effect transistor is maintained by smaller maintaining current, so that the power consumption of the circuit can be reduced, and the embodiment gives consideration to the turn-on speed and the power consumption of the field effect transistor.
Other advantages of the present invention will be set forth in the description of specific technical features and solutions, by which those skilled in the art should understand the advantages that the technical features and solutions bring.
Drawings
Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. In the figure:
fig. 1 is a switching circuit of a field effect transistor according to a preferred embodiment of the present invention;
fig. 2 is a switching circuit of a field effect transistor according to another preferred embodiment of the present invention;
FIG. 3 is a switching circuit of a field effect transistor according to another preferred embodiment of the present invention;
fig. 4 is a switching circuit of a field effect transistor according to another preferred embodiment of the present invention;
fig. 5 is a switching circuit of a field effect transistor according to another preferred embodiment of the present invention;
fig. 6 is a switching circuit of a field effect transistor according to another preferred embodiment of the present invention;
FIG. 7 is a graph showing the relationship between the parasitic capacitance of the gate of the NMOS field effect transistor and different gate-source voltages according to a preferred embodiment of the present invention;
fig. 8 is a switching circuit of a field effect transistor according to another preferred embodiment of the present invention;
fig. 9 is a switching circuit of a field effect transistor according to another preferred embodiment of the present invention;
fig. 10 is a switching circuit of a field effect transistor according to another preferred embodiment of the present invention.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in order to avoid obscuring the present invention, and in order to avoid obscuring the present invention, well-known methods, procedures, flows, and components are not presented in detail.
Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".
In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
Fig. 1 is a switching circuit of a field effect transistor according to an embodiment of the present invention, which can be applied to circuits of various electronic devices, such as integrated circuits or discrete component circuits. The fet Ms may be a power type fet or a non-power type fet, and may be an N-channel type fet or a P-channel type fet. The switching circuit comprises a charge pump 100, a field effect transistor Ms and an opening degree detection circuit 200; the current input end of the field effect transistor Ms is connected with the input end Vin for inputting the input voltage, and the current output end of the field effect transistor Ms is connected with the output end Vout for outputting the output voltage; the output end of the charge pump 100 is connected with the grid Vgate of the field effect transistor Ms; the input end can be connected with a power supply, and the output end can be connected with a post-stage circuit; the opening degree detection circuit 200 is used for detecting the voltage of the grid electrode of the field effect transistor Ms; the parasitic capacitance of the gate of the field effect transistor Ms is Cpar.
When the field effect transistor Ms needs to be controlled to be turned on, the charge pump 100 charges the grid electrode of the field effect transistor Ms with a starting current so as to control the field effect transistor to be turned on, and the voltage of the grid electrode of the field effect transistor Ms is gradually increased; in addition, the turn-on detection circuit 200 starts to detect the voltage of the gate of the fet Ms, and if the turn-on detection circuit 200 detects that the voltage of the gate of the fet Ms is greater than the gate voltage threshold, the charge pump 100 changes from turning on the current to charging the gate of the fet Ms with the sustain current to maintain the fet Ms on; wherein the holding current is less than the on current; the gate voltage threshold is a voltage at which the field effect transistor Ms can be turned on. In some embodiments, the fet Ms is an NMOS fet, and since the voltage at the source of the fet Ms is the input voltage, the gate voltage threshold is an offset voltage added to the input voltage, for example, the offset voltage may be 2 times the on threshold Vth of the fet Ms. In this embodiment, since the on current is larger, the charging of the gate of the fet Ms can be completed in a shorter time, so that the fet Ms is turned on faster; after the fet Ms is turned on, the turn-on of the fet Ms is maintained with a smaller holding current, so that the power consumption of the circuit can be reduced, that is, the embodiment takes into account the turn-on speed and the power consumption of the fet Ms.
Fig. 2 is a switching circuit of a field effect transistor according to another embodiment of the present invention, the switching circuit includes a control module 300, and the opening degree detecting circuit 200 includes an opening degree detecting unit and a detecting switch S3. When the fet Ms needs to be controlled to turn off, the detection switch S3 is turned off, so that the turn-on detection circuit 200 turns off and stops detecting the voltage of the gate of the fet Ms. When the field effect transistor Ms needs to be controlled to be turned on, the detection switch S3 is turned on to enable the opening degree detection circuit 200 to be turned on and start to detect the voltage of the gate of the field effect transistor Ms; if the gate of the fet Ms is charged to a voltage less than the gate voltage threshold, the detection switch S3 is kept turned on to control the opening degree detection circuit 200 to keep detecting the voltage of the gate of the fet Ms; if the gate of the fet Ms is charged to a voltage greater than the gate voltage threshold, the turn-on detection circuit 200 may also stop detecting the voltage of the gate of the fet Ms; for example, the control module 300 controls the detection switch S3 to turn off, thereby turning off the opening degree detection circuit 200, and further stopping the opening degree detection circuit 200 from detecting the voltage of the gate of the fet Ms. Thus, the power consumption of the switch circuit can be reduced on the basis of realizing the opening degree detection. In this embodiment, after the turn-on detection circuit 200 detects whether the gate voltage of the fet Ms is greater than the gate voltage threshold, a corresponding signal may be sent to the control module 300, so that the control module 300 controls the charge pump 100 to output the turn-on current or the sustain current accordingly.
Fig. 3 is a switching circuit of a field effect transistor according to another embodiment of the present invention, in which an opening degree detecting circuit 200 includes a first detecting PMOS transistor Mp3, a second detecting PMOS transistor Mp4, and a detecting resistor Rs; the source electrode of the first detection PMOS tube MP3 is connected with the grid electrode of the field effect tube Ms, the drain electrode of the first detection PMOS tube MP3 is respectively connected with the grid electrode of the first detection PMOS tube MP3 and the source electrode of the second detection PMOS tube MP4, the grid electrode of the second detection PMOS tube MP4 is connected with the source electrode of the field effect tube Ms, and the drain electrode is grounded through a detection resistor Rs. In this embodiment, the on threshold values of the first detection PMOS transistor Mp3 and the second detection PMOS transistor Mp4 are the same, and are Vth and the same as the on threshold value of the field effect transistor Ms, so the gate voltage threshold value may be expressed as 2×vth. When the voltage of the gate of the field effect transistor Ms exceeds the gate voltage threshold value by 2×vth, the first detection PMOS transistor Mp3 and the second detection PMOS transistor Mp4 are turned on, and the current flows through the detection resistor Rs via the gate of the field effect transistor Ms, the first detection PMOS transistor Mp3 and the second detection PMOS transistor Mp4, so that the voltage on the detection resistor Rs is at a high level; accordingly, if the voltage of the detection resistor Rs is detected to be high, it can be determined that the voltage of the gate of the field-effect transistor Ms is greater than the gate voltage threshold. When the voltage of the gate of the field effect transistor Ms is less than 2×vth of the gate voltage threshold, the first detection PMOS transistor Mp3 and the second detection PMOS transistor Mp4 are disconnected, and no current flows through the detection resistor Rs, so that the voltage on the detection resistor Rs is low level; accordingly, if the voltage of the detection resistor Rs is detected to be low, it can be determined that the voltage of the gate of the field-effect transistor Ms is smaller than the gate voltage threshold.
In an alternative embodiment of the switching circuit of fig. 3, the first detection PMOS transistor Mp3 may be replaced by a detection diode, in which the anode of the detection diode is connected to the gate of the field effect transistor Ms and the cathode is connected to the source of the second detection PMOS transistor Mp 4. Further, the gate voltage threshold in this alternative embodiment is vth+vd, where Vd is the turn-on threshold of the sense diode.
As shown in fig. 3, in the switch circuit of this embodiment, the opening degree detection circuit 200 further includes a detection switch S3, where after the detection switch S3 is connected in series with the detection resistor Rs, the detection switch S3 is connected between the drain electrode of the second detection PMOS transistor Mp4 and ground, for example, the drain electrode of the second detection PMOS transistor Mp4 is grounded sequentially through the detection switch S3 and the detection resistor Rs; the control module 300 controls the on and off of the opening degree detection circuit 200 by controlling the on and off of the detection switch S3. For example, when the fet Ms needs to be turned on, the control module 300 controls the detection switch S3 to be turned on, so that the turn-on detection circuit 200 starts to detect the gate voltage of the fet Ms. If the turn-on detection circuit 200 detects that the gate of the fet Ms is charged to a voltage greater than the gate voltage threshold, the control module 300 controls the detection switch S3 to be turned off, so that the turn-on detection circuit 200 stops detecting the voltage of the gate of the fet Ms, thereby saving power consumption.
Fig. 4 is a schematic diagram of a switching circuit of a field effect transistor according to another embodiment of the present invention, the switching circuit further including a current source 500, the current source 500 being a mirror current source, and the charge pump 100 being configured to provide a desired current to the current source 500; the current source 500 comprises a first reference leg 510 for providing a first reference current, a second reference leg 520 for providing a second reference current, and an output leg 530; wherein the first reference current is less than the second reference current. When the fet Ms needs to be controlled to be turned on, if the voltage of the gate of the fet Ms is smaller than the gate voltage threshold (e.g., the turn-on detection circuit 200 detects that the voltage of the gate is smaller than the gate voltage threshold), the output branch 530 copies the sum of the first reference current and the second reference current as the turn-on current, so that the gate of the fet Ms can be charged to a voltage greater than the gate voltage threshold at a higher speed, and the fet Ms is turned on rapidly. If the gate of the fet Ms is charged to a voltage greater than the gate voltage threshold (e.g., the turn-on detection circuit 200 detects that the voltage of the gate is greater than the gate voltage threshold), the output branch 530 only copies the first reference current as the sustain current to maintain the fet Ms on, which can save power consumption. In this embodiment, the first reference current and the second reference current are output through the first reference branch 510 and the second reference branch 520, so that the output branch 530 copies and outputs the maintaining current and the starting current, thereby accurately controlling the charging current provided by the charge pump 100 to the gate of the fet Ms, and further accurately controlling the conduction or maintaining conduction of the NMOS switch.
FIG. 5 is a schematic diagram of a switching circuit of a FET according to another embodiment of the present invention, the switching circuit further comprising a current source 500, the current source 500 being a mirrored current source; the control module 300 includes an RS flip-flop 310, and the charge pump 100 is configured to provide a desired current to the current source 500. The current source 500 comprises a first reference leg 510 for providing a first reference current, a second reference leg 520 for providing a second reference current, a reference current switch S1 for controlling the second reference leg 520 to be turned on and off, and an output leg 530; wherein the first reference current is less than the second reference current; the reset terminal and the set terminal of the RS flip-flop 310 are used for inputting the voltage of the detection resistor RS and the control signal on_slot of the RS flip-flop 310, respectively, and the output terminal is used for controlling the reference current switch S1 and the detection switch S3, wherein the control signal of the RS flip-flop 310 is a rising edge extraction signal of the switching signal of the fet Ms, that is, when the switching signal of the fet Ms is a rising edge, the rising edge extraction signal is at a high level with a set width, and when other states of the switching signal of the fet Ms, such as a stable level or a falling edge, the rising edge extraction signal is at a low level. When the fet Ms needs to be controlled to be turned on, the switching signal of the fet Ms is an on signal, and the rising edge of the on signal is used as a control signal of the RS flip-flop 310, and the control signal causes the output end of the RS flip-flop 310 to output a trigger on signal, so as to control the reference current switch S1 and the detection switch S3 to be turned on, so that the output branch 530 replicates the sum of the first reference current and the second reference current as an on current, to rapidly charge the gate of the fet Ms, and the turn-on detection circuit 200 starts to detect the voltage of the gate of the fet Ms; in this way, the charge pump 100 starts to charge the gate of the fet Ms with an on-current, and the voltage of the gate will gradually rise. When the gate of the field effect transistor Ms is smaller than the gate voltage threshold, the first detection PMOS transistor Mp3 and the second detection PMOS transistor Mp4 are not turned on, and no current passes through the detection resistor Rs, so that the voltage of the detection resistor Rs is low, the output end of the Rs trigger 310 is caused to still maintain to output the trigger on signal, and the reference current switch S1 and the detection switch S3 are kept on. When the gate of the fet Ms is greater than the gate voltage threshold, the first detecting PMOS Mp3 and the second detecting PMOS Mp4 are turned on, and the current passes through the detecting resistor Rs, so that the voltage of the detecting resistor Rs is at a high level, the output terminal of the Rs flip-flop 310 is prompted to output a trigger off signal, the reference current switch S1 and the detecting switch S3 are controlled to be turned off, so that the output branch 530 replicates the first reference current as the maintaining current, to maintain the fet Ms to be turned on, and the opening degree detecting circuit 200 stops detecting the voltage of the gate of the fet Ms.
Fig. 6 is a switching circuit of a field effect transistor according to another embodiment of the present invention, which is a more specific switching circuit based on the switching circuit of the embodiment of fig. 4. The switching circuit further includes a clamp circuit 400. When it is necessary to control the fet Ms to turn off, the output branch 530 copies the first reference current as the holding current to supply the current required for clamping, or the gate voltage of the fet Ms required for clamping, to the clamping circuit 400, so that the clamping circuit 400 clamps the gate of the fet Ms to a voltage that causes the fet Ms to be in an off state. When the fet Ms needs to be controlled to turn on, the clamp circuit 400 stops clamping the gate of the fet Ms, and the charge pump 100 charges the gate of the fet Ms with an on current (i.e., charges the parasitic capacitor Cpar of the gate), so that the gate-source voltage is greater than the on threshold of the fet Ms, to control the fet Ms to turn on.
If the fet Ms is an NMOS fet, when the fet Ms needs to be controlled to be turned off, the clamp circuit 400 clamps the gate of the fet Ms to a voltage that causes the fet Ms to be in an off state with reference to the input voltage, and at this time, the voltage of the gate is greater than or equal to the input voltage, that is, the gate-source voltage is greater than or equal to 0, and the drain does not output a voltage because the fet Ms is turned off.
Fig. 7 is a graph showing the relationship between the parasitic capacitance Cpar of the gate electrode of the NMOS field effect transistor Ms and the different gate-source voltages Vgs, and it can be seen from the graph that the parasitic capacitance Cpar of the gate electrode is minimized when the gate-source voltage is near 0, and the amount of charge required for the gate electrode to charge from one gate-source voltage to the other gate-source voltage is the area size enclosed by the vertical line, the curve and the abscissa where the two voltages are located. In this embodiment, the gate-source voltage when the fet Ms is turned on is denoted as Vg (for example, the magnitude is 2×vth, where Vth is the on threshold of the fet Ms, that is, the gate-source voltage required for critical conduction), and the charge amount of the charge pump 100 charging the gate is approximately a shadow region within the range of L1; however, in the conventional known technology, since the potential of the gate is set to 0 when the NMOS is turned off, the gate-source voltage is about-Vin (e.g., -5V), and when the fet Ms needs to be turned on, the charge pump charges the gate with an amount of charge about in the shadow region of L2; compared with the prior art, in the present embodiment, the amount of charge transferred from the charge pump 100 to the gate of the fet Ms is greatly reduced, so that the fet Ms can be turned on quickly, and the method is very suitable for the scene where the fet Ms needs to be turned on quickly; for example, in the NVDC architecture, the fet Ms connected to vsys and vbat may be controlled to be turned on quickly, so as to avoid voltage drop of vsys, and even serious system downtime.
As shown in fig. 6, in another embodiment of the present invention, the clamp circuit 400 includes a clamp unit 410 and a clamp switch S2; when the fet Ms needs to be controlled to be turned off, the control module 300 controls the clamp switch S2 to be turned on, and the charge pump 100 charges the gate of the fet Ms with a sustain current, so that the voltage of the gate of the fet Ms is sufficient to turn on the clamp unit 410, i.e. the clamp circuit 400 is turned on, so that the clamp circuit 400 clamps the gate of the fet Ms. When the fet Ms needs to be controlled to be turned on, the control module 300 controls the clamp switch S2 to be turned off, so that the clamp unit 410 is turned off, i.e., the clamp circuit 400 is turned off, so that the clamp circuit 400 stops clamping the gate of the fet Ms. In this embodiment, the control module 300 may be configured by a logic circuit, for example, including an inverter, and since the on states of the fet Ms and the clamp switch S2 are just opposite, for example, the clamp switch S2 is turned off when the fet Ms is turned on (or the clamp switch S2 is turned on when the fet Ms is turned off), a signal obtained by inverting the control signal of the fet Ms may be used as the control signal for controlling the clamp switch S2.
Fig. 8 is a more specific embodiment based on the embodiment of fig. 6, in which the clamping unit 410 includes a clamping diode D, and the clamping diode D and the clamping switch S2 are connected in series to form the clamping circuit 400; for example, the anode of the clamp diode D is connected to the gate of the fet Ms, and the cathode is connected to the source of the fet Ms through the clamp switch S2. When the fet Ms needs to be controlled to be turned off, the control module 300 controls the clamp switch S2 to be turned on, and the charge pump 100 charges the gate of the fet Ms with a sustain current, so that the voltage of the gate of the fet Ms is sufficient to turn on the clamp diode D, that is, the clamp circuit 400 is turned on, so that the clamp circuit 400 clamps the gate of the fet Ms; since the voltage at the output of the charge pump 100 is sufficient to turn on the clamp diode D, the clamp diode D is turned on, and the gate of the fet Ms is clamped to a voltage, such as vin+vd, with reference to the input voltage, where Vd is the conduction voltage drop of the clamp diode D. When the fet Ms needs to be controlled to be turned on, the control module 300 controls the clamp switch S2 to be turned off, so that the clamp diode D is turned off, i.e., the clamp circuit 400 is turned off, so that the clamp circuit 400 stops clamping the gate of the fet Ms.
Fig. 9 is a more specific embodiment based on the embodiment of fig. 6, in the switch circuit of this embodiment, the clamp unit 410 includes a clamp PMOS transistor Mclp and a voltage source V1, the source of the clamp PMOS transistor Mclp is connected to the gate of the field effect transistor Ms, the gate of the clamp PMOS transistor Mclp is connected to the source of the field effect transistor Ms through the voltage source, and the drain of the clamp PMOS transistor Mclp is grounded through the clamp switch S2; the voltage source is used for providing a voltage with the magnitude equal to the difference between the input voltage and the starting threshold value of the clamping PMOS tube Mclp, namely Vin-Vth, for the grid electrode of the clamping PMOS tube Mclp by taking the input voltage as a reference; the voltage provided by the output end of the charge pump 100 is sufficient to turn on the clamp PMOS transistor Mclp, i.e., is greater than the sum of the voltage source and the turn-on threshold of the clamp PMOS transistor Mclp. When the fet Ms needs to be controlled to be turned off, the control module 300 controls the clamp switch S2 to be turned on, and the charge pump 100 charges the gate of the fet Ms with a holding current, so that the voltage of the gate of the fet Ms is sufficient to turn on the clamp PMOS Mclp, that is, the clamp circuit 400 is turned on, so that the clamp circuit 400 clamps the gate of the fet Ms; since the voltage at the output end of the charge pump 100 is sufficient to turn on the clamp PMOS transistor Mclp, the clamp PMOS transistor Mclp is turned on, and the gate of the clamp PMOS transistor Mclp is clamped at the sum of the voltage source and the turn-on threshold of the clamp PMOS transistor Mclp, that is: v1+vth; since v1=vin-Vth, the clamp PMOS transistor Mclp is clamped at (Vin-Vth) +vth, i.e., vin. When the fet Ms needs to be controlled to be turned on, the control module 300 controls the clamp switch S2 to be turned off, so that the clamp PMOS Mclp is turned off, i.e., the clamp circuit 400 is turned off, so that the clamp circuit 400 stops clamping the gate of the fet Ms.
Fig. 10 is a schematic diagram showing a switching circuit of a fet according to another embodiment of the present invention, in which the charge pump 100 includes an output capacitor Ccp 120 and a charge generation circuit 110, the output capacitor 120 is connected across an output terminal of the charge generation circuit 110 and a source of the fet Ms, that is, one end of the output capacitor 120 is connected to an output terminal of the charge generation circuit 110, and the other end is connected to an input terminal Vin, and the charge generation circuit 110 is used for adjusting an amount of charge of the output capacitor 120 so that the output capacitor 120 maintains a predetermined voltage difference on a reference of an input voltage; the target voltage Vt of the output capacitor 120 may be expressed as: vt=vin+ [ delta ] V; the voltage at the output terminal of the charge generation circuit 110 may be obtained by feedback, and then the charge generation circuit 110 adjusts the voltage at the output terminal of the charge generation circuit 110 to maintain the target voltage by comparing the target voltage with the voltage obtained by feedback. In this embodiment, the output end of the charge generation circuit 110 maintains a predetermined voltage difference on the reference of the input voltage, and since the voltage of the source electrode of the fet Ms is the input voltage, the predetermined voltage difference Δv can be used to turn on the fet Ms, so that the voltage difference output by the charge generation circuit 110 can be minimized on the basis of ensuring that the fet Ms is turned on; in addition, even if the input voltage Vin changes, only a predetermined voltage difference is required to be maintained on the reference of the input voltage, and the effect of clamping or opening the fet Ms is not affected.
As shown in fig. 10, in the switch circuit, the clamp circuit 400 may be the clamp circuit in fig. 9, and the current source 500 includes a first PMOS transistor Mp1, a first reference branch 510, a second reference branch 520, and an output branch 530; the first reference branch 510 includes a reference constant current source Ib, the second reference branch 520 includes a reference resistor Rq and a reference current switch S1, and the reference resistor Rq is connected in series with the reference current switch S1 and then connected in parallel with the reference constant current source Ib; the output branch 530 includes a second PMOS transistor Mp2; the source electrode of the first PMOS tube MP1 is connected with the output end VCP of the charge generation circuit 110, the grid electrode is connected with the drain electrode of the first PMOS tube MP2, and the grid electrode and the drain electrode of the second PMOS tube MP2 are grounded through a reference constant current source Ib; the source of the second PMOS Mp2 is connected to the output VCP of the charge generating circuit 110, and the drain is connected to the gate of the fet Ms. When the control current source 500 outputs the start current, the RS flip-flop 310 controls the reference current switch S1 to be turned on, and the second reference branch 520 outputs the second reference current, so that the first PMOS transistor Mp1 flows through the sum of the first reference current and the second reference current, and therefore, the second PMOS transistor Mp2 replicates (or is called as a mirror image) the sum of the first reference current and the second reference current, and charges the fet Ms. When the control current source 500 outputs the sustain current, the RS flip-flop 310 controls the reference current switch S1 to be turned off, and the second reference branch 520 stops outputting the second reference current, so that the first PMOS transistor Mp1 only flows through the first reference current, and thus the second PMOS transistor Mp2 duplicates (or is called a mirror image) the first reference current and charges the field effect transistor Ms.
In the switching circuit of fig. 10, the RS flip-flop 310 includes a first nor gate 311 and a second nor gate 312; the first input terminal 311a of the first nor gate 311 inputs the voltage of the detection resistor Rs, the second input terminal 311b is connected to the output terminal 312c of the second nor gate 312, and the output terminal 311c serves as the output terminal of the Rs flip-flop 310 and is connected to the first input terminal 312a of the second nor gate 312; the second input terminal 312b of the second nor gate 312 inputs the control signal on_slot of the RS flip-flop 310. In the waveform of the switching circuit of the embodiment of fig. 10, on, on_ b, fullon, on _slot and on_fast are respectively represented by a switching signal of the field effect transistor Ms, a control signal of the clamp switch S2, a voltage of the detection resistor Rs, a control signal of the Rs flip-flop 310 and an output signal of the Rs flip-flop 310; the control signal on_slot of the RS flip-flop 310 is a rising edge extraction signal of the switching signal of the field effect transistor Ms; the control signal on_b of the clamp switch S2 is the inverse of the switching signal of the field effect transistor Ms. When the fet Ms needs to be controlled to be turned off, the on signal is at a low level, and the on_ b, fullon, on _slot and the on_fast are respectively at a high level, a low level and a low level, so that the clamp switch S2 is turned on, and the clamp circuit 400 clamps the fet Ms; the reference current switch S1 and the detection switch S3 are turned off, and the output branch 530 only copies the first reference current to charge the gate of the fet Ms, so as to maintain the voltage of the gate of the fet Ms required for the clamp 400 to turn on. When the fet Ms needs to be controlled to be turned on, the on signal is changed from low level to high level, the rising edge extraction signal on_b is a high level pulse with a set width, the rising edge extraction signal on_b causes the output end of the RS flip-flop 310 to output a trigger on signal, that is, on_fast is changed to high level, the reference current switch S1 and the detection switch S3 are turned on, the output branch 530 copies the sum of the first reference current and the second reference current as an on current, and charges the gate of the fet Ms; before the gate voltage of the field-effect transistor Ms reaches the gate threshold voltage, the voltage fullon of the detection resistor Rs is low, and therefore, on_fast maintains high, i.e., the reference current switch S1 and the detection switch S3 are maintained on. When the gate voltage of the fet Ms is greater than the gate threshold voltage, since a current flows through the detection resistor Rs, the voltage fullon thereof becomes high level, so that the output terminal of the Rs flip-flop 310 outputs a trigger off signal, i.e., on_fast becomes low level, the reference current switch S1 and the detection switch S3 are turned off, and the output branch 530 only copies the first reference current as the sustain current, thereby charging the gate of the fet Ms.
Those skilled in the art will appreciate that the above-described preferred embodiments can be freely combined and stacked without conflict.
It will be understood that the above-described embodiments are merely illustrative and not restrictive, and that all obvious or equivalent modifications and substitutions to the details given above may be made by those skilled in the art without departing from the underlying principles of the invention, are intended to be included within the scope of the appended claims.

Claims (7)

1. The switching circuit of the field effect transistor comprises a charge pump and the field effect transistor, and is characterized by further comprising an opening degree detection circuit;
the opening degree detection circuit is used for detecting the voltage of the grid electrode of the field effect transistor; the opening degree detection circuit comprises a detection switch, a first detection PMOS tube, a second detection PMOS tube and a detection resistor; the source electrode of the first detection PMOS tube is connected with the grid electrode of the field effect tube, the drain electrode of the first detection PMOS tube is respectively connected with the grid electrode of the first detection PMOS tube and the source electrode of the second detection PMOS tube, the grid electrode of the second detection PMOS tube is connected with the source electrode of the field effect tube, and the drain electrode is grounded through the detection resistor;
when the field effect transistor needs to be controlled to be turned off:
the detection switch is turned off, so that the opening degree detection circuit is turned off and stops detecting the voltage of the grid electrode of the field effect transistor;
when the field effect transistor needs to be controlled to be conducted:
the detection switch is conducted so as to enable the opening degree detection circuit to conduct and start detecting the voltage of the grid electrode of the field effect transistor, if the grid electrode of the field effect transistor is charged to a voltage smaller than the grid voltage threshold value, the detection switch is kept conducted so as to control the opening degree detection circuit to keep detecting the voltage of the grid electrode of the field effect transistor, and if the grid electrode of the field effect transistor is charged to a voltage larger than the grid voltage threshold value, the detection switch is turned off so as to control the opening degree detection circuit to stop detecting the voltage of the grid electrode of the field effect transistor; if the voltage of the detection resistor is high level, judging that the voltage of the grid electrode of the field effect transistor is larger than the grid voltage threshold value, and if the voltage of the detection resistor is low level, judging that the voltage of the grid electrode of the field effect transistor is smaller than the grid voltage threshold value;
the charge pump charges the grid electrode of the field effect tube with starting current so as to control the conduction of the field effect tube; if the opening degree detection circuit detects that the voltage of the grid electrode of the field effect tube is larger than a grid voltage threshold value, the charge pump is converted from the opening current to the maintaining current to charge the grid electrode of the field effect tube so as to maintain the field effect tube to be kept on; wherein the sustain current is less than the on current.
2. The switching circuit according to claim 1, wherein,
the charge pump is used for providing required current to the current source;
the current source comprises a first reference branch for providing a first reference current, a second reference branch for providing a second reference current, and an output branch, wherein the first reference current is less than the second reference current;
when the field effect transistor needs to be controlled to be turned off, the output branch circuit copies the first reference current as the maintaining current so as to provide current required by clamping for a clamping circuit, and the clamping circuit clamps the grid electrode of the field effect transistor at a voltage which enables the field effect transistor to be in an off state;
when the field effect transistor needs to be controlled to be conducted, if the voltage of the grid electrode of the field effect transistor is smaller than the grid voltage threshold value, the output branch circuit copies the sum of the first reference current and the second reference current as the starting current, and if the grid electrode of the field effect transistor is charged to be larger than the voltage of the grid voltage threshold value, the output branch circuit copies the first reference current as the maintaining current so as to maintain the conduction of the field effect transistor.
3. The switching circuit according to claim 1, wherein,
the charge pump is used for providing required current to the current source;
the current source comprises a first reference branch for providing a first reference current, a reference current switch for controlling the first reference branch to be turned on and off, a second reference branch for providing a second reference current, and an output branch; wherein the first reference current is less than the second reference current;
the reset end and the set end of the RS trigger are used for respectively inputting the voltage of the detection resistor and the control signal of the RS trigger, and the output end is used for controlling the reference current switch and the detection switch; the control signal of the RS trigger is a rising edge extraction signal of a switching signal of the field effect transistor;
when the field effect transistor needs to be controlled to be turned off, the switching signal of the field effect transistor is a turn-off signal, the output end of the RS trigger outputs a trigger turn-off signal, the reference current switch and the detection switch are controlled to be turned off, so that the output branch circuit replicates the first reference current as the maintaining current, the clamping circuit clamps the grid electrode of the field effect transistor at the voltage which enables the field effect transistor to be in the turn-off state, and the opening degree detection circuit stops detecting the voltage of the grid electrode of the field effect transistor;
when the field effect transistor needs to be controlled to be conducted, the switching signal of the field effect transistor is a conducting signal, the output end of the RS trigger outputs a triggering conducting signal, the reference current switch and the detection switch are controlled to be conducted so that the output branch circuit replicates the sum of the first reference current and the second reference current as the starting current, the starting degree detection circuit starts to detect the voltage of the grid electrode of the field effect transistor, if the voltage of the detection resistor is high level, the output end of the RS trigger outputs a triggering switching-off signal, the reference current switch and the detection switch are controlled to be switched off so that the output branch circuit replicates the first reference current as the maintaining current, and the starting degree detection circuit stops detecting the voltage of the grid electrode of the field effect transistor.
4. A switching circuit according to claim 2 or 3, wherein,
the first reference branch comprises a reference constant current source, the second reference branch comprises a reference resistor, and the reference resistor and the reference constant current source are connected in parallel.
5. The switching circuit according to claim 3, wherein,
the RS trigger comprises a first NOR gate and a second NOR gate;
the first input end of the first NOR gate inputs the voltage of the detection resistor, the second input end is connected with the output end of the second NOR gate, and the output end is used as the output end of the RS trigger and is connected with the first input end of the second NOR gate;
a second input end of the second NOR gate inputs a control signal of the RS trigger;
when the field effect transistor needs to be controlled to be conducted, a control signal of the RS trigger is generated according to the rising edge of the switching signal of the field effect transistor, so that the output end of the RS trigger outputs a trigger conducting signal.
6. The control method of the switching circuit of the field effect tube, the said switching circuit includes charge pump and field effect tube, characterized by that, the said switching circuit also includes the detection circuit of the opening degree, is used for detecting the voltage of the grid of the said field effect tube; the opening degree detection circuit comprises a detection switch, a first detection PMOS tube, a second detection PMOS tube and a detection resistor; the source electrode of the first detection PMOS tube is connected with the grid electrode of the field effect tube, the drain electrode of the first detection PMOS tube is respectively connected with the grid electrode of the first detection PMOS tube and the source electrode of the second detection PMOS tube, the grid electrode of the second detection PMOS tube is connected with the source electrode of the field effect tube, and the drain electrode is grounded through the detection resistor;
when the field effect transistor needs to be controlled to be turned off:
the detection switch is turned off, so that the opening degree detection circuit is turned off and stops detecting the voltage of the grid electrode of the field effect transistor;
when the field effect transistor needs to be controlled to be conducted:
the detection switch is conducted so as to enable the opening degree detection circuit to conduct and start detecting the voltage of the grid electrode of the field effect transistor, if the grid electrode of the field effect transistor is charged to a voltage smaller than the grid voltage threshold value, the detection switch is kept conducted so as to control the opening degree detection circuit to keep detecting the voltage of the grid electrode of the field effect transistor, and if the grid electrode of the field effect transistor is charged to a voltage larger than the grid voltage threshold value, the detection switch is turned off so as to control the opening degree detection circuit to stop detecting the voltage of the grid electrode of the field effect transistor; if the voltage of the detection resistor is high level, judging that the voltage of the grid electrode of the field effect transistor is larger than the grid voltage threshold value, and if the voltage of the detection resistor is low level, judging that the voltage of the grid electrode of the field effect transistor is smaller than the grid voltage threshold value;
the charge pump charges the grid electrode of the field effect tube with starting current so as to control the conduction of the field effect tube; if the opening degree detection circuit detects that the voltage of the grid electrode of the field effect tube is larger than a grid voltage threshold value, the charge pump is converted from the opening current to the maintaining current to charge the grid electrode of the field effect tube so as to maintain the field effect tube to be kept on;
wherein the sustain current is less than the on current.
7. A chip comprising a switching circuit of a field effect transistor according to any one of claims 1 to 5.
CN202310102324.5A 2023-01-16 2023-01-16 Switching circuit, control method and chip of field effect transistor Active CN115996048B (en)

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