CN111277042A - Chip and dual-power supply circuit - Google Patents

Chip and dual-power supply circuit Download PDF

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Publication number
CN111277042A
CN111277042A CN202010097870.0A CN202010097870A CN111277042A CN 111277042 A CN111277042 A CN 111277042A CN 202010097870 A CN202010097870 A CN 202010097870A CN 111277042 A CN111277042 A CN 111277042A
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Prior art keywords
power supply
circuit
voltage
mos transistor
mos tube
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CN202010097870.0A
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李响
董渊
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Shanghai Awinic Technology Co Ltd
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Shanghai Awinic Technology Co Ltd
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Priority to CN202010097870.0A priority Critical patent/CN111277042A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
    • H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
    • H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
    • H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
    • H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
    • H02J9/061—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems for DC powered loads

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  • Emergency Management (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention relates to a chip and a dual-power supply circuit, which comprises a first power supply path, a second power supply path, a switching circuit and a power supply port, wherein the first power supply path is connected with the second power supply path; the first power supply path comprises a charge pump circuit, a MOS tube MN2, a MOS tube MP2 and a diode D1 with reverse clamping effect, wherein the input end of the charge pump circuit is used for accessing voltage provided by a first power supply, the output end of the charge pump circuit is connected with the grid electrode of the MOS tube MN2, the drain electrode of the MOS tube MN2 is used for accessing voltage provided by the first power supply, the source electrode of the MOS tube MN2 is connected with the drain electrode of the MOS tube MP2, the drain electrode of the MOS tube MP2 is connected with the power supply port, the charge pump circuit responds to the voltage provided by the first power supply to be boosted to trigger the MOS tube MN2 to be conducted and enable the MOS tube MN2 to work in a deep linear region, and the power supply voltage of the power supply port can reach the minimum working voltage of a chip internal circuit without the first power supply reaching high starting voltage.

Description

Chip and dual-power supply circuit
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a chip and a dual-power supply circuit.
Background
In integrated circuit applications, most systems require an internal power module to provide stable power to the internal circuitry. In some special applications, the internal power module of the chip needs to select an appropriate power from two different power sources to supply power to the internal circuit of the chip.
As shown in fig. 1, a chip, such as a charger chip, for supplying power by using two power sources, namely a first power source and a second power source, is provided, where the first power source provides an input voltage VIN for the chip, the second power source provides a battery supply voltage VBAT, and one of the power sources in the chip is selected by a power source module in the chip to output a supply voltage VDD for starting an internal circuit of the chip.
As shown in fig. 1, the conventional power supply circuit brings the voltage VBAT provided by the second power supply to the voltage VIN provided by the first power supply, and the voltage VDD drops when the voltage VBAT provided by the second power supply is switched to the voltage VIN provided by the first power supply for power supply, the voltage drop from the input voltage VIN to the power supply port is large, and the voltage VDD can reach the minimum working voltage of the internal circuit of the chip only when the input voltage VIN reaches a large value, that is, when the starting voltage of the first power supply is large.
Disclosure of Invention
In view of the above, there is a need for a dual power supply circuit and a chip, in which the first power supply does not need a high start voltage to make the supply voltage of the power supply port reach the minimum operating voltage of the internal circuit of the chip.
In a first aspect, an embodiment of the present invention provides a dual power supply circuit, including a first power supply path, a second power supply path, a switching circuit, and a power supply port;
the first power supply path comprises a charge pump circuit, a MOS tube MN2, a MOS tube MP2 and a diode D1 with reverse clamping action, wherein the input end of the charge pump circuit is used for accessing a voltage provided by a first power supply, the output end of the charge pump circuit is connected with the gate of the MOS tube MN2, the drain of the MOS tube MN2 is used for accessing the voltage provided by the first power supply, the source of the MOS tube MN2 is connected with the drain of the MOS tube MP2, the drain of the MOS tube MP2 is connected with the power supply port, the cathode of the diode D1 is connected with the input end of the charge pump circuit, the anode of the diode D1 is grounded, the diode D1 is used for enabling the voltage provided by the first power supply to be input to the input end of the charge pump circuit, and the charge pump circuit is boosted in response to the voltage provided by the first power supply to trigger the conduction of the MOS tube MN2 to work in a deep linear region; the second power supply path comprises a MOS tube MP1, the drain of the MOS tube MP1 is used for accessing the voltage provided by the second power supply, and the source of the MOS tube MP1 is connected with the power supply port;
the switching circuit is used for selectively switching on the MOS transistor MP2 to switch on the first power supply path when the power supply of a first power supply is determined, and selectively switching on the MOS transistor MP1 to switch on the second power supply path when the power supply of a second power supply is determined.
In one embodiment, the switching circuit includes a comparator and a control logic circuit, a first input terminal of the comparator is used for accessing a voltage provided by a first power supply, a second input terminal of the comparator is used for accessing a voltage provided by a second power supply, an output terminal of the comparator is connected with an input terminal of the control logic circuit, an output terminal of the control logic circuit is connected with a gate of the MOS transistor MP2, and another output terminal of the control logic circuit is connected with the second power supply path; the comparator is used for comparing the voltage provided by the first power supply with the voltage provided by the second power supply, the control logic circuit is used for judging that the first power supply supplies power when the comparator compares that the voltage provided by the first power supply is greater than the voltage provided by the second power supply, so that the MOS tube MP2 is selected to be turned on, and is used for judging that the second power supply supplies power when the comparator compares that the voltage provided by the first power supply is less than the voltage provided by the second power supply, so that the MOS tube MP1 is selected to be turned on.
In one embodiment, the first input terminal of the comparator is connected to the source of the MOS transistor MN2, and the comparator is configured to compare the source voltage of the MOS transistor MN2 with the voltage provided by the second power supply.
In one embodiment, the power supply circuit further includes a unregulated voltage regulator, the source of the MOS transistor MN2 is connected to an input terminal of the unregulated voltage regulator, and the first input terminal of the comparator is connected to an output terminal of the unregulated voltage regulator.
In one embodiment, the power supply circuit further includes a MOS transistor MN1, wherein a drain of the MOS transistor MN2 is connected to a drain of the MOS transistor MN1, a source of the MOS transistor MN1 is used for receiving a voltage provided by the first power supply, and a gate of the MOS transistor MN1 is connected to the driving voltage.
In one embodiment, the voltage upper limit of the first power supply is higher than that of the second power supply, the power supply circuit further comprises a clamping circuit, the clamping circuit is connected with the gate of the transistor MN2, the clamping circuit enables the source voltage of the transistor MN2 to be lower than 6V, and the transistor MP2 adopts a low-voltage PMOS transistor device with a voltage of 6V or lower.
In one embodiment, the control logic circuit is provided with a time keeping module, which is used for providing a power supply keeping time when the power supply circuit is switched from the first power supply to the second power supply, so that the first power supply path is conducted in the power supply keeping time.
In one embodiment, the power supply circuit further includes an auxiliary start circuit, a control end of the auxiliary start circuit is connected to an input end of the charge pump circuit, an input end of the auxiliary start circuit is connected to a drain of the MOS transistor, and an output end of the auxiliary start circuit is connected to the power supply port, and is used for assisting the start of the first power supply path.
In one embodiment, the auxiliary starting circuit includes an N-type MOS transistor MN3 and an N-type MOS transistor MN4, a drain of the N-type MOS transistor MN3 is connected to a drain of the N-type MOS transistor MN2, a gate of the N-type MOS transistor MN3 is connected to an input terminal of the charge pump circuit, a source of the N-type MOS transistor MN3 is connected to a source of the N-type MOS transistor MN4, a gate of the N-type MOS transistor MN4 is connected to the input terminal of the charge pump circuit, and a drain of the N-type MOS transistor MN4 is connected to the power supply port.
According to the dual-power supply circuit, when the power supply is switched from the second power supply to the first power supply, the first power supply path is conducted by the switching circuit, the MOS tube MN2 grid source can have a large voltage difference due to the pressurization of the charge pump circuit, so that the MOS tube MN2 grid source works in a deep linear region, the first power supply path basically has no voltage drop, the power supply voltage of the power supply port is basically consistent with the voltage provided by the first power supply, and therefore the first power supply can enable the power supply voltage of the power supply port to reach the minimum working voltage of the internal circuit of the chip without high starting voltage.
In a second aspect, an embodiment of the present invention provides a chip, where the power supply circuit as described in any of the above embodiments is formed, and a voltage of a power supply port of the power supply circuit is used to supply power to an internal circuit of the chip.
Drawings
FIG. 1 is a schematic diagram of an internal power supply circuit of a conventional chip;
FIG. 2 is a schematic diagram of a power supply circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of waveforms of different voltages when the voltage VBAT is switched to the voltage VIN according to an embodiment;
fig. 4 is a schematic diagram illustrating waveforms of different voltages when the voltage VIN is switched to the voltage VBAT according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As described in the background art, the conventional power supply circuit shown in fig. 1 may cause the voltage VBAT provided by the second power supply to drop down to the voltage VDD provided by the first power supply when the voltage VBAT provided by the second power supply is switched to the voltage VIN provided by the first power supply for power supply, the voltage drop from the input voltage VIN to the power supply port is large, and the voltage VDD at the power supply port can reach the minimum operating voltage of the internal circuit of the chip only when the input voltage VIN needs to reach a large value, that is, when the start voltage of the first power supply is large.
The invention provides a dual-power supply circuit, and a first power supply can enable the power supply voltage of a power supply port to reach the minimum working voltage of a circuit in a chip without high starting voltage. The dual-power supply circuit can be applied to a charging scene, the dual power supplies are a first power supply and a second power supply, and the upper voltage limits can be different.
As shown in fig. 2, the dual power supply circuit includes a first power supply path, a second power supply path, a switching circuit U1, and a power supply port for providing a power supply voltage VDD for the chip internal circuit.
The first power supply path comprises a charge pump circuit U2, a MOS tube MN2, a MOS tube MP2 and a diode D1 with reverse clamping effect, the input end of the charge pump circuit U2 is used for accessing the voltage provided by the first power supply, the output end of the charge pump circuit U2 is connected with the gate of the MOS transistor MN2, the drain electrode of the MOS transistor MN2 is used for accessing the voltage provided by the first power supply, the source electrode of the MOS transistor MN2 is connected with the drain electrode of the MOS transistor MP2, the drain of the MOS transistor MP2 is connected to the power supply port, the cathode of the diode D1 is connected to the input terminal of the charge pump circuit U2, the anode of the diode D1 is grounded, the diode D1 is used for enabling the voltage provided by the first power supply to flow to the input terminal of the charge pump circuit U2, the charge pump circuit U2 is used for boosting voltage and outputting voltage to trigger the MOS transistor MN2 to be conducted and enable the MOS transistor to work in a deep linear region when the first power supply supplies power; the second power supply path comprises a MOS tube MP1, the drain of the MOS tube MP1 is used for accessing the voltage provided by the second power supply, and the source of the MOS tube MP1 is connected with the power supply port. The first input end of the switching circuit U1 is used for accessing a voltage provided by a first power supply, the second input end of the switching circuit U1 is used for accessing a voltage provided by a second power supply, the first output end of the switching circuit U1 is connected with the grid of the MOS tube MP2, the second output end of the switching circuit U1 is connected with the grid of the MOS tube MP1, the switching circuit U1 is used for selectively conducting the MOS tube MP2 to conduct the first power supply path when the first power supply is judged, and selectively conducting the MOS tube MP1 to conduct the second power supply path when the second power supply is judged.
In the power supply circuit of the embodiment of the invention, if the switching circuit U1 compares that the voltage VIN is greater than the voltage VBAT, it indicates that the power supply is switched from the second power supply to the first power supply, the switching circuit U1 selectively turns on the MOS transistor MP2, and the MOS transistor MN2 is also turned on by the trigger of the charge pump circuit U2, so the first power supply path of the MOS transistor MN2, the MOS transistor MP2, and the power supply port is turned on, the charge pump circuit U2 has stored energy and has a boosting function, after the input end of the charge pump circuit U2 is connected to the voltage VIN, the output voltage makes the gate voltage and the source voltage of the MOS transistor MN2 have a large difference, so the MOS transistor MN2 works in a deep linear region, so the first power supply path of the MOS transistor MN2, the MOS transistor MP2, and the power supply port has substantially no voltage drop, the power supply voltage of the power supply port is substantially consistent with the voltage, and therefore the power supply voltage VDD of the power supply port easily reaches the minimum working voltage VDD of the internal circuit of the chip, it is not necessary for the first power supply to reach a very high starting voltage. Especially, when the voltage upper limit of the first power supply is higher than that of the second power supply, the VDD reaches the minimum working voltage of the internal circuit of the chip when the voltage VIN is very small, and compared with a traditional power supply circuit, the starting voltage reduction effect required by the first power supply in the embodiment of the invention is more obvious.
In addition, when the voltage VIN starts to be powered up when the power is supplied by the first power supply, the charge pump circuit U2 can be triggered to work, which is beneficial to quickly turn on the MOS transistor MN2, and the output of the charge pump circuit U2 boosts the gate of the driving MOS transistor MN2, which is also beneficial to completely turn on the MOS transistor MN 2.
Specifically, the power supply circuit comprises a first input end and a second input end, the first input end is used for receiving a voltage VIN provided by a first power supply, the second input end is used for receiving a voltage VBAT provided by a second power supply, a cathode of a diode D1 is connected with the first input end, an input end of a charge pump circuit U2 is connected with the first input end, and a drain of a MOS transistor MN2 is connected with the first input end to receive the voltage VIN. The voltage VIN provided by the first power supply may be an input voltage of the chip, and the voltage provided by the second power supply may be a battery supply voltage.
Specifically, the MOS transistor MN2 may be an N-type MOS transistor, and when the N-type MOS transistor operates in a deep linear region, the voltage drop may be smaller, which is more favorable for reducing the voltage drop of the first power supply path. Both the MOS transistor MP1 and the MOS transistor MP2 may be P-type transistors, and as shown in fig. 2, the conduction directions of the parasitic diodes of the two PMOS transistors MP1 and MP2 are both toward the power supply port, so that when one of the two power supplies power to the power supply port, the voltage VDD at the power supply port does not leak to the other power supply, for example, when the MOS transistor MP2 is turned on, the voltage VDD at the power supply port does not leak to the second power supply through the MOS transistor MP1, thereby preventing the problem of power supply backflow.
Specifically, the MOS transistor MN2 may adopt a high voltage tube, and the first power supply path of the MOS transistor MN2, the MOS transistor MP2 and the power supply port can withstand a higher voltage. Diode D1 may be a zener diode. Specifically, the diode D1 in fig. 2 may be connected to the voltage VIN through the resistor R1.
Specifically, the power supply circuit further comprises a MOS transistor MN1, and the MOS transistor MN1 can be used for negative pressure processing, current sampling and the like of the chip. The drain of the MOS transistor MN2 may be directly connected to the voltage VIN provided by the first power supply, or may be connected to the voltage VIN provided by the first power supply through the MOS transistor MN1 as shown in fig. 2, wherein the drain of the MOS transistor MN2 is connected to the drain of the MOS transistor MN1, the source of the MOS transistor MN1 is used for connecting to the voltage VIN provided by the first power supply, and the gate of the MOS transistor MN1 is connected to the driving voltage VIN-DRV. The MOS transistor MN1 may be an NMOS input power transistor, and its gate is powered by another driving voltage VIN-DRV, which can ensure that the MOS transistor MN1 is fully turned on when the driving voltage VIN-DRV is continuously powered.
Regarding the switching circuit U1, in an embodiment, the switching circuit U1 includes a comparator COMP1 and a control logic circuit U11, a first input end of the comparator COMP1 is configured to be connected to a voltage VIN provided by a first power supply, a second input end of the comparator COMP1 is connected to a voltage VBAT provided by a second power supply, an output end of the comparator COMP1 is connected to an input end of the control logic circuit U11, and two output ends of the control logic circuit U11 are further connected to gates of a MOS transistor MP1 and a MOS transistor MP2, respectively. The comparator COMP1 is configured to compare the magnitude of the voltage VIN and the voltage VBAT, the control logic circuit U11 is configured to selectively turn on the MOS transistor MP1 or the MOS transistor MP2 according to a comparison result of the comparator COMP1, and when the voltage VIN is greater than the voltage VBAT, determine that the dual power supplies are switched to a first power supply to supply power, thereby selectively turn on the MOS transistor MP2, and turn off the MOS transistor MP2, and when the voltage VIN is less than the voltage VBAT, determine that the dual power supplies are switched to a second power supply to supply power, turn on the MOS transistor MP1, and turn off the MOS transistor MP 2.
Specifically, comparator COMP1 is a hysteresis comparator.
Regarding the first input end of the comparator COMP1 accessing the voltage VIN, as shown in fig. 2, the first input end of the comparator COMP1 accesses the first power voltage VIN through the MOS transistor MN2, the first input end of the comparator COMP1 is connected to the source of the MOS transistor MN2, and the comparator is used for comparing the source voltage of the MOS transistor MN2 with the voltage provided by the second power supply, so that the voltage VDD of the power supply port does not suddenly power down during the period of switching to the first power supply.
Specifically, the source of the MOS transistor MN2 is connected to the non-inverting input terminal of a comparator COMP1, and the inverting input terminal of the comparator COMP1 is connected to the second input terminal.
The working principle of the dual-power supply circuit when the input end of the comparator COMP1 is connected to the voltage VIN provided by the first power supply through the MOS tube MN2 is briefly described below.
As shown in fig. 2, VIN and VBAT are voltages provided by the first power supply and the second power supply of the dual power supplies, respectively, the voltage of the final power supply node is VDD, and the VDD voltage is an output voltage of the internal power supply of the chip, and supplies power to the internal circuits of the chip. In this embodiment, the comparator COMP1 determines the source voltage VSMN2 and the second power voltage VBAT of the MOS transistor MN2, and the control logic circuit U11 turns on the MOS transistor MP1 or the MOS transistor MP2 according to the comparison result. When the comparator COMP1 outputs the result that the source voltage VSMN2 of the MOS transistor MN2 is greater than VBAT, the control logic circuit U11 turns on the MOS transistor MP2 and turns off the MOS transistor MP1 in response to the comparison result, and the voltage VIN provides the supply voltage VDD for the power supply port, otherwise turns on the MOS transistor MP 1.
The conventional circuit comparator shown in fig. 1 is directly connected to the voltage VIN and then compared with the voltage VBAT, as shown in fig. 3, so that during the period when the voltage VBAT provided by the second power supply is switched to the voltage VIN provided by the first power supply, the power supply port VDD is suddenly powered down during the switching period. In the embodiment of the present invention, the comparator COMP1 accesses the voltage VIN through the MOS transistor MN2, that is, the source voltage VSMN2 of the MOS transistor MN2 indirectly reflects the magnitude of the voltage VIN, and the comparator COMP1 switches the power supply path by determining the source voltage VSMN2 of the MOS transistor MN2 and the second power VBAT, when the first power VIN is quickly powered up, due to the influence of the parasitic capacitance in the MOS transistor MN2, the source voltage VSMN2 of the MOS transistor MN2 may not be completely powered up along with the voltage VIN, that is, the source voltage VSMN2 of the MOS transistor MN2 is powered up in a delayed manner compared with the voltage VIN, so that the voltage VBAT is still used for power supply in the delayed period, and the power supply port VDD is not suddenly powered down during power switching.
In one embodiment, the power supply circuit of the chip according to the embodiment of the present invention further includes a voltage-dropping regulator VOS, as shown in fig. 2, the source of the MOS transistor MN2 is connected to the first input terminal of the comparator COMP1 through the voltage-dropping regulator VOS, and the voltage-dropping regulator VOS is introduced to reduce the drop of the VDD voltage at the moment when the second power supply is switched to the first power supply, so as to reduce the influence on the start of the internal circuit of the chip. Because the comparator COMP1 may have a certain offset, if the power is switched from the second power to the first power, at a moment after the switching, the MOS transistor MN2 will switch from the subthreshold conducting state or the off state to the linear region state, which will cause the source voltage VSMN2 of the MOS transistor MN2 to drop for a short time, so that the VDD voltage drops for a short time, and after the voltage drop across the offset voltage transformer VOS is introduced, the first power supply path will be turned on when the voltage VIN of the first power is greater than the voltage VBAT + of the second power, so that the offset voltage will reduce the drop of the VDD voltage.
In the embodiment of the invention, the power supply path is switched by a scheme that the comparator judges the source voltage VSMN2 of the MOS tube MN2 and the second power supply voltage VBAT, and the voltage drop of the power supply port voltage VDD is reduced by a scheme that the unregulated voltage regulator VOS is introduced, so that the power failure of the power supply port voltage VDD is reduced. Although the power-down situation of the power supply port voltage VDD can be reduced, in the actual working process of the power supply circuit, the power-down situation of the source voltage VSMN2 of the MOS transistor MN2 still exists in the power supply switching process, especially when the current required by the load connected to the power supply port reaches the milliampere level, the switching of the power supply can cause the comparator COMP1 to turn over back and forth, and then the output of the oscillation of the comparator COMP1 can cause the power supply port voltage VDD to be insufficient for power supply and the voltage VDD to drop.
Therefore, further, the control logic circuit U1 is further configured to provide a power retention time when the first power supply is switched to the second power supply, as shown in fig. 4, the power retention time may be in the order of microseconds, and when the first power supply is switched to the second power supply, because the MOS transistor MP2 is still turned on during the retention time, the power supply port voltage VDD can be maintained to be supplied at the switching instant, so as to reduce the jitter of the power supply port voltage VDD during switching.
Specifically, the control logic circuit U11 has a time keeping module, which is used to provide a power keeping time when the power supply circuit is switched from the first power supply to the second power supply, so that the first power supply path of the MOS transistor MN2, the MOS transistor MP2, and the power supply port is kept on during the power keeping time. When the second power supply is switched to the first power supply, the control logic circuit U11 may not set the power supply holding time, because the second power supply supplies power to the power supply port through a PMOS transistor, and the absolute value of the gate-source voltage VGS after the switching on becomes very large immediately, so that the power supply port voltage VDD has sufficient power supply capability.
In a conventional power supply circuit, if the voltage upper limit of the first power supply is higher than that of the second power supply, that is, if the first power supply is a high-voltage power supply, for example, the voltage upper limit is 12V, and the second power supply is a low-voltage power supply, for example, the voltage upper limit is 5V, the first power supply path needs to adopt a high-voltage tube to resist high voltage, and a large chip area is occupied. The embodiment of the invention also provides another dual-power supply circuit which can reduce the voltage of the source end of the MOS tube MN2, so that the MOS tube MP2 adopts a low-voltage tube to reduce the area of a chip.
As shown in fig. 2, the source terminal voltage of the MOS transistor MN2 is related to the output voltage Vcp of the charge pump, and if the output voltage of the charge pump circuit U2 is Vcp, the source voltage of the MOS transistor MN2 is: vSMN2＝Vcp-VGSMN2，VSMN2The source terminal voltage of the MOS transistor MN2, Vcp the output voltage of the charge pump circuit U2 (i.e. the gate voltage of the MN2 transistor), VGSMN2The voltage difference between the gate terminal and the source terminal of the MOS transistor MN2 is obtained. Therefore, the source terminal voltage of the MOS transistor MN2 is related to the output voltage Vcp of the charge pump circuit U2.
Therefore, in another embodiment of the dual power supply circuit of the present invention, the dual power supply circuit may include a clamping circuit (not shown in fig. 2) for clamping the output voltage Vcp of the charge pump circuit U2, and the clamping circuit is connected to the gate of the MOS transistor MN 2. In an alternative, the clamp circuit enables the source voltage of the transistor MN2 to be lower than a preset voltage, so that the MP2 transistor can use low-voltage devices below the preset voltage, for example, the preset voltage is 6V, and the low-voltage devices can use low-voltage devices below 6V, for example, 5V, thereby reducing the chip area. Since the second power source is a low voltage source, the MOS transistor MP1 can directly use a low voltage PMOS transistor below a predetermined voltage, for example, a 5V low voltage device, to reduce the chip area occupation.
Specifically, the clamping circuit comprises a Zener diode, the cathode of the clamping circuit is connected to the grid electrode of the MOS transistor MN2, and the anode of the clamping circuit is grounded.
The dual-power-supply circuit in another embodiment of the present invention further includes an auxiliary start circuit U3, a control terminal of the auxiliary start circuit U3 is connected to an input terminal of the charge pump circuit U2, an input terminal of the auxiliary start circuit U3 is connected to a drain of the MOS transistor, and an output terminal of the auxiliary start circuit U3 is connected to a power supply port, so as to assist the start of the first power supply path. Specifically, the auxiliary starting circuit U3 includes MOS transistor MN3 and MOS transistor MN4 that are N-type, and the drain of MOS transistor MN3 is connected with the drain of MOS transistor MN2, and the gate of MOS transistor MN3 is connected with the input of charge pump circuit U2, and the source of MOS transistor MN3 is connected with the source of MOS transistor MN4, and the gate of MOS transistor MN4 is connected with the input of charge pump circuit U2, and the drain of MOS transistor MN4 is connected with the power supply port.
In this embodiment, MOS transistor MN3 and MOS transistor MN4 serve as auxiliary starting circuit U3, and it is guaranteed that when second power supply output voltage is 0, when the first power supply is started, if MOS transistor MN1, MOS transistor MN2 and MOS transistor MP2 are both turned off, MOS transistor MN4 enters a linear region, MOS transistor MN3 works in a saturation region, and a voltage difference from voltage VIN to a power supply port is also mainly MOS transistor MN3 threshold voltage, thereby further avoiding the problem of too high first power supply starting voltage. However, if there are no two MOS transistors MN3 and MN4, considering that the start voltage of the charge pump circuit U2 is usually the threshold voltage of the MOS transistor, the start of the whole power supply path from the MOS transistor MN1, MN2, and MP2 to the power supply port requires three MOS transistor threshold voltages, which may result in a larger start voltage required by the first power supply.
In the above dual power supply circuit provided in the embodiment of the present invention, a chip, for example, a charger chip, is further provided in the embodiment of the present invention, where the power supply circuit described in any of the above embodiments is formed, and a voltage of a power supply port of the power supply circuit is used to supply power to an internal circuit of the chip.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A dual-power supply circuit is characterized by comprising a first power supply path, a second power supply path, a switching circuit and a power supply port;
the first power supply path comprises a charge pump circuit, a MOS tube MN2, a MOS tube MP2 and a diode D1 with reverse clamping action, wherein the input end of the charge pump circuit is used for accessing a voltage provided by a first power supply, the output end of the charge pump circuit is connected with the gate of the MOS tube MN2, the drain of the MOS tube MN2 is used for accessing the voltage provided by the first power supply, the source of the MOS tube MN2 is connected with the drain of the MOS tube MP2, the drain of the MOS tube MP2 is connected with the power supply port, the cathode of the diode D1 is connected with the input end of the charge pump circuit, the anode of the diode D1 is grounded, the diode D1 is used for enabling the voltage provided by the first power supply to be input to the input end of the charge pump circuit, and the charge pump circuit is boosted in response to the voltage provided by the first power supply to trigger the conduction of the MOS tube MN2 to work in a deep linear region;
the second power supply path comprises a MOS tube MP1, the drain of the MOS tube MP1 is used for accessing the voltage provided by the second power supply, and the source of the MOS tube MP1 is connected with the power supply port;
the switching circuit is used for selectively switching on the MOS transistor MP2 to switch on the first power supply path when the power supply of a first power supply is determined, and selectively switching on the MOS transistor MP1 to switch on the second power supply path when the power supply of a second power supply is determined.
2. The power supply circuit according to claim 1, wherein the switching circuit comprises a comparator and a control logic circuit, a first input terminal of the comparator is used for receiving a voltage provided by a first power supply, a second input terminal of the comparator is used for receiving a voltage provided by a second power supply, an output terminal of the comparator is connected with an input terminal of the control logic circuit, an output terminal of the control logic circuit is connected with the gate of the MOS transistor MP2, and another output terminal of the control logic circuit is connected with the gate of the MOS transistor MP 1; the comparator is used for comparing the voltage provided by the first power supply with the voltage provided by the second power supply, the control logic circuit is used for judging that the first power supply supplies power when the comparator compares that the voltage provided by the first power supply is greater than the voltage provided by the second power supply, so that the MOS tube MP2 is selected to be turned on, and is used for judging that the second power supply supplies power when the comparator compares that the voltage provided by the first power supply is less than the voltage provided by the second power supply, so that the MOS tube MP1 is selected to be turned on.
3. The power supply circuit of claim 2, wherein a first input terminal of the comparator is connected to the source of the MOS transistor MN2, and the comparator is configured to compare a voltage at the source of the MOS transistor MN2 with a voltage provided by a second power supply.
4. The power supply circuit according to claim 2, further comprising a unregulated voltage regulator, wherein the source of the MOS transistor MN2 is connected to an input of the unregulated voltage regulator, and the first input of the comparator is connected to an output of the unregulated voltage regulator.
5. The power supply circuit of claim 1, further comprising a MOS transistor MN1, wherein a drain of the MOS transistor MN2 is connected to a drain of the MOS transistor MN1, a source of the MOS transistor MN1 is configured to receive a voltage provided by the first power supply, and a gate of the MOS transistor MN1 is configured to receive a driving voltage.
6. The power supply circuit of claim 1, wherein the voltage upper limit of the first power supply is higher than that of the second power supply, and the power supply circuit further comprises a clamp circuit, the clamp circuit is connected to the gate of the transistor MN2, the clamp circuit enables the source voltage of the transistor MN2 to be lower than a preset voltage, and the transistor MP2 adopts PMOS devices below the preset voltage.
7. The power supply circuit of claim 2, wherein the control logic circuit comprises a time keeping module configured to provide a power keeping time when the power supply circuit switches from the first power supply to the second power supply, so that the first power supply path is turned on during the power keeping time.
8. The power supply circuit according to any one of claims 1-7, wherein the power supply circuit further comprises an auxiliary start-up circuit, a control terminal of the auxiliary start-up circuit is connected to the input terminal of the charge pump circuit, an input terminal of the auxiliary start-up circuit is connected to the drain of the MOS transistor, and an output terminal of the auxiliary start-up circuit is connected to the power supply port for assisting the start-up of the first power supply path.
9. The power supply circuit of claim 8, wherein the auxiliary start-up circuit comprises a MOS transistor MN3 and a MOS transistor MN4 both of N type, a drain of the MOS transistor MN3 is connected to a drain of the MOS transistor MN2, a gate of the MOS transistor MN3 is connected to the input terminal of the charge pump circuit, a source of the MOS transistor MN3 is connected to a source of the MOS transistor MN4, a gate of the MOS transistor MN4 is connected to the input terminal of the charge pump circuit, and a drain of the MOS transistor MN4 is connected to the power supply port.
10. A chip, characterized in that a supply circuit according to any of claims 1-9 is formed, the voltage of the supply port of the supply circuit being used for supplying the internal circuitry of the chip.
CN202010097870.0A 2020-02-17 2020-02-17 Chip and dual-power supply circuit Pending CN111277042A (en)

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CN112953227A (en) * 2021-05-14 2021-06-11 上海芯龙半导体技术股份有限公司 Circuit, switching power supply chip and system
CN115313826A (en) * 2022-07-19 2022-11-08 圣邦微电子(苏州)有限责任公司 Power supply voltage switching circuit and power supply voltage switching method
CN116742786A (en) * 2023-08-14 2023-09-12 四川中久大光科技有限公司 Laser seed source and main control loop safety power supply circuit
CN117937927A (en) * 2024-01-19 2024-04-26 上海芯启程微电子科技有限公司 Supply voltage selection circuit, method and DCDC chip having the circuit

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112953227A (en) * 2021-05-14 2021-06-11 上海芯龙半导体技术股份有限公司 Circuit, switching power supply chip and system
CN115313826A (en) * 2022-07-19 2022-11-08 圣邦微电子(苏州)有限责任公司 Power supply voltage switching circuit and power supply voltage switching method
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CN116742786B (en) * 2023-08-14 2023-10-20 四川中久大光科技有限公司 Laser seed source and main control loop safety power supply circuit
CN117937927A (en) * 2024-01-19 2024-04-26 上海芯启程微电子科技有限公司 Supply voltage selection circuit, method and DCDC chip having the circuit

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