CN115995439A - Packaging substrate, packaging structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a packaging substrate, which comprises: the metal substrate comprises a plurality of metal frames, and cutting areas are arranged between adjacent metal frames; the metal frame includes: binding area; the same side surface of the binding area is provided with a connecting structure and at least two sub-areas, the sub-areas are used for fixing chips, and the connecting structure is used for connecting and fixing chips in different sub-areas. By applying the technical scheme of the invention, the risk cross line is avoided, and the cost is reduced.

Description

Packaging substrate, packaging structure and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductor packaging, in particular to a packaging substrate, a packaging structure and a manufacturing method thereof.

Background

Along with the continuous progress of scientific technology, more and more electronic equipment is widely applied to daily life and work of people, brings great convenience to daily life and work of people, and becomes an indispensable important tool for people at present. The main component of the electronic device for realizing various functions is a chip, and the chip needs to be packaged for protection in order to ensure the reliability and service life of the chip and avoid damage of external factors.

However, with the progress of technology, the use function of a single chip product cannot meet the needs of people, so that two or more chips are combined and packaged into a product. However, in the actual packaging process, packaging problems similar to risk crossing lines can occur, the occurrence of the risk crossing lines can have a larger influence on the yield and stability of products, and the existing packaging needs to be redesigned to avoid the occurrence of the risk crossing lines, so that the cost is higher. Therefore, how to reduce the cost of combining and packaging multiple chips while avoiding risk cross lines is one of the problems to be solved by those skilled in the art.

Disclosure of Invention

Therefore, the technical scheme of the invention provides a packaging substrate, a packaging structure and a manufacturing method thereof, so that the problem of risk crossing lines is avoided, and the cost is reduced.

In order to achieve the above purpose, the present invention provides the following technical solutions:

a packaging substrate, the packaging substrate comprising:

the metal substrate comprises a plurality of metal frames, and cutting areas are arranged between adjacent metal frames;

the metal frame includes: binding area; the same side surface of the binding area is provided with a connecting structure and at least two sub-areas, the sub-areas are used for fixing chips, and the connecting structure is used for connecting and fixing chips in different sub-areas.

Preferably, the binding area has a groove, which is located outside the sub-area; wherein, the connection structure is located in the recess.

Preferably, the method comprises the steps of. The connecting structure is positioned in the groove, and the height of the connecting structure does not exceed the surface.

Preferably, the connection structure includes:

an insulating layer positioned on one side of the metal frame facing the connecting structure;

and the conductive layer is positioned on one side of the insulating layer, which is away from the metal frame.

Preferably, the insulation layer has a shore hardness of greater than 90.

The invention also provides a packaging structure, which comprises:

a metal frame; the metal frame includes: the binding area is provided with a connecting structure and at least two sub-areas on the same side surface;

the chips are fixed on the subareas, each subarea is fixed with one chip, and different chips are connected through the connecting structure;

the metal frame further comprises a pin for connecting an external circuit, the pin is disconnected with the binding area, and the pin is connected with the chip.

Preferably, the binding area has a groove, which is located outside the sub-area; wherein, the connection structure is located in the recess.

Preferably, the connection structure is located within the recess and the height of the connection structure does not exceed the surface.

Preferably, the connection structure includes:

an insulating layer positioned on one side of the metal frame facing the connecting structure;

and the conductive layer is positioned on one side of the insulating layer, which is away from the metal frame.

Preferably, the package structure further includes: and the plastic sealing layer surrounds the metal frame and the chip, and the plastic sealing layer exposes parts of the pins.

The invention also provides a packaging method, which comprises the following steps:

providing a packaging substrate, wherein the packaging substrate comprises a metal substrate, the metal substrate comprises a plurality of metal frames, and a cutting area is arranged between every two adjacent metal frames; the metal frame includes: binding area; a connection structure and at least two sub-regions located on the same side surface of the binding region; pins located outside the binding area;

fixing chips on the subareas, wherein the chips fixed on different subareas are connected through the connecting structure, and the chips are connected with the pins;

forming a plastic layer, wherein the plastic layer at least covers the surface of the metal frame facing to one side of the binding area;

cutting the cutting area.

Preferably, the method for connecting the chips fixed at the different sub-regions by the connection structure comprises:

etching the same side surface of the binding region to form a groove, wherein the groove is positioned outside the subarea;

the connecting structure is arranged in the groove;

and connecting and fixing chips in different subareas through the connecting structure.

Preferably, the connecting structure is disposed in the groove, and the height of the connecting structure does not exceed the same side surface of the binding area.

According to the technical scheme provided by the invention, the connecting structure is arranged in the metal frame to connect and fix the chips in different areas, so that the problem of risk crossing lines in chip interconnection is solved, the package is not required to be redesigned, the operation is simple, and the cost is further reduced.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings may be obtained according to the provided drawings without inventive effort to a person skilled in the art.

It should be noted that, the structures, proportions, sizes, etc. shown in the drawings are merely used in conjunction with the disclosure of the present specification, and are not intended to limit the applicable limitations of the present application, so that any modification, variation of proportions, or adjustment of sizes of the structures, proportions, etc. should not be construed as essential to the effect of the present application and the achievement of the objective, and should still fall within the scope of the disclosure of the present application.

FIG. 1 is a schematic diagram of a package structure according to the prior art;

fig. 2 is a schematic structural diagram of a package substrate according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a package structure according to an embodiment of the present invention;

fig. 4 is a schematic cross-sectional view of a package structure according to an embodiment of the present invention;

fig. 5-10 are cross-sectional flowcharts of a packaging method according to an embodiment of the present invention.

Detailed Description

Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which it is shown, and in which it is evident that the embodiments described are exemplary only some, and not all embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings.

In the prior art of packaging chips, due to the increase of the demand, a single chip product cannot meet the existing demand, and then a combined packaging technology for upgrading the single chip to a plurality of chips is generated, but in the actual process, when one or even a plurality of chips are integrated on the original single chip, the situation of risk crossing lines among the chips is easy to occur because of the general unchanged design, and referring to fig. 1, fig. 1 is a schematic structural diagram of a next packaging structure in the prior art. In fig. 1, the connection line a and the connection line B are risk intersecting lines. The existence of the risk cross line has great influence on the yield and stability of actual mass production, but most of the existing solutions are to redesign and wire the chip, so that the cost is high, and low-cost mass production cannot be realized.

The invention provides a packaging substrate, a packaging structure and a manufacturing method thereof based on the background, and solves the problem of risk crossing lines at lower cost.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a package substrate according to an embodiment of the present invention. The embodiment of the invention provides a packaging substrate, which comprises the following components: a metal substrate, wherein the metal substrate comprises a plurality of metal frames 1, and a cutting area 2 is arranged between adjacent metal frames 1; the metal frame 1 includes: binding area 3; the same side surface of the binding area 3 is provided with a connecting structure 4 and at least two sub-areas 5, the sub-areas 5 are used for fixing chips, and the connecting structure 4 is used for connecting and fixing chips in different sub-areas 5.

The chips in the different sub-areas 5 are interconnected by the connection structure 4, so that risk crossing lines are avoided, and compared with the prior art, only one connection structure 4 is added, low-cost mass production can be realized, and the cost is reduced.

It should be noted that fig. 1 shows that the metal substrate includes four metal frames. In practice, however, it is apparent that the package substrate comprises a plurality of metal frames. Not shown here due to the drawing requirements.

In the above-mentioned encapsulation substrate, the binding region 3 has grooves 6, which grooves 6 are located outside the sub-regions 5. Wherein the connecting structure 4 is located in the recess 6. And the height of the connection structure 4 does not exceed the surface.

Due to the grooves 6, the surface routing space of the package substrate is not reduced by adding the connection structure 4, and the grooves 6 are located in the surface of the binding region 3 and outside the sub-regions 5, so that the utilization rate of the metal substrate is improved.

Besides, when the binding area 3 does not have the groove 6, the connection structure 4 is located on the surface of the binding area 3, and the risk cross line can be avoided, which obviously falls within the protection scope of the present invention.

In the above package substrate, the connection structure 4 includes: an insulating layer located on a side of the metal frame 1 facing the connection structure 4; and a conductive layer positioned on one side of the insulating layer away from the metal frame 1. The insulating layer plays a role in isolating the conductive layer and the metal substrate, and two ends of the conductive layer are respectively connected and fixed with chips in different subareas 5.

In the actual packaging process, the conducting layer is isolated from the connecting wires above the conducting layer through a plastic sealing layer, but before the plastic sealing layer is formed, the conducting layer and the connecting wires above the conducting layer are possibly interconnected. Therefore, the connection structure 4 may further be provided with an isolation layer located on a side surface of the conductive layer away from the insulating layer, so as to avoid interconnection between the conductive layer and the connection wire above the conductive layer, thereby improving the yield.

Wherein the insulating layer comprises: insulating tape, hard resin, and polyester-like material; the insulating layer is required to have high deformation resistance, and generally, the Shore hardness of the insulating layer is required to be more than 90, and the Young modulus reaches GPa level at the normal temperature of 20-150 ℃.

In the above package substrate, the package substrate further includes: and a pin 7, wherein the pin 7 is disconnected with the binding area 3. The chip is interconnected with the pins 7 to realize connection of the chip with an external circuit.

Based on the above embodiment, another embodiment of the present invention further provides a package structure, and referring to fig. 3 to fig. 4, fig. 3 is a schematic structural diagram of the package structure provided in the embodiment of the present application, and fig. 4 is a schematic sectional view of the package structure provided in the embodiment of the present application. The package structure includes:

a metal frame 1; the metal frame 1 includes: a binding area 3, wherein the same side surface of the binding area 3 is provided with a connecting structure 4 and at least two sub-areas 5; chips 9 fixed to the sub-areas 5, each sub-area 5 being fixed with one chip 9, different chips 9 being connected by the connection structure 4; wherein, the metal frame 1 further comprises a pin 7 for connecting an external circuit, the pin 7 is disconnected from the binding area 3, and the pin 7 is connected with the chip 9.

In the above-mentioned packaging structure, the chips 9 fixed in different sub-regions 5 are interconnected by the connection structure 4, so that risk cross lines are avoided, and compared with the prior art, only one connection structure 4 is added, thereby realizing low-cost mass production and reducing cost.

Referring to fig. 4, in the above-described package structure, the binding region 3 has a groove 6, and the groove 6 is located outside the sub-region 5; wherein the connecting structure 4 is located in the recess 6. And, the connection structure 4 is located in the recess 6, and the height of the connection structure 4 does not exceed the surface.

Due to the existence of the grooves 6, the surface routing space of the packaging substrate is not reduced by adding the connecting structure 4, and the grooves 6 are positioned in the surface of the binding region 3 and outside the sub-regions 5, so that the utilization rate of the metal substrate is improved.

In addition, when the binding area 3 does not have the groove 6, the connection structure 4 is located on the surface of the binding area 3, and the risk cross line can be avoided, so that the connection structure is obviously also within the protection scope of the present invention.

In the above package substrate, the connection structure 4 includes:

an insulating layer located on a side of the metal frame 1 facing the connection structure 4; and a conductive layer positioned on one side of the insulating layer away from the metal frame 1. The insulating layer plays a role in isolating the conductive layer from the metal substrate, and two ends of the conductive layer are respectively connected with and fixed on the chips 9 of different subareas 5.

In the actual packaging process, the conductive layer is isolated from the connecting wires above the conductive layer by the plastic sealing layer 8, but before the plastic sealing layer 8 is formed, the conductive layer and the connecting wires above the conductive layer are possibly interconnected. Therefore, the connection structure 4 may further be provided with an isolation layer located on a side surface of the conductive layer away from the insulating layer, so as to avoid interconnection between the conductive layer and the connection wire above the conductive layer, thereby improving the yield.

Wherein the insulating layer comprises: insulating tape, hard resin, and polyester-like material; the insulating layer is required to have high deformation resistance, and generally, the Shore hardness of the insulating layer is required to be more than 90, and the Young modulus reaches GPa level at the normal temperature of 20-150 ℃.

In the above-mentioned package structure, the package structure further includes: a plastic layer 8 surrounding the metal frame 1 and the chip 9, wherein the plastic layer 8 exposes a portion of the leads 7. As shown in fig. 4, the plastic layer 8 covers the surface of the metal frame 1, the recess 6, the chip 9 and the connection structure 4, and covers the leads 7 and exposes portions of the leads 7. The portion of the pin 7 is exposed for connection to an external circuit.

The above packaging structure is only added with one connecting structure 4, so that the chips 9 fixed on different sub-areas 5 are interconnected, the problem of risk crossing lines is avoided, the cost is low, and low-cost mass production can be realized.

Based on the foregoing embodiments, another embodiment of the present invention further provides a packaging method for packaging the packaging structure described in the foregoing embodiments, where the packaging method refers to fig. 5 to fig. 10, and fig. 5 to fig. 10 are cross-sectional flowcharts of a packaging method provided in the embodiment of the present invention, and the packaging method includes:

step S1: referring to fig. 2 and 5, a package substrate is provided, wherein the package substrate comprises a metal substrate, the metal substrate comprises a plurality of metal frames 1, and a cutting area 2 is arranged between adjacent metal frames 1; the metal frame 1 includes: binding area 3; a connection structure 4 and at least two sub-areas 5 located on the same side surface of the binding area 3; pins 7 located outside the binding area 3.

The above-mentioned structure of the package substrate may be obtained by etching, where the surface of the package substrate facing away from the bonding area 3 is etched to obtain the recess structure 10 shown in fig. 5.

In addition, the packaging substrate is generally a large-sized copper sheet.

Step S2: referring to fig. 6-8, chips 9 are fixed on the sub-areas 5, wherein the chips 9 fixed on different sub-areas 5 are connected through the connection structure 4, and the chips 9 are connected with the pins 7.

Wherein, as shown in fig. 6, a chip 9 is fixed on the sub-areas 5, and one or more chips 9 are fixed on each sub-area 5.

As shown in fig. 7, the chips 9 fixed to the different sub-areas 5 are connected by the connection structure 4. Wherein the chip 9 and the connection structure 4 are interconnected by means of metal wire bonding.

As shown in fig. 8, the chip 9 and the pins 7 are connected, and the chip 9 is connected to the pins 7 to communicate with an external circuit.

In step S2 provided in this embodiment, the chips 9 fixed on the different sub-areas 5 are connected first, and then the chips 9 and the pins 7 are connected. Obviously, it is also possible to connect the chip 9 and the pins 7 first, and then connect the chips 9 fixed in the different sub-areas 5; and simultaneously connecting the chip 9, the chip 9 and the pins 7 fixed to different sub-areas 5.

Step S3: a plastic layer 8 is formed as shown in fig. 9, wherein the plastic layer 8 covers at least the surface of the metal frame 1 facing the binding area 3. The glue injection can be performed on the basis of the same side surface of the binding area 3, so as to cover the concave structure and the surface of the metal frame 1 facing the binding area 3.

The plastic layer covers the concave structure 10, so that the contact area of the pins 7, the metal frame 1 and the plastic layer 8 is increased, and when the cutting area 2 is cut later, the pins 7 are fixedly connected with the metal frame 1, and the pins 7 are prevented from falling off.

Step S4: the dicing area 2 is diced, and the package structure after dicing is shown in fig. 10, wherein the leads 7 are connected and fixed with the metal frame 1 through the plastic layer 8, and the leads 7 are disconnected from the metal frame 1. By the above packaging method, the packaging structure shown in fig. 4 can be obtained, the obtained packaging structure realizes the interconnection of the chips 9 fixed on different subareas 5, the problem of risk crossing lines is avoided, the cost is lower, and the low-cost mass production can be realized.

It should be noted that, in the step S5, the first plastic layer may be formed on a surface of the metal frame 1 facing away from the bonding area 3, and then the second plastic layer may be formed on the basis of the same surface of the bonding area 3.

In addition, in the above-described packaging method, the method of connecting the chips 9 fixed to the different sub-areas 5 by the connection structure 4 includes:

etching the same side surface of the binding area 3 to form a groove 6, wherein the groove 6 is positioned outside the subarea 5; the connecting structure 4 is arranged in the groove 6; the chips 9 fixed to the different sub-areas 5 are connected by the connection structures 4.

Wherein, the connection structure 4 is disposed in the groove 6, and the height of the connection structure 4 does not exceed the same side surface of the binding area 3. The method of etching the same side surface of the binding area 3 to form the groove 6 generally adopts a half etching process.

In addition, the method of forming the connection structure 4 includes: forming an insulating layer on a side of the metal frame 1 facing the connection structure 4; a conductive layer is formed on the side of the insulating layer facing away from the metal frame 1.

Wherein, the insulating layer is formed by using Mask to brush glue or paste film. When the conductive layer is formed, conventional electroplating cannot be realized due to the existence of the insulating layer, so that the conductive layer is formed by adopting a mode of curing a mold brush layer.

According to the packaging substrate, the packaging structure and the manufacturing method thereof provided by the embodiment of the invention, the connecting structure is added between the packaging substrate and the packaging structure, and the interconnection between chips is realized through the connecting structure, so that low-cost mass production can be realized on the premise of solving the risk cross line.

In the present specification, each embodiment is described in a combination of progressive and parallel manner, and each embodiment is mainly described and is different from other embodiments, and identical and similar parts between the embodiments are all enough to be seen with each other.

It should be noted that, in the description of the present application, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "top", "bottom", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific direction, be configured and operated in the specific direction, and thus should not be construed as limiting the present application. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or apparatus that comprises such element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (13)

1. A package substrate, comprising:

the metal substrate comprises a plurality of metal frames, and cutting areas are arranged between adjacent metal frames;

the metal frame includes: binding area; the same side surface of the binding area is provided with a connecting structure and at least two sub-areas, the sub-areas are used for fixing chips, and the connecting structure is used for connecting and fixing chips in different sub-areas.

2. The package substrate of claim 1, wherein the bonding region has a groove, the groove being located outside the sub-region; wherein, the connection structure is located in the recess.

3. The package substrate of claim 2, wherein the connection structure is located within the recess and the height of the connection structure does not exceed the surface.

4. The package substrate of claim 1, wherein the connection structure comprises:

an insulating layer positioned on one side of the metal frame facing the connecting structure;

and the conductive layer is positioned on one side of the insulating layer, which is away from the metal frame.

5. The package substrate of claim 4, wherein the insulation layer has a shore hardness greater than 90.

6. A package structure, comprising:

a metal frame; the metal frame includes: the binding area is provided with a connecting structure and at least two sub-areas on the same side surface;

the chips are fixed on the subareas, each subarea is fixed with one chip, and different chips are connected through the connecting structure;

the metal frame further comprises a pin for connecting an external circuit, the pin is disconnected with the binding area, and the pin is connected with the chip.

7. The package structure of claim 6, wherein the binding region has a groove, the groove being located outside the sub-region; wherein, the connection structure is located in the recess.

8. The package structure of claim 7, wherein the connection structure is located within the recess and a height of the connection structure does not exceed the surface.

9. The package structure of claim 6, wherein the connection structure comprises:

an insulating layer positioned on one side of the metal frame facing the connecting structure;

and the conductive layer is positioned on one side of the insulating layer, which is away from the metal frame.

10. The package structure of claim 6, further comprising: and the plastic sealing layer surrounds the metal frame and the chip, and the plastic sealing layer exposes parts of the pins.

11. A packaging method, characterized in that the packaging method comprises:

providing a packaging substrate, wherein the packaging substrate comprises a metal substrate, the metal substrate comprises a plurality of metal frames, and a cutting area is arranged between every two adjacent metal frames; the metal frame includes: binding area; a connection structure and at least two sub-regions located on the same side surface of the binding region; pins located outside the binding area;

fixing chips on the subareas, wherein the chips fixed on different subareas are connected through the connecting structure, and the chips are connected with the pins;

forming a plastic layer, wherein the plastic layer at least covers the surface of the metal frame facing to one side of the binding area;

cutting the cutting area.

12. The packaging method according to claim 11, wherein the method of connecting chips fixed to different ones of the sub-regions by the connection structure comprises:

etching the same side surface of the binding region to form a groove, wherein the groove is positioned outside the subarea;

the connecting structure is arranged in the groove;

and connecting and fixing chips in different subareas through the connecting structure.

13. The packaging method according to claim 12, wherein the connection structure is disposed in the groove, and a height of the connection structure does not exceed a same side surface of the binding region.

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