CN115995256A - Self-calibration current programming and current calculation type memory calculation circuit and application thereof - Google Patents
Self-calibration current programming and current calculation type memory calculation circuit and application thereof Download PDFInfo
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Abstract
The invention provides a self-calibration current programming and current calculation type in-memory calculation circuit and application thereof, and belongs to the technical field of novel storage and calculation. The invention relates to a calculation unit which is composed of two current programming multivalued eDRAM units through pseudo-differential combination, wherein the current programming multivalued eDRAM units are composed of three transistors and a storage capacitor, the three transistors are a write-in transistor and two readout transistors connected with a self-source common gate, and the operation of an internal calculation circuit is realized by a current programming circuit. Compared with the traditional voltage programming current calculation type memory calculation circuit, the current programming and current calculation of the invention can lead the analog memory calculation to have higher precision and energy efficiency, has better robustness on voltage, temperature and process fluctuation, and has wide application prospect.
Description
Technical Field
The invention relates to the field of integrated circuit design (integrated circuit design), in particular to a self-calibration current programming (current programming) and current calculation (current computing) in-memory computing circuit based on an embedded dynamic random access memory (embedded dynamic random access memory, eDRAM) and application thereof.
Background
In recent years, deep learning (deep learning) algorithms have achieved very good results in various fields. At the same time, the parameter scale of the deep neural network (deep neural networks) is also becoming larger and larger. The computation of the deep neural network is mainly dominated by matrix vector multiplication operations of large dimensions. When performing a large number of matrix vector multiplications using a conventional memory-separate computing architecture, a significant power consumption is often required for data handling, which is known as a memory wall (memory wall) problem. The memory wall problem makes it difficult for deep learning algorithms to be deployed to edge devices (edge devices) that have stringent requirements for power consumption. To solve this problem, a new computing architecture, an in-memory-computing architecture, has been proposed by designers in recent years.
The analog in-memory computing circuit is particularly highly energy efficient due to the characteristics of analog computation and the nature of parallel processing. In recent years, various new in-memory computing chips have been proposed, wherein eDRAM-based in-memory computing circuits, in particular, wherein design based on multi-valued cells, are receiving increasing attention due to their compatibility with standard complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) processes and higher memory density. In performing matrix vector multiplication, eDRAM-based in-memory computing circuits often apply inputs in the form of pulse widths to Word Lines (WL), activating multiple memory cells in the same row in parallel, and multiplying weights in the memory cells. At the same time, a plurality of rows of memory cells are activated in parallel, and the products of the inputs and weights on a plurality of memory cells on the same column are accumulated in the form of currents on Bit Lines (BL). Because the accumulation operation is directly completed on the bit line, the weight data in the memory does not need to be read out, and the embedded dynamic random access memory internal computing circuit based on the computing mode has high throughput and energy efficiency.
Although eDRAM analog in-memory computing circuit based on multi-value units brings about great energy efficiency and throughput improvement, analog computation is easy to be subjected to transistor non-idealityAnd voltage, temperature and process fluctuations, resulting in a decrease in computational accuracy. At the same time, transistor non-idealities limit further increases in their energy efficiency. First, the in-memory computation circuit needs to operate with a small computation current. Because with the same bit line capacitance, smaller computation current means more rows in the in-memory compute array can be turned on simultaneously to complete the computation, with higher energy efficiency and throughput. However, the smaller the calculation current is, the larger the fluctuation is, resulting in a decrease in calculation accuracy. Second, due to transistor gate voltage (V GS ) With source drain current (I) DS ) The programming of multiple-valued eDRAM cells requires calibration, and the power consumption area overhead incurred for calibrating each cell would be unacceptable in the presence of memory cell fluctuations.
The root cause of the above problem arises because the weight representation at programming is not consistent with the weight representation at computation: the multi-value weight data is written in the form of a voltage and stored in the memory cell at the gate terminal of the calculation transistor, and the corresponding transistor current is used for calculation. Due to the non-linear relationship between the gate voltage and the source leakage current of the transistor itself, the threshold voltage (V TH ) Although the weight data is accurately programmed in the form of voltages and stored in eDRAM cells, it is not accurate to calculate the current at the time of calculation. In addition, when accumulation is completed on the bit line, there is a problem in that the calculated current varies with the voltage variation of the bit line due to the limited output impedance of the transistor.
Therefore, a new programming and computing mode is needed to solve the problem of accurate programming and computing of multi-valued eDRAM and further improve the energy efficiency and throughput of the eDRAM-based analog in-memory computing circuit.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a self-calibration current programming and current calculation type in-memory calculation circuit and application thereof, which can carry out high-precision multi-value programming on a multi-value eDRAM unit and ensure the precision of calculating current under small current.
The technical scheme provided by the invention is as follows:
the self-calibration current programming and current calculation type memory calculating circuit comprises an array formed by calculating units, a voltage-current two-step programming driving circuit and a peripheral circuit, and is characterized in that the calculating units are formed by combining two current programming multivalued eDRAM units through pseudo-difference, the current programming multivalued eDRAM units are formed by three transistors and a storage capacitor, the three transistors are a writing-in tube and two reading-out transistors which are connected with a self-common source and a common grid respectively, the source end and the drain end of the writing-in tube are connected with a bit line and a storage node respectively, and the grid end of the writing-in tube is connected with a writing line (WWL). The two self-source and common-gate connected read transistors are respectively a low threshold transistor, a high threshold transistor, the drain terminal of the low threshold transistor is connected to the bit line, the source terminal of the low threshold transistor is connected with the drain terminal of the high threshold transistor, the drain terminal of the high threshold transistor is connected to a Read Word Line (RWL), the gate terminals of the low threshold transistor and the high threshold transistor are connected to a storage node, one end of the storage capacitor is connected to the storage node, the other end of the storage capacitor is grounded, the external interfaces of the current programming multivalued eDRAM unit are bit lines, write word lines and read word lines, and two adjacent current programming multivalued eDRAM units form a calculation unit through pseudo-differential combination, so that the signed weight storage and calculation can be completed. When the weight current is written, positive pulse and negative pulse are respectively applied to the writing word line and the reading word line, two reading transistors connected with the self-cascade of the eDRAM are in diode connection state, the written weight current WC/weight current WCb flows through two currents in the computing unit to program the eDRAM unit through the bit line BL/bit line BLb, self-calibration storage voltage is generated on the storage node SN/storage node SNb, when the weight current is calculated, the writing word line is in low level, the negative pulse is applied to the reading word line, the reading transistors connected with the self-cascade of the eDRAM are turned on, the bit line BL/bit line BLb is discharged, the discharged current value is the weight current when programming, the activation value is input into the computing unit through the pulse width of the reading word line, the activation value is multiplied by the weight, the bit line BL and the bit line BLb are discharged, and the multiplication result is reflected on the voltage difference between the bit line BL and the bit line BLb.
Further, the voltage-current two-step program driving circuit includes 2 write voltage sources and 1 write current source, wherein the first write voltage source is used for pulling the bit line BL and the bit line BLb to a low level when writing a zero weight, and pulling one side of the bit line BL and the bit line BLb to a low level when writing a non-zero weight. The second write voltage source and the write current source are used for fast writing the weight current.
In the programming mode, the self-calibration current programming and the programming method of the current calculation type in-memory computing circuit are provided according to different weight data, and the programming method specifically comprises 3 modes: write zero weight, write positive weight, and write negative weight.
When zero weight is written: the write word line of the selected row in the array is at a high level, the read word line is at a low level, the storage nodes of two eDRAM cells in the compute unit are connected to the corresponding bit lines, and the eDRAM cells are in a "diode connected" state. The voltage source 1 in the voltage-current two-step programming driving circuit is connected to the bit line BL and the bit line BLb, and pulls the bit line BL, the bit line BLb, the storage node SN of the computing unit and the storage node SNb to low level.
When writing positive weights: the write word line of the selected row in the array is at a high level, the read word line is at a low level, the storage nodes of two eDRAM cells in the compute unit are connected to the corresponding bit lines, and the eDRAM cells are in a "diode connected" state. The voltage source 1 in the voltage-current two-step program driving circuit is connected to the bit line BLb, pulling the bit line BLb and the storage node SNb of the calculation unit to a low level. Two steps are required for programming the bit line BL and the storage node SN: first step) voltage source 2 is connected to bit line BL, which pulls the storage node SN voltage of the bit line BL and eDRAM cells rapidly to 0.5 volts. Second step): a current source is connected to the bit line BL, the current value of which is proportional to the absolute value of the weight, and the current flowing through the diode-connected sense transistor generates a corresponding self-calibration voltage at the storage node SN, so that the current value is accurately stored. The write word line of the selected row in the array is then at a low level, the read word line is at a high level, and programming is completed. The voltage corresponding to the write current is stored on the storage node SN of the eDRAM cell.
When writing negative weights: the write word line of the selected row in the array is at a high level, the read word line is at a low level, the storage nodes of two eDRAM cells in the compute unit are connected to the corresponding bit lines, and the eDRAM cells are in a "diode connected" state. The voltage source 1 in the voltage-current two-step programming driving circuit is connected to the bit line BL, pulling the bit line BL and the storage node SN of the calculation unit low. The programming of the bit line BLb and the storage node SNb requires two steps: first step) voltage source 2 is connected to bit line BLb to rapidly pull the voltage at bit line BLb and storage node SNb of the memory cell to 0.5 volts. Second step): a current source is connected to the bit line BLb, the current value of which is proportional to the absolute value of the weight, and a current flowing through the diode-connected sense transistor generates a corresponding self-calibration voltage at the storage node SNb, so that the current value is accurately stored. The write word line of the selected row in the array is then at a low level, the read word line is at a high level, and programming is completed. The voltage corresponding to the write current is stored on the storage node SNb of the eDRAM cell.
Further, the operation method of the self-calibration current programming and current calculation type in-memory calculation circuit is characterized in that the specific operation comprises three steps: bit line precharge, analog computation, and analog to digital conversion.
Bit line precharge: the sampling enable signal is set high, the precharge enable signal is set high, all bit lines BL and BLb are charged to the precharge voltage, and then the precharge enable signal is set low, and the precharge is finished.
Simulation calculation: and converting different activation values into different read word line pulse widths according to the values in the corresponding activation value registers, and controlling the opening time of each row of computing units. The compute cells are turned on and the bit line BL/BLb is discharged, and the voltage difference of each cell discharging the bit line BL/BLb is the product of the activation value and the weight. All cells on each column discharge the bit line BL/BLb at the same time, so that the voltage difference of each column of bit line BL/BLb is the result of multiplying the column weight by the active value and is sampled by the analog-to-digital converter.
Analog-to-digital conversion: the sample enable signal is set low, ending the sampling. The analog-to-digital converter quantizes the sampled analog multiply-accumulate result.
The invention has the technical effects that:
compared with the traditional voltage programming current calculation type memory calculation circuit, the current programming and current calculation of the invention can enable the analog weight writing of the multi-value eDRAM to be more accurate, and simultaneously enable the analog memory calculation circuit to have higher precision and energy efficiency and better robustness to voltage, temperature and process fluctuation.
Drawings
FIG. 1 is a schematic diagram of a current programmed multi-valued eDRAM cell of the present invention.
FIG. 2 is a schematic diagram of a computing unit according to the present invention, wherein (a) is a schematic diagram of a computing unit; (b) a schematic diagram of the operation of a computing unit when writing weights; (c) is a schematic diagram of the operation of a computing unit in computing.
FIG. 3 is a schematic diagram and corresponding relation between the weight and the activation value and the parameters of the computing unit when the computing unit of the present invention computes, wherein (a) is the corresponding relation between the weight and the activation value, the read word line pulse width and the current of the computing unit; (b) Schematic diagram of write word line, read word line, weighting current WC/counter WCb and bit line BL/bit line BLb when calculated by one calculation unit.
FIG. 4 is a schematic diagram of a voltage-current two-step programming driving circuit according to the present invention.
FIG. 5 is a schematic diagram of a voltage-current two-step programming driving circuit of the present invention in writing zero weights, positive weights and negative weights, wherein (a) is a schematic diagram of writing zero weights; (b) is a schematic diagram of writing positive weights; (c) is a schematic diagram of writing negative weights.
FIG. 6 is a schematic diagram of the voltage/current two-step programming driving circuit of the present invention when programming a computing unit.
FIG. 7 is a block diagram illustrating the overall architecture of one embodiment of a self-calibrating current programming and current-calculation in-memory calculation circuit according to the present invention.
FIG. 8 is a timing diagram of the self-calibration current programming and current calculation type in-memory calculation circuit according to the present invention.
Detailed Description
The invention will be further elucidated by means of specific embodiments in conjunction with the accompanying drawings.
As shown in fig. 1, the current programming multivalued eDRAM cell is composed of three transistors and a storage capacitor, wherein transistor 1 is a write-in transistor, and transistor 2 and transistor 3 are read-out transistors connected from a cascode. The source end and the drain end of the writing tube are respectively connected with the bit line and the storage node, and the gate end is connected with the writing line. The transistor 2 of the two self-cascode connected read transistors is a low threshold transistor and the transistor 3 is a high threshold transistor. The drain terminal of transistor 2 is connected to the bit line, the source terminal is connected to the drain terminal of transistor 3, the drain terminal of transistor 3 is connected to the read word line, and the gate terminals of both transistor 2 and transistor 3 are connected to the storage node. The storage capacitor has one end connected to the storage node and one end grounded. The external interfaces of the current programming multivalued eDRAM unit are bit lines, write word lines and read word lines.
As shown in fig. 2 (a), two current programming multivalued eDRAM cells form a computation unit capable of storing symbol weight data through pseudo-differential combination, and external interfaces are bit line BL/bit line BLb, write word line and read word line. As shown in fig. 2 (b), when the weight current is written, a positive pulse and a negative pulse are applied to the write word line and the read word line, respectively, the self-cascode read transistor of the eDRAM in the computation unit is in a diode-connected state, and the written weight current WC/weight current WCb programs the eDRAM cell through the current flowing through the bit line BL/bit line BLb on both sides, generating a self-calibrated storage voltage on the storage node SN/storage node SNb, as shown in fig. 2 (c). During calculation, the write word line is at a low level, a negative pulse is applied to the read word line, and a self-cascode read transistor of the eDRAM in the calculation unit is turned on to discharge the bit line BL/bit line BLb, and the discharged current value is a weight current at the time of programming. As shown in fig. 3, signed 4-bit (15 current states) weights may be stored in the computing unit in the form of a current, and 4-bit activation values may be given to the computing unit by the read word line pulse width. The activation value is multiplied by the weight, discharging the bit line BL and the bit line BLb, and the result of the multiplication is reflected on the voltage difference between the bit line BL and the bit line BLb.
As shown in fig. 4, the voltage-current two-step programming driving circuit includes 2 writing voltage sources, 1 writing current source and a switch, wherein the writing voltage source 1 is used for writing zero weight to pull the bit line BL and the bit line BLb to low level, and writing non-zero weight to pull one side of the bit line BL and the bit line BLb to low level. The write voltage source 2 and the write current source are used for fast write weight currents.
When zero weight is written: voltage source 1 (0.0 v) in the voltage-current two-step programming driving circuit is connected to bit line BL and bit line BLb, pulling both bit line BL, bit line BLb and storage node SN, SNb of the compute unit low as shown in fig. 5 (a).
When writing positive weights: the write word line of the selected row in the array is at a high level (1.0 volts), the read word line is at a low level (0.0 volts), the storage nodes of two eDRAM cells in the compute unit are connected to the corresponding bit lines, and the eDRAM cells are in a "diode connected" state. Voltage source 1 (0.0 volt) in the voltage-current two-step programming drive circuit is connected to bit line BLb, pulling bit line BLb and storage node SNb of the compute unit low. The programming of the bit line BL and the storage node SN as shown in FIG. 5 (b) requires two steps: first step) voltage source 2 is connected to bit line BL, which pulls the storage node SN voltage of the bit line BL and eDRAM cells rapidly to 0.5 volts. Second step): a current source is connected to the bit line BL, the current value of which is proportional to the absolute value of the weight, and the current flowing through the diode-connected sense transistor generates a corresponding voltage at the storage node. The write word line of the selected row in the column is then low, the read word line is high, and programming is complete. The voltage corresponding to the write current is stored on the storage node SN of the eDRAM cell.
When writing negative weights: the write word line of the selected row in the array is at a high level (1.0 volts), the read word line is at a low level (0.0 volts), the storage nodes of two eDRAM cells in the compute unit are connected to the corresponding bit lines, and the eDRAM cells are in a "diode connected" state. Voltage source 1 (0.0 volt) in the voltage-current two-step programming drive circuit is connected to the bit line BL, pulling the bit line BL and the storage node SN of the compute unit low. The programming of the bit line BLb and the storage node SNb as shown in fig. 5 (c) requires two steps: first step) voltage source 2 is connected to bit line BLb to rapidly pull the voltage at bit line BLb and storage node SNb of the memory cell to 0.5 volts. Second step): a current source is connected to the bit line BLb, the current value of which is proportional to the absolute value of the weight, and which flows through the diode-connected sense transistor to generate a corresponding voltage at the storage node. The write word line of the selected row in the column is then low, the read word line is high, and programming is complete. The voltage corresponding to the write current is stored on the storage node SNb of the eDRAM cell.
The waveforms of the voltage and current on the bit line when performing the two-step writing are shown in fig. 6.
FIG. 7 is a block diagram illustrating the overall architecture of one embodiment of a self-calibrating current programming and current computation in-memory computation circuit according to the present invention.
As shown in fig. 7, in the present embodiment, n=m=1, and the analog in-memory computing circuit of the present embodiment includes a 64×64 computing cell array and peripheral circuits;
64x64 computational cell array. Each column of the calculation units is connected together through bit lines BL and bit lines BLb, and the number of the bit lines BL and the bit lines BLb is 64, namely, the 1 st to 64 th bit lines BL and the 1 st to 64 th bit lines BLb; each row of computing units is connected together through a writing word line and a reading word line, and the number of the writing word line and the reading word line is 64, namely the 1 st to 64 th writing lines and the 1 st to 64 th reading word lines;
the peripheral circuit comprises a write control circuit for weight programming, a write word line/read word line drive, a 64x weight register and a 64x voltage current two-step write drive circuit; a read control circuit, a 64x analog-to-digital conversion circuit, a bit line precharge circuit, a 64x activation value register, and a 64x digital time conversion circuit for calculation;
the 64x weight registers are registered with weight data, each weight register is connected to each write driving circuit in the 64x voltage-current two-step write driving circuit, and each voltage-current two-step write driving circuit is connected to each bit line BL and bit line BLb; the respective channels of the write word line/read word line drive are connected to each write word line and read word line, respectively.
The 64x activation value registers are registered with activation value data, each activation value register is connected to a digital time conversion circuit in the 64x digital time conversion circuit, and each digital time conversion circuit is connected to each read word line; each channel of the bit line precharge circuit is connected to each bit line BL and bit line BLb; each of the 64x analog-to-digital conversion circuits is connected to each of the bit lines BL and BLb.
Before computation, the weight data is written into the compute array by a write control circuit, a write word line/read word line driver, a 64x weight register, and a 64x voltage current two-step write driver circuit. As shown in fig. 8, the calculation in this embodiment includes the following steps:
bit line precharge: the sample enable signal is set high and the precharge enable signal is set high, all bit lines and bit line BLb are charged to a precharge voltage (1.0 volt), and then the precharge enable signal is set low and the precharge is ended.
Simulation calculation: the digital time conversion circuit converts different activation values into different read word line pulse widths according to the values in the corresponding activation value registers, and controls the opening time of each row of calculation units. The calculation units are turned on, discharging the bit lines BL/BLb, and the voltage difference of each calculation unit discharging the bit lines BL/BLb is the product of the activation value and the weight. All the computation units on each column discharge the bit line BL/BLb at the same time, so that the voltage difference of each column of bit line BL/BLb is the result of multiplying and accumulating the column weight and the activation value, and is sampled by the analog-to-digital converter.
Analog-to-digital conversion: the sample enable signal is set low, ending the sampling. The analog-to-digital converter quantizes the sampled analog multiply-accumulate result
Finally, it should be noted that the examples are disclosed for the purpose of aiding in the further understanding of the present invention, but those skilled in the art will appreciate that: various alternatives and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the disclosed embodiments, but rather the scope of the invention is defined by the appended claims.
Claims (6)
1. The self-calibration current programming and current calculation type memory calculation circuit comprises an array formed by calculation units, a voltage-current two-step programming driving circuit and a peripheral circuit, and is characterized in that the calculation units are formed by combining two current programming multivalued eDRAM units through pseudo-differential, the current programming multivalued eDRAM units are formed by three transistors and a storage capacitor, the three transistors are respectively a writing tube and two reading transistors connected with a self-common source and a common gate, the source end and the drain end of the writing tube are respectively connected with a bit line and a storage node, the gate end of the writing tube is connected with a writing line, the two reading transistors connected with the self-common source and the common gate are respectively a low threshold transistor and a high threshold transistor, the drain end of the low threshold transistor is connected with a bit line, the source end of the low threshold transistor is connected with the drain end of the high threshold transistor, the drain terminal of the high threshold transistor is connected to the read word line, the gate terminals of the low threshold transistor and the high threshold transistor are connected to the storage node, one end of the storage capacitor is connected to the storage node, the other end of the storage capacitor is grounded, the external interface of the computing unit is a bit line BL, a bit line BLb, a write word line and a read word line, when the weight current is written, positive pulses and negative pulses are respectively applied to the write word line and the read word line, two read transistors connected with the self-cascode of the current programming multivalue eDRAM are in a diode connection state, the written weight current WC/weight current WCb respectively flows into two current programming multivalue eDRAM units of the computing unit through the bit line BL/bit line BLb, self-calibration storage voltage is generated on the storage node SN/storage node SNb in the current programming eDRAM units, when the computing unit is in a low level, the negative pulses are applied to the read word line, the two read transistors connected by the self-cascades of the current programming multivalue eDRAM are turned on, the bit line BL/bit line BLb is discharged, the discharged current value is the weight current during programming, the activation value is given to the calculation unit through the read word line pulse width, the activation value is multiplied by the weight, the bit line BL and the bit line BLb are discharged, and the product result is reflected on the voltage difference between the bit line BL and the bit line BLb.
2. The self-calibrating current programming and current-calculating in-memory computing circuit of claim 1, wherein the voltage-current two-step programming drive circuit comprises two write voltage sources and a write current source, wherein a first write voltage source is used for writing zero weights to pull bit lines and bit lines back low, and a second write voltage source is used for writing non-zero weights to pull one side of bit lines and bit lines back low.
3. A self-calibration current programming and current calculation type in-memory calculation circuit programming method is characterized by comprising the steps of writing zero weight, writing positive weight and writing negative weight, wherein:
when zero weight is written: the write word line of the selected row in the array is at a high level, the read word line is at a low level, the storage nodes of two eDRAM units in the computing unit are connected to corresponding bit lines, a first voltage source in the voltage-current two-step programming driving circuit is connected to the bit lines and the bit lines BLb, and the bit lines BL and the bit lines BLb and the storage nodes SN and SNb of the computing unit are pulled to the low level;
when writing positive weights: the write word line of the selected row in the array is at a high level, the read word line is at a low level, the storage nodes of two eDRAM units in the computing unit are connected to corresponding bit lines, a first voltage source in the voltage-current two-step programming driving circuit is connected to the bit line BLb, and the bit line BLb and the storage node SNb of the computing unit are pulled to the low level;
when writing negative weights: the write word line of the selected row in the array is at a high level, the read word line is at a low level, the storage nodes of two eDRAM cells in the compute unit are connected to the corresponding bit lines, a first voltage source in the voltage-current two-step programming drive circuit is connected to the bit line BL, and the bit line BL and the storage node SN of the compute unit are pulled to a low level.
4. The method of programming a self-calibrating current programming and current-calculation-in-memory computation circuit of claim 3, wherein programming the bit line BL and the storage node SN comprises:
1) A second voltage source in the voltage-current two-step programming driving circuit is connected to the bit line BL, and the voltages of the bit line BL and the storage node SN of the eDRAM unit are rapidly pulled to 0.5V;
2) The current source is connected to the bit line, the current value of the current source is proportional to the absolute value of the weight, the current flows through the diode-connected sense transistor to generate a corresponding self-calibration voltage at the storage node SN, then the write word line of the selected row in the array is at a low level, the read word line is at a high level, and the voltage corresponding to the write current is stored at the storage node SN of the eDRAM cell.
5. The method for programming a self-calibrating current programming and current-calculation-in-memory computation circuit of claim 3, wherein programming the bit line BLb and the storage node SNb comprises:
1) A second voltage source in the voltage-current two-step programming driving circuit is connected to the bit line BLb, and the voltages of the bit line BLb and the storage node SNb of the storage unit are rapidly pulled to 0.5V;
2) The current source is connected to the bit line BLb, the current value of the current source is proportional to the absolute value of the weight, the current flows through the diode-connected read transistor to generate a corresponding self-calibration voltage at the storage node SNb, the write word line of the selected row in the array is then at a low level, the read word line is at a high level, and the voltage corresponding to the write current is stored at the storage node SNb of the eDRAM cell.
6. A self-calibrating current programming and operation method of a current calculation type in-memory calculation circuit is characterized by comprising the following specific steps: bit line precharge, analog computation, and analog-to-digital conversion:
bit line precharge: the sampling enabling signal is set high, the pre-charging enabling signal is set high, all bit lines BL and BLb are charged to the pre-charging voltage, and then the pre-charging enabling signal is set low, and the pre-charging is finished;
simulation calculation: converting different activation values into different read word line pulse widths according to the values in the corresponding activation value registers, controlling the opening time of each row of calculation units, opening the calculation units, discharging the bit lines BL/BLb, wherein the voltage difference of each calculation unit discharging the bit lines BL/BLb is the product of the activation value and the weight; all the calculation units on each column discharge the bit line BL/bit line BLb at the same time, so that the voltage difference of each column of bit line BL/bit line BLb is the result of multiplying and accumulating the column weight and the activation value, and is sampled by an analog-to-digital converter;
analog-to-digital conversion: the sampling enable signal is set low, the sampling is finished, and the analog-to-digital converter quantizes the sampled analog multiply-accumulate result.
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