CN115994509A - Chip layout method, device, electronic equipment and storage medium - Google Patents
Chip layout method, device, electronic equipment and storage medium Download PDFInfo
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- CN115994509A CN115994509A CN202310137322.XA CN202310137322A CN115994509A CN 115994509 A CN115994509 A CN 115994509A CN 202310137322 A CN202310137322 A CN 202310137322A CN 115994509 A CN115994509 A CN 115994509A
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Abstract
The application provides a chip layout method, a chip layout device, an electronic apparatus and a computer readable storage medium. The method comprises the following steps: determining a functional module corresponding to the target unit according to the name of the target unit; searching the units of the chip to find out the associated units associated with the target units; and arranging the target unit and the association unit in the area corresponding to the functional module. According to the method and the device, the related units can be arranged in the same area, so that the overall performance is improved, and the delay is reduced.
Description
Technical Field
The present invention relates to the field of chip design, and in particular, to a chip layout method, a chip layout apparatus, an electronic device, and a computer readable storage medium.
Background
Layout of cells in a chip is a well known technique in the art of chip design. In the existing layout operation, only the units to which the functional modules to which they belong can be recognized are arranged in a specific area, and the associated units are not considered. This arrangement often results in the associated cells being placed far apart, resulting in increased latency.
Disclosure of Invention
To this end, the present application has been made in an effort to provide a chip layout method, a chip layout apparatus, an electronic device, and a computer-readable storage medium, which are capable of arranging units associated with each other in the same area, reducing an overall delay.
In one aspect, the present application provides a chip layout method, including: determining a functional module corresponding to the target unit according to the name of the target unit; searching the units of the chip to find out the associated units associated with the target units; and arranging the target unit and the association unit in the area corresponding to the functional module.
According to a particular embodiment of the present application, searching the cells of the chip for an associated cell associated with the target cell includes: performing primary search on the units of the chip to find a plurality of primary association units directly associated with the target unit; and carrying out secondary search on the units of the chip to find a plurality of secondary association units directly associated with each primary association unit in the plurality of primary association units.
According to a particular embodiment of the present application, performing a secondary search on a unit of a chip to find a plurality of secondary association units directly associated with each of a plurality of primary association units, includes: when the number of the plurality of secondary association units found for the secondary search of the primary association unit exceeds a specific value, discarding the secondary search results for the primary association unit.
According to a particular embodiment of the present application, the specific value is between 5 and 15.
According to a particular embodiment of the present application, the specific value is 10.
According to a particular embodiment of the present application, the target unit includes a register.
According to a particular embodiment of the present application, the association unit includes one or more of registers, look-up tables, adders, multiplexers.
In another aspect, the present application provides a chip layout apparatus, comprising: the determining module is used for determining a functional module corresponding to the target unit according to the name of the target unit; the search module is used for searching the units of the chip and finding out the association units associated with the target units; and the layout module is used for laying out the target unit and the association unit in the area corresponding to the functional module.
In another aspect, the present application provides an electronic device comprising: a processor; a memory; an application program stored in the memory and configured to be executed by the processor, the application program including instructions for performing the chip layout method described above.
In another aspect, the present application provides a computer readable storage medium storing a computer program for executing the above-described chip layout method.
According to the method and the device, the target unit of the functional module is easily identified to determine the placement area, and meanwhile, the unit associated with the target unit is found through searching and is also placed in the area, so that the units associated with each other are placed in the same area, delay is reduced, and overall performance is improved.
Drawings
The following detailed description of specific embodiments of the present application refers to the accompanying drawings, in which:
FIG. 1 shows a flow diagram of a chip layout method according to an embodiment of the present application;
FIG. 2 shows a schematic diagram of search results according to the embodiment of FIG. 1;
FIG. 3 shows a schematic diagram of a chip layout apparatus according to an embodiment of the present application;
fig. 4 shows a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the concepts and concepts of the present application more clearly understood by those skilled in the art, the present application is described in detail below in conjunction with specific embodiments. It should be understood that the embodiments presented herein are only a part of all embodiments that the application may have. Those skilled in the art, after having read the present specification, will be able to make improvements, modifications, or substitutions in part or in whole of the embodiments described below, which are also included within the scope of the present application.
The terms "a," "an," and other similar words are not intended to mean that there is only one of the things, but rather that the description is directed to only one of the things, which may have one or more. In this document, the terms "comprise," "include," and other similar words are intended to denote a logical relationship, but not to be construed as implying a spatial structural relationship. For example, "a includes B" is intended to mean that logically B belongs to a, and not that spatially B is located inside a. In addition, the terms "comprising," "including," and other similar terms should be construed as open-ended, rather than closed-ended. For example, "a includes B" is intended to mean that B belongs to a, but B does not necessarily constitute all of a, and a may also include other elements such as C, D, E.
The terms "first," "second," and the like, herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The terms "embodiment," "this embodiment," "an embodiment," "one embodiment," and the like herein do not denote that the descriptions are merely applicable to one particular embodiment, but rather denote that the descriptions are also applicable to one or more other embodiments. It will be appreciated by those skilled in the art that any descriptions of one embodiment herein may be substituted, combined, or otherwise combined with those described in relation to another embodiment or embodiments, such substitution, combination, or other combination resulting in a new embodiment as would be apparent to one of ordinary skill in the art and would be within the scope of this application.
In various embodiments of the present application, a chip may be referred to as an integrated circuit, or microcircuit, microchip, wafer/chip, which is a way in electronics to miniaturize circuits (including mainly semiconductor devices, also including passive components, etc.) and is often manufactured on a semiconductor wafer surface. For example, the chip may include a central processing unit (Central Processing Unit, CPU), a graphics processor (Graphics Processing Unit, GPU), a Memory (Memory), a field programmable gate array (Field Programmable Gate Array, FPGA), or the like.
In embodiments of the present application, chip layout may refer to one step in chip design. Chip designs typically include front-end designs and back-end designs; the front end design may include RTL (Register Transfer Level ) design, verification, static timing analysis, coverage and logic synthesis; backend designs may include logic synthesis, formal verification, physical implementation (including floor plan, place, and route), clock tree synthesis, parasitic parameter extraction, and layout physical verification. For example, chip design may include the main steps of function definition, device type selection, design input, functional simulation, comprehensive optimization, comprehensive post-simulation, layout, routing, post-simulation, board level simulation, and chip programming and debugging.
In embodiments of the present application, the chip layout may refer to placing standard cells, I/O pads, macro cells to implement the entire circuit logic. For example, the chip layout may refer to a macro block for placing a chip, and the placement positions of various functional circuits, such as an IP block, a RAM, I/O pins, etc., are generally determined, so that the layout can directly affect the final area of the chip. The inputs of the layout can be the netlist information after packaging, constraint information of the chip and constraint information customized by a user, wherein the constraint information comprises physical constraints written in a constraint file of the user and time delay constraints written in a constraint file of the design, and the output of the layout can be the netlist after the layout for wiring by an automatic router. Chip layouts may generally include input-output layouts, global clock layouts, initial layouts, overall layouts, legal layouts, and detailed layouts. For example, the process of laying out generally includes global layout, legal layout, and detailed layout. In some layout processes, the layout also includes a region layout, i.e., region dividing some specified functional modules in the design.
In EDA (Electronic Design Automation ) design engineering, a number of units are often subjected to region layout, so that a group of functional modules are relatively close to each other in terms of location, so that the operation is more stable, and the expected effect can be achieved in terms of performance. REG (register) units in the netlist generated by the synthesis step are functional blocks whose correspondence can be basically confirmed by name. The REG units of these easily distinguishable functional modules are often constrained to a specified region if used in the region layout process after integration. For some designs, the area layout is done by designating some REGs, but the result is sometimes not ideal, the root cause of which is that some other non-REG units associated with REGs in the area are placed farther apart, resulting in a larger delay between them. For this case, we use the method of region-extended search to treat the cells associated with REGs in the region as the cell handling in this region as well.
Fig. 1 shows a flow diagram of a chip layout method according to an embodiment of the present application.
According to the present embodiment, the chip layout method includes steps S110 to S130, and each step is described in detail below.
S110, determining a functional module corresponding to the target unit according to the name of the target unit.
Target units may refer to those chip units that may be used to identify the identity of the functional module to which they belong. In the chip design process, a certain amount of information is given to each unit or unit in the netlist generated through logic synthesis before the chip layout step. For example, a name is given to each register. The corresponding functional module can be judged according to the name of the register.
As an example, the target unit includes a register.
S120, searching the units of the chip to find out the association units associated with the target units.
Searching for a cell of a chip may refer to performing a search operation in a netlist file to find a particular cell. The association unit associated with the target unit may be a unit directly associated with the target unit (directly connected, as an input source or an output object thereof), or may be a unit indirectly associated with the target unit (an association unit in which other units are present in the middle, as a unit directly associated therewith).
As an example, the association unit includes one or more of registers, look-up tables, adders, and multiplexers.
A register may refer to a commonly used sequential logic circuit, but such sequential logic circuit only includes a memory circuit. The storage circuit of the register is constituted by latches or flip-flops, and since one latch or flip-flop can store 1-bit binary numbers, an N-bit register can be constituted by N latches or flip-flops.
Look-Up tables (LUTs) may refer to data structures that replace arrays computed at run-time with simple query operations.
An Adder (ADD) may refer to a device that generates a sum of numbers. The means for adding the sum to the input and adding the sum to the carry to the output is a half adder. If the addend, the summand and the low order carry-in number are inputs, and the sum and carry-in number are outputs, the full adder is used. Are commonly used as arithmetic logic units in computers to perform logic operations, shifts, and instruction calls.
The Multiplexer (MUX) may refer to a circuit capable of selecting any one of the paths according to the need in the process of multiplexing data transmission, so as to achieve the purpose of channel expansion or multiplexing.
As an example, S120 may include a first level search, which may refer to performing a first level search on a unit of a chip to find a plurality of first level association units directly associated with a target unit, and a second level search, which may refer to performing a second level search on a unit of a chip to find a plurality of second level association units directly associated with each of the plurality of first level association units.
As an example, when the number of the plurality of secondary association units found for the secondary search of the primary association unit exceeds a certain value, the secondary search results for the primary association unit are discarded.
As an example, the specific value is between 5 and 15, for example, the specific value is 10.
In this embodiment, the unit associated with REG in the region may also be regarded as the unit process in this region by using the method of region-extended search. The region expansion search is divided into two-level search, and can be set as one-level search or two-level search by controlling variable users and developers, wherein the one-level search is to find out the units related to REG in the region before and after REG and treat the units as the units of region layout; the secondary search is based on the primary search (the associated units before and after REG) to find the associated units before and after the associated units, and the primary search associated units and the secondary search associated units are treated as the units of the regional layout. The number of fanouts may be limited in the secondary search to control the search range, for example, the number of fanouts is limited to 10, and if the number of units reached by a certain output signal of a certain associated unit of the primary search is greater than 10 in the secondary search, the secondary search of the output of the unit is ignored.
As an example, the units of the primary and secondary searches corresponding to one REG in the region are shown in fig. 2. The cells in the middle of the first row are REG, with in representing the input port and out representing the output port in each cell. The unit marked 1 in the figure is a result unit of the first-level search; and 2 is a result unit of the secondary search. The method has the advantage that the overall performance of the distributed area can be better improved.
S130, arranging the target unit and the association unit in the area corresponding to the functional module.
In this embodiment, after the specific functional module has a specific chip area and its functional module is determined according to the name of the target unit, both the target unit and the searched association unit may be disposed in the area corresponding to the functional module, which is beneficial to reducing delay.
Fig. 3 shows a schematic structural diagram of a chip layout device according to an embodiment of the present application.
According to the present embodiment, the chip layout apparatus 300 includes:
a determining module 310, configured to determine, according to the name of the target unit, a function module corresponding to the target unit;
the searching module 320 is configured to search the units of the chip to find an association unit associated with the target unit;
and a layout module 330, configured to layout the target unit and the associated unit in the area corresponding to the functional module.
In an embodiment, the search module 320 is further configured to:
performing primary search on the units of the chip to find a plurality of primary association units directly associated with the target unit;
and carrying out secondary search on the units of the chip to find a plurality of secondary association units directly associated with each primary association unit in the plurality of primary association units.
In an embodiment, the search module 320 is further configured to:
when the number of the plurality of secondary association units found for the secondary search of the primary association unit exceeds a specific value, discarding the secondary search results for the primary association unit.
In one embodiment, the specific value is between 5 and 15.
In one embodiment, the specific value is 10.
In one embodiment, the target unit includes a register.
In one embodiment, the association unit includes one or more of a register, a lookup table, an adder, and a multiplexer.
An electronic device according to an embodiment of the present application is described below in connection with fig. 4.
As shown in fig. 4, electronic device 400 includes one or more processors 410 and memory 420.
Processor 410 may be a Central Processing Unit (CPU) or other form of processing unit having data processing and/or instruction execution capabilities and may control other components in electronic device 400 to perform desired functions.
Memory 420 may include one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. The volatile memory may include, for example, random Access Memory (RAM) and/or cache memory (cache), and the like. The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, flash memory, and the like. One or more computer program instructions may be stored on the computer readable storage medium that can be executed by the processor 410 to implement the chip layout methods and/or other desired functions of the various embodiments of the present application described above.
In one example, the electronic device 400 may further include: input device 430 and output device 440, which are interconnected by a bus system and/or other form of connection mechanism (not shown).
For example, the input device 430 may be a microphone or microphone array for capturing voice input signals; a communication network connector for receiving the acquired input signal from the cloud or other device; and may also include, for example, a keyboard, mouse, etc.
The output device 440 may output various information to the outside, including the determined distance information, direction information, and the like. The output device 440 may include, for example, a display, speakers, a printer, and a communication network and remote output devices connected thereto, etc.
Of course, only some of the components of the electronic device 400 that are relevant to the present application are shown in fig. 4 for simplicity, components such as buses, input/output interfaces, etc. are omitted. In addition, electronic device 400 may include any other suitable components depending on the particular application.
Embodiments of the present application may also be a computer-readable storage medium, having stored thereon computer program instructions, which when executed by a processor, cause the processor to perform the steps in the chip layout method according to various embodiments of the present application described hereinabove.
The computer readable storage medium may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The concepts, principles and concepts of the application have been described above in connection with specific embodiments (including examples and illustrations). It will be appreciated by those skilled in the art that embodiments of the present application are not limited to the several forms set forth above, and that after reading the present application, those skilled in the art may make any possible modifications, substitutions, and equivalents of the steps, methods, apparatuses, and components of the above embodiments, which are intended to be within the scope of the present application. The protection scope of the present application is only subject to the claims.
Claims (10)
1. A chip layout method, comprising:
determining a function module corresponding to a target unit according to the name of the target unit;
searching the units of the chip to find the associated units associated with the target units;
and arranging the target unit and the association unit in the area corresponding to the functional module.
2. The chip layout method according to claim 1, wherein the searching the cells of the chip for the associated cells associated with the target cell comprises:
performing primary search on the units of the chip to find a plurality of primary association units directly associated with the target unit;
and carrying out secondary search on the units of the chip to find a plurality of secondary association units directly associated with each primary association unit in the plurality of primary association units.
3. The chip layout method according to claim 2, wherein the performing a secondary search on the cells of the chip to find a plurality of secondary association cells directly associated with each of the plurality of primary association cells comprises:
when the number of the plurality of secondary association units found for the secondary search of the primary association unit exceeds a specific value, discarding the secondary search results for the primary association unit.
4. A chip layout method according to claim 3, wherein the specific value is between 5 and 15.
5. The chip layout method according to claim 4, wherein the specific value is 10.
6. The chip layout method according to any one of claims 1 to 5, wherein the target unit includes a register.
7. The chip layout method of any one of claims 1 to 5, wherein the association unit comprises one or more of a register, a look-up table, an adder, and a multiplexer.
8. A chip layout apparatus, comprising:
the determining module is used for determining a functional module corresponding to the target unit according to the name of the target unit;
the searching module is used for searching the units of the chip and finding out the association unit associated with the target unit;
and the layout module is used for laying out the target unit and the association unit in the area corresponding to the functional module.
9. An electronic device, comprising:
a processor;
a memory;
an application program stored in the memory and configured to be executed by the processor, the application program comprising instructions for performing the chip layout method according to any one of claims 1 to 7.
10. A computer-readable storage medium storing a computer program for executing the chip layout method according to any one of claims 1 to 7.
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| CN202310137322.XA CN115994509A (en) | 2023-02-20 | 2023-02-20 | Chip layout method, device, electronic equipment and storage medium |
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| CN202310137322.XA CN115994509A (en) | 2023-02-20 | 2023-02-20 | Chip layout method, device, electronic equipment and storage medium |
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| CN115994509A true CN115994509A (en) | 2023-04-21 |
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