CN115988733A

CN115988733A - Printed circuit board

Info

Publication number: CN115988733A
Application number: CN202211526953.2A
Authority: CN
Inventors: 廖建兴
Original assignee: Shenzhen Queclink Communication Technology Co ltd
Current assignee: Shenzhen Queclink Communication Technology Co ltd
Priority date: 2022-12-01
Filing date: 2022-12-01
Publication date: 2023-04-18

Abstract

The application provides a printed circuit board, includes: the top layer and/or the bottom layer are/is provided with a wiring area, and at least one sensitive signal line is arranged in the wiring area; the first copper foil is arranged on one side of the wiring area, and the second copper foil is arranged on the other side of the wiring area; one or more middle layers arranged between the top layer and the bottom layer, wherein a third copper foil is arranged on the middle layers; the first through holes are formed in the first copper foil, penetrate through the first copper foil, and are connected with the third copper foil through copper on the hole wall of the first through holes; and the second via holes are arranged in the second copper foil, penetrate through the second copper foil, and are connected with the third copper foil through the copper on the hole walls of the second via holes. The application reduces the influence of peripheral electronic components on sensitive signal lines in the wiring area, and is favorable for guaranteeing the normal use of the printed circuit board.

Description

Printed circuit board

Technical Field

The application relates to the technical field of printed circuit boards, in particular to a printed circuit board.

Background

A PCB (Printed Circuit Board), i.e., a Printed Circuit Board, is one of important parts in the electronics industry. The printed circuit board is a support body of electronic components, a carrier for interconnecting the electronic components and an important component of the communication equipment.

With the increase of functions of communication equipment, more electronic components need to be arranged on a printed circuit board, which not only have various sensitive signal lines (such as radio frequency signal lines, microphone signal lines, and the like), but also have various interference sources (such as clock lines, digital routing lines, crystal oscillator pin pads, CPU core power lines, GPU power lines, and the like), and in addition, the size of the printed circuit board is smaller and smaller, the density of the printed circuit board is higher and higher, and the functions of the sensitive signal lines can be affected if the various interference sources are close to the sensitive signal lines, and even the normal use of products can be seriously affected. For example, a ground copper foil is required near a radio frequency signal line (one of the sensitive signal lines), and a large number of through holes (ground via holes) need to be punched on the ground copper foil, but a notching effect is formed due to an excessive density of the through holes (ground via holes), so that when the distance between interference sources such as power traces and digital traces around the radio frequency signal line (one of the sensitive signal lines) is short, indexes such as return loss of the radio frequency signal line (S11), voltage Standing Wave Ratio (VSWR), error Vector Magnitude (EVM), and reception sensitivity are affected.

Disclosure of Invention

In order to overcome the above-mentioned defect under the correlation technique, the utility model aims at providing a printed circuit board, the influence that this application can reduce electronic components on the printed circuit board and produce sensitive signal line ensures printed circuit board's normal use.

The application provides a printed circuit board, includes:

the top layer and/or the bottom layer are/is provided with a wiring area, and at least one sensitive signal line is arranged in the wiring area;

the first copper foil is arranged on one side of the routing area, and the second copper foil is arranged on the other side of the routing area;

one or more middle layers arranged between the top layer and the bottom layer, wherein a third copper foil is arranged on the middle layers;

the first through holes are formed in the first copper foil, penetrate through the first copper foil, and are connected with the third copper foil through copper on the hole wall of the first through holes;

and the second copper foils are connected with the third copper foils through the copper of the hole walls of the second via holes.

Optionally, the plurality of first vias includes a plurality of first laser holes and a plurality of first through holes, and the plurality of second vias includes a plurality of second laser holes and a plurality of second through holes.

Optionally, the first through hole and the second through hole penetrate through the printed circuit board, and the bottom layer, each of the middle layers and the top layer are electrically connected with the second through hole through the first through hole;

the first laser hole extends from the first copper foil to the third copper foil, a first copper column is arranged in the first laser hole, and the first copper foil and the third copper foil are electrically connected through the first copper column;

the second laser hole extends to the third copper foil from the second copper foil, a second copper column is arranged in the second laser hole, and the second copper foil and the third copper foil are electrically connected through the second copper column.

Optionally, the arrangement direction of the first through holes is the same as the routing direction of the sensitive signal line, and one or more first laser holes are arranged between two adjacent first through holes;

the arrangement direction of the second through holes is the same as the routing direction of the sensitive signal line, and one or more second laser holes are arranged between every two adjacent second through holes.

The printed circuit board as described above, optionally, at least one first laser hole is disposed between two adjacent first through holes; and/or at least one second laser hole is arranged between two adjacent second through holes.

Optionally, at least two first laser holes are disposed between two adjacent first through holes, and an arrangement direction of the at least two first laser holes is perpendicular to a routing direction of the sensitive signal line;

at least two second laser holes are arranged between every two adjacent second through holes, and the arrangement direction of the at least two second laser holes is perpendicular to the wiring direction of the sensitive signal line.

The printed circuit board as described above, optionally, two adjacent first laser holes are tangent, or a distance between two adjacent first laser holes is less than or equal to 1.5mm;

the adjacent two second laser holes are tangent, or the distance between the adjacent two second laser holes is less than or equal to 1.5mm;

the adjacent first laser holes are tangent to the first through holes, or the distance between the adjacent first laser holes and the first through holes is smaller than or equal to 1.5mm;

the adjacent second laser holes are tangent to the second through holes, or the distance between the adjacent second laser holes and the second through holes is smaller than or equal to 1.5mm.

Optionally, the arrangement direction of the plurality of first through holes is the same as the routing direction of the sensitive signal line, and one or more first laser holes are disposed between two adjacent first through holes;

and/or the arrangement direction of the plurality of second through holes is the same as the routing direction of the sensitive signal lines, the second through holes are arranged close to the plate edges of the printed circuit board, the second copper foil is also connected with a ground wire, and the routing direction of the ground wire is the same as that of the sensitive signal lines;

and/or one or more second laser holes are arranged between two adjacent second through holes, the arrangement direction of the second laser holes is the same as the routing direction of the sensitive signal line, the second through holes are arranged close to the plate edge of the printed circuit board, the second copper foil is further connected with a ground wire, and the routing direction of the ground wire is the same as the routing direction of the sensitive signal line.

Optionally, in the printed circuit board as described above, a plurality of the sensitive signal lines are disposed in the routing region, two adjacent sensitive signal lines are disposed at an interval, the sensitive signal line near one side of the first copper foil is disposed at an interval with the first copper foil, and the sensitive signal line near one side of the second copper foil is disposed at an interval with the second copper foil.

The printed circuit board as described above, optionally, further includes at least one first line and/or first trace;

the first circuit and/or the first routing are/is positioned on one side, away from the routing area, of the first copper foil; and/or the first line and/or the first trace are/is positioned on one side of the second copper foil, which is deviated from the trace area;

the first circuit comprises one or more of a power supply pad, a signal via hole and a power supply via hole; the first wire comprises one or more of a power wire and a signal wire.

As for the printed circuit board, optionally, the routing area is disposed on the top layer, at least one of the bottom layer and each of the middle layers is further provided with a second routing and/or a second line, and the second routing and/or the second line is located within a projection range of the first copper foil, the routing area, and the second copper foil;

and/or the wiring area is arranged on the bottom layer, at least one of the top layer and each middle layer is also provided with a second wiring and/or a second circuit, and the second wiring and/or the second circuit are positioned in the projection range of the first copper foil, the wiring area and the second copper foil.

As for the printed circuit board, optionally, the routing area is disposed on the top layer, at least one of the middle layers is further provided with a second routing and a second line, the bottom layer is provided with an electronic component, and the second routing, the second line and the electronic component are located within a projection range of the first copper foil, the routing area and the second copper foil.

The application provides a printed circuit board, includes: the top layer and/or the bottom layer are/is provided with a wiring area, and at least one sensitive signal line is arranged in the wiring area; the first copper foil is arranged on one side of the wiring area, and the second copper foil is arranged on the other side of the wiring area; one or more middle layers arranged between the top layer and the bottom layer, wherein a third copper foil is arranged on the middle layers; the first through holes are formed in the first copper foil, penetrate through the first copper foil, and are connected with the third copper foil through copper on the hole wall of the first through holes; and the second via holes are arranged on the second copper foil, penetrate through the second copper foil, and are connected with the third copper foil through the copper on the hole walls of the second via holes. This application is through setting up a plurality of first via holes and a plurality of second via hole on the first copper foil and the second copper foil of walking line region both sides respectively, be connected with the third copper foil in intermediate level through first via hole and second via hole, the noise that peripheral electronic components on the printed circuit board produced can couple to on the third copper foil in intermediate level, thereby the isolation between sensitive signal line and the peripheral electronic components has been increased, the influence that peripheral electronic components produced the sensitive signal line in to walking the line region has been reduced, be favorable to ensureing printed circuit board's normal use.

Drawings

In order to more clearly illustrate the embodiments of the present application or technical solutions in related arts, the drawings used in the description of the embodiments or related arts will be briefly described below, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a simplified top view of a printed circuit board according to one embodiment of the present application;

FIG. 2 is a cross-sectional view of a printed circuit board provided in an embodiment of the present application;

FIG. 3 is a simplified top view of a top layer of a printed circuit board according to one embodiment of the present application;

FIG. 4 is a cross-sectional view of the printed circuit board of FIG. 3 in one embodiment;

FIG. 5 is a cross-sectional view of the printed circuit board of FIG. 3 in another embodiment;

FIG. 6 is a cross-sectional view of the printed circuit board of FIG. 3 in yet another embodiment;

FIG. 7 is a cross-sectional view of the printed circuit board of FIG. 3 in yet another embodiment;

FIG. 8 is a cross-sectional view of the printed circuit board of FIG. 3 in yet another embodiment;

FIG. 9 is a simplified top view schematic diagram of a top layer of a printed circuit board according to another embodiment of the present application;

FIG. 10 is a simplified top view schematic diagram of a top layer of a printed circuit board according to yet another embodiment of the present application;

FIG. 11 is a simplified top view schematic diagram of a top layer of a printed circuit board according to yet another embodiment of the present application;

FIG. 12 is a simplified top view schematic diagram of a top layer of a printed circuit board according to yet another embodiment of the present application;

FIG. 13 is a simplified top view diagrammatic illustration of a top layer of a printed circuit board according to another embodiment of the present application;

FIG. 14 is a partial cross-sectional view of a printed circuit board according to an embodiment of the present invention between the top layer and the layer 2;

FIG. 15 is a partial cross-sectional view of a printed circuit board according to yet another embodiment of the present application, between the top layer and the layer 2;

FIG. 16 is a partial cross-sectional view of a printed circuit board according to another embodiment of the present application, taken between the top layer and layer 2;

FIG. 17 is a partial cross-sectional view of a printed circuit board according to another embodiment of the present application, taken between the top layer and the layer 2;

fig. 18 is a simplified top view schematic diagram of a top layer of a printed circuit board according to yet another embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments.

All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

FIG. 1 is a simplified top view of a printed circuit board according to one embodiment of the present application; fig. 2 is a cross-sectional view of a printed circuit board according to an embodiment of the present application.

Referring to fig. 1-2, the present embodiment provides a printed circuit board, including:

the top layer 1000 and the bottom layer 2000, the top layer 1000 and/or the bottom layer 2000 are provided with a routing area 1100, and at least one sensitive signal line 1110 is arranged in the routing area 1100.

The first copper foil 1200 is disposed on one side of the routing area 1100, and the second copper foil 1300 is disposed on the other side of the routing area 1100.

One or more intermediate layers 3000 disposed between the top layer 1000 and the bottom layer 2000, with a third copper foil 3100 disposed on the intermediate layers 3000.

And the plurality of first via holes are formed in the first copper foil 1200, penetrate through the first copper foil 1200, and the first copper foil 1200 is connected with the third copper foil 3100 through copper on the hole walls of the first via holes.

And the plurality of second via holes are formed in the second copper foil 1300, the second via holes penetrate through the second copper foil 1300, and the second copper foil 1300 is connected with the third copper foil 3100 through copper on the hole walls of the second via holes.

In the embodiment, the first copper foil 1200 and the second copper foil 1300 on two sides of the wiring area 1100 are respectively provided with the first via holes and the second via holes, and are connected with the third copper foil 3100 of the interlayer 3000 through the first via holes and the second via holes, and noise generated by peripheral electronic components on the printed circuit board can be coupled to the third copper foil 3100 of the interlayer 3000, so that the isolation between the sensitive signal line 1110 and the peripheral electronic components is increased, the influence of the peripheral electronic components on the sensitive signal line 1110 in the wiring area 1100 is reduced, and the normal use of the printed circuit board is favorably guaranteed.

In this embodiment, the plurality of first vias includes a plurality of first laser holes 1210 and a plurality of first through holes 1220, and the plurality of second vias includes a plurality of second laser holes 1310 and a plurality of second through holes 1320.

Specifically, a first via 1220 and a second via 1320 penetrate the printed circuit board, and the bottom layer 2000, each of the intermediate layers 3000, and the top layer 1000 are electrically connected to the second via 1320 through the first via 1220. Specifically, the trace area 1100, the first copper foil 1200 and the second copper foil 1300 are all located on the top layer 1000, the third copper foil 3100 is disposed on the middle layer 3000, and the fourth copper foil is disposed on the bottom layer 2000. The first via 1220 is opened in the first copper foil 1200, and the first copper foil 1200, the third copper foil 3100, and the fourth copper foil are electrically connected by copper on the hole wall of the first via 1220. The second via 1320 is opened in the second copper foil 1300, and the second copper foil 1300, the third copper foil 3100, and the fourth copper foil are electrically connected through copper on the wall of the second via 1320.

The first laser hole 1210 extends from the first copper foil 1200 to the third copper foil 3100, a first copper pillar is arranged in the first laser hole 1210, and the first copper foil 1200 and the third copper foil 3100 are electrically connected through the first copper pillar.

The second laser hole 1310 extends from the second copper foil 1300 to the third copper foil 3100, a second copper pillar is arranged in the second laser hole 1310, and the second copper foil 1300 and the third copper foil 3100 are electrically connected through the second copper pillar.

In a possible implementation manner, in this embodiment, the arrangement direction of the plurality of first vias 1220 is the same as the routing direction of the sensitive signal line 1110, and one or more first laser holes 1210 are disposed between two adjacent first vias 1220. The arrangement direction of the second through holes 1320 is the same as the routing direction of the sensitive signal line 1110, and one or more second laser holes 1310 are disposed between two adjacent second through holes 1320.

Through the arrangement, the laser hole can be used for filling the gap between the two through holes, so that noise generated by peripheral electronic components on the printed circuit board can be guided and transmitted to the third layer of copper foil by the laser hole when passing through the two through holes, and the influence of the noise on the sensitive signal line 1110 is reduced.

Further, at least one first laser hole 1210 is arranged between two adjacent first through holes 1220; and/or at least one second laser hole 1310 is disposed between two adjacent second through holes 1320.

Further, at least two first laser holes 1210 are disposed between two adjacent first through holes 1220, and an arrangement direction of the at least two first laser holes 1210 is perpendicular to a routing direction of the sensitive signal line 1110. At least two second laser holes 1310 are arranged between two adjacent second through holes 1320, and the arrangement direction of the at least two second laser holes 1310 is perpendicular to the routing direction of the sensitive signal line 1110.

Optionally, in this embodiment, two adjacent first laser holes 1210 are tangent, or the distance between two adjacent first laser holes 1210 is less than or equal to 1.5mm.

Adjacent two second laser holes 1310 are tangent, or the distance between adjacent two second laser holes 1310 is less than or equal to 1.5mm.

The adjacent first laser holes 1210 are tangent to the first through holes 1220, or the distance between the adjacent first laser holes 1210 and the first through holes 1220 is less than or equal to 1.5mm.

The adjacent second laser holes 1310 and the second through holes 1320 are tangent, or the distance between the adjacent second laser holes 1310 and the second through holes 1320 is less than or equal to 1.5mm.

In a possible implementation manner, an arrangement direction of the plurality of first vias 1220 of the present embodiment is the same as a routing direction of the sensitive signal line 1110, and one or more first laser holes 1210 are disposed between two adjacent first vias 1220;

and/or the arrangement direction of the plurality of second through holes 1320 is the same as the routing direction of the sensitive signal line 1210, the second through holes 1320 are arranged close to the edge of the printed circuit board, the second copper foil 1300 is also connected with a ground wire, and the ground wire is the same as the routing direction of the sensitive signal line 1210;

and/or one or more second laser holes 1310 are arranged between two adjacent second through holes 1320, the arrangement direction of the second laser holes 1310 is the same as the routing direction of the sensitive signal line 1210, the second through holes 1320 are arranged close to the board edge of the printed circuit board, the second copper foil 1300 is further connected with a ground wire, and the routing direction of the ground wire is the same as the routing direction of the sensitive signal line 1210.

In a possible implementation manner, a plurality of sensitive signal lines 1110 are disposed in the trace area 1100 of this embodiment, two adjacent sensitive signal lines 1110 are disposed at intervals, the sensitive signal line 1110 near one side of the first copper foil 1200 is disposed at an interval with the first copper foil 1200, and the sensitive signal line 1110 near one side of the second copper foil 1300 is disposed at an interval with the second copper foil 1300.

In one possible implementation, the printed circuit board of the present embodiment further includes at least one first line 1410 and/or a first trace 1420;

the first wire 1410 and/or the first trace 1420 are located on a side of the first copper foil 1200 facing away from the trace area 1100; and/or the first wire 1410 and/or the first trace 1420 are located on a side of the second copper foil 1300 facing away from the trace area 1100;

the first line 1410 includes one or more of a power pad, a signal via, and a power via; the first traces 1420 include one or more of power traces, signal traces.

In one possible implementation, the trace area 1100 of the present embodiment is disposed on at least one of the top layer 1000, the bottom layer 2000 and each middle layer 3000, and a second trace and a second line are further disposed on at least one of the top layer 1000, the bottom layer 2000 and each middle layer 3000, and the second trace and the second line are located within a projection range of the first copper foil 1200, the trace area 1100 and the second copper foil 1300.

In a possible implementation manner, the trace area 1100 of the present embodiment is disposed on the top layer 1000, at least one of the middle layers 3000 is further provided with a second trace and a second circuit, the bottom layer 2000 is provided with an electronic component, and the second trace, the second circuit, and the electronic component are located within a projection range of the first copper foil 1200, the trace area 1100, and the second copper foil 1300.

The embodiments of the present application will be described in detail with reference to specific examples.

FIG. 3 is a simplified top view of a top layer of a printed circuit board according to one embodiment of the present application; fig. 4 is a cross-sectional view of the printed circuit board of fig. 3 in one embodiment. Wherein, fig. 4 is a cross-sectional view along laser hole 206, through hole 205, laser hole 201, through hole 202, laser hole 211, laser hole 200 in fig. 3; the TOP layer is shown as the TOP layer; the BOTTOM layer is shown as the BOTTOM layer; the intermediate layer is provided with four layers, shown as L02, L03, L04, and L05 layers, respectively. In the figure, the sensitive signal lines 40 may be radio frequency lines (e.g., wifi radio frequency lines, LTE radio frequency lines, GPS radio frequency lines, etc.), fetal heart sampling signal lines (signal swing is only μ V level), microphone sampling signal lines, etc., or sensitive MIPI signal lines, differential signal lines, e.g., 25GB/s differential signal lines, whose swing is only 30mV, which are very easily interfered by surrounding power supply lines or via holes, clock signal lines or via holes, etc. Both laser vias and vias are shown to include PAD (PAD) and via holes, wherein the via holes are first drilled in the PCB and then plated in the walls of the via holes, the plated portions in the walls of the via holes forming the PAD, the via holes 203 are formed in the via holes 202, and the via holes 204 are formed in the via holes 205. The laser hole is drilled by laser processing, and meanwhile, the drilled hole is also electroplated and filled, so that the laser hole can be considered as a solid copper column.

Referring to fig. 3, a sensitive signal line 40 (e.g., an rf trace, a microphone sampling signal trace, etc.) is disposed in a local area of a TOP layer of the printed circuit board 310, a ground copper foil 207 (i.e., a first copper foil) of the TOP layer is disposed on the left side of the sensitive signal line 40, and a gap 51 (i.e., a copper-free area) is disposed between the ground copper foil 207 and the sensitive signal line 40. The ground copper foil 207 is provided with a laser hole 30, a laser hole 206, a through hole 205, a laser hole 201, a laser hole 32, a through hole 202, a laser hole 211, a laser hole 31, a laser hole 200 and a laser hole 33 from top to bottom. The laser holes 30 and the laser holes 206 are arranged in parallel in the horizontal direction, and the edge of the hole plate of the laser hole 30 is tangent to the edge of the hole plate of the laser hole 206; the laser holes 32 and the laser holes 201 are arranged in parallel in the horizontal direction, and the edge of the hole plate of the laser holes 32 is tangent to the edge of the hole plate of the laser holes 201; the laser holes 31 and the laser holes 211 are arranged in parallel in the horizontal direction, and the edge of the hole plate of the laser hole 31 is tangent to the edge of the hole plate of the laser hole 211; the laser holes 33 and 200 are arranged side by side in the horizontal direction, and the hole disc edge of the laser hole 33 is tangent to the hole disc edge of the laser hole 200.

A TOP layer of ground copper foil 52 (i.e., a second copper foil) is disposed to the right of the sensitive signal line 40, and a gap 50 (i.e., a copper-free region) is disposed between the ground copper foil 52 and the sensitive signal line 40. The ground copper foil 52 is provided with a laser hole 41, a laser hole 34, a through hole 35, a laser hole 36, a laser hole 58, a through hole 37, a laser hole 42, a laser hole 38, a laser hole 43, and a laser hole 39 from top to bottom. The laser holes 41 and the laser holes 34 are arranged in parallel in the horizontal direction, and the edge of the hole plate of the laser hole 41 is tangent to the edge of the hole plate of the laser hole 34; the laser holes 36 and the laser holes 58 are arranged in parallel in the horizontal direction, and the edge of the hole plate of the laser hole 36 is tangent to the edge of the hole plate of the laser hole 58; the laser holes 42 and the laser holes 38 are arranged in parallel in the horizontal direction, and the edge of the hole plate of the laser hole 42 is tangent to the edge of the hole plate of the laser hole 38; the laser holes 39 and the laser holes 43 are arranged side by side in the horizontal direction, and the distance between the hole plate edge of the laser hole 39 and the hole plate edge of the laser hole 43 is L23,0 ≦ L23<1.5mm, preferably L23=0, that is, the hole plate edge of the laser hole 39 and the hole plate edge of the laser hole 43 are tangent to each other, so that space is saved.

With continued reference to fig. 3 and 4, the TOP layer of copper foil 207 connects laser via 211, laser via 200, via 202, laser via 201, via 205, and laser via 206 at the TOP layer. The through

holes

202 and 202 connect the TOP layer earth copper foil 207, the L02 layer earth copper foil 208, the L03 layer earth copper foil 212, the L04 layer earth copper foil 213, the L05 layer earth copper foil 214 and the BOTTOM layer earth copper foil 210 into a low-impedance whole. In the present embodiment, the third copper foil includes a ground copper foil 208, a ground copper foil 212, a ground copper foil 213, and a ground copper foil 214. Generally, the ground copper foil 208 of the L02 layer is set as a complete ground plane, that is, only the ground copper foil 208 is set on the L02 layer, noise in the TOP layer ground copper foil 207, the L03 layer ground copper foil 212, the L04 layer ground copper foil 213, the L05 layer ground copper foil 214, and the BOTTOM layer ground copper foil 210 at the positions of the through

holes

202 and 202 will be absorbed and attenuated by the L02 layer ground copper foil 208, noise on the TOP layer ground copper foil 207, the L03 layer ground copper foil 212, the L04 layer ground copper foil 213, the L05 layer ground copper foil 214, and the BOTTOM layer ground copper foil 210 at the positions of the through

holes

202 and 202 will be greatly reduced, and EMI radiation index and radio frequency index of the stray product will be greatly reduced. Laser holes 211, 200, 201, 206 are provided from the TOP layer to the L02 layer, in the scheme shown in fig. 4, the laser hole 211, the laser hole 200, the laser hole 201 and the laser hole 206 tightly connect the TOP layer ground copper foil 207 and the L02 layer ground copper foil 208 together in the Z direction in the laminated structure of the printed circuit board 310, and the combination of the through hole 202 and the through hole 205 realizes the low-impedance connection between the TOP layer ground copper foil 207 and the L02 layer ground copper foil 208, this prevents the sensitive signal lines 40 (e.g., rf traces) from leaking towards the surrounding signal traces and vias (e.g., clock traces, not shown in fig. 4), power traces and vias (not shown in fig. 4), TOP layer pads (not shown in fig. 4), meanwhile, the holes avoid the interference of the leakage of pulsed electric field (radiation) generated by the laser holes 211, 200, 202, 201, 205, 206 (such as clock lines, not shown in fig. 4), power lines and vias (not shown in fig. 4), and TOP pads (not shown in fig. 4) to the sensitive signal lines 40 (such as rf lines), meanwhile, since the ground copper foil 207 of the TOP layer is in low-impedance connection with the ground copper foil 208 of the L02 layer, the peripheral signal traces and vias (such as clock traces, not shown in fig. 4), power traces and vias (not shown in fig. 4), and ground noise (absorbed by the ground copper foil 208 of the L02 layer) generated by the pads (not shown in fig. 4) of the TOP layer in the traces of the laser holes 211, 200, 202, 201, 205, 206 can be ignored for the sensitive signal lines 40 (such as rf traces).

In this embodiment, the edge distance between the laser holes 211 and 200 is L2. In order to avoid leakage interference of pulsed electric field radiation on the sensitive signal line 40 caused by signal traces and vias (such as clock traces, not shown in fig. 4), power traces and vias (not shown in fig. 4), and TOP pads (not shown in fig. 4) around the laser holes 211 and 200, an edge distance between the laser holes 211 and 200 is L2 ≦ 1.5mm, and preferably, an edge distance between the laser holes 211 and 200 is L2=0, that is, an edge of the aperture plate of the laser hole 211 is tangent to an edge of the aperture plate of the laser hole 200. The aperture disk edge of laser aperture 211 and the aperture disk edge of laser aperture 200 may be tangent, but may not overlap.

The aperture disk edge of the laser aperture 200 is tangent to the aperture disk edge of the through-hole 202. The edge of the hole plate of the laser hole 201 is tangent to the edge of the hole plate of the through hole 202 and the edge of the hole plate of the through hole 205 respectively.

The edge distance between the laser hole 206 and the through hole 205 is L1. In order to avoid leakage interference of pulsed electric field radiation on the sensitive signal line 40 caused by signal traces and vias (such as clock traces, not shown in fig. 4), power traces and vias (not shown in fig. 4), and TOP pads (not shown in fig. 4) around the laser aperture 206 and the through hole 205, an edge distance between the laser aperture 206 and the through hole 205 is L1 ≦ 1.5mm, and preferably, an edge distance between the laser aperture 211 and the laser aperture 200 is L2=0, that is, an aperture edge of the laser aperture 211 is tangent to an aperture edge of the laser aperture 200. The aperture disk edge of laser aperture 211 and the aperture disk edge of laser aperture 200 may be tangent, but may not overlap.

In this embodiment, the laser hole 211, the laser hole 200, the laser hole 201, and the laser hole 206 are processed from the TOP layer to the L02 layer of the printed circuit board 310 by a laser processing method, and because of being limited by the existing laser hole processing process, the thickness H1 of the insulating medium from the TOP layer to the L02 layer is less than or equal to 3 mils (0.075 mm), and the thickness H5 of the insulating medium from the BOTTOM layer to the L05 layer is less than or equal to 3 mils (0.075 mm). The thicknesses H1 and H5 of the TOP layer to L02 layer insulating medium and the BOTTOM layer to L05 layer insulating medium are symmetrically distributed.

With reference to fig. 4 and 3, the through

holes

202 and 205 are added around the sensitive signal line 40, so that the through

holes

202 and 205 can connect the TOP layer of ground copper foil 207, the L02 layer of ground copper foil 208, the L03 layer of ground copper foil 212, the L04 layer of ground copper foil 213, the L05 layer of ground copper foil 214, and the BOTTOM layer of ground copper foil 210 with low impedance, thereby reducing the voltage difference between the ground copper foils and improving the board level EMI performance.

Fig. 5 is a cross-sectional view of the printed circuit board of fig. 3 in another embodiment. The cutting direction of fig. 5 is the same as that of fig. 4.

The difference in the solution of fig. 5 compared to the solution of fig. 4 is that the laser hole 206 in the TOP-L02 layer of fig. 4 is changed to the laser hole 220 in the TOP-L02-L03 layer, i.e. the laser hole 220 penetrates from the TOP layer to the L02 layer, L03 layer, connecting the copper foil 207 of the TOP layer with the copper foil 208 of the L02 layer, 212 of the L03 layer with low impedance. The thickness H2 of the L02 layer to the L03 layer of the insulating medium is less than or equal to 3mil (0.075 mm), the thickness H4 of the L05 layer to the L04 layer of the insulating medium is less than or equal to 3mil (0.075 mm), and the thicknesses H1 and H5 of the L02 layer to the L03 layer of the insulating medium and the L05 layer to the L04 layer of the insulating medium are symmetrically distributed.

Except for the above differences, the other parts in the scheme of fig. 5 are the same as those in fig. 4, and the description is not repeated.

Fig. 6 is a cross-sectional view of the printed circuit board of fig. 3 in yet another embodiment. The cutting direction of fig. 6 is the same as that of fig. 4.

The difference in the scheme of fig. 6 compared with the scheme of fig. 5 is that the laser hole 220 in the TOP-L02-L03 layer of fig. 5 is changed into the laser hole 221 in the TOP-L02-L03-L04 layer, that is, the laser hole 221 penetrates from the TOP layer to the L02, L03, and L04 layers, and the copper foil 207 of the TOP layer is connected with the copper foil 208 of the L02 layer, the copper foil 212 of the L03 layer, and the copper foil 213 of the L04 layer in a low impedance manner. The thickness H2 of the insulating medium from the L03 layer to the L04 layer is less than or equal to 3mil (0.075 mm).

Except for the above differences, the other parts in the scheme of fig. 6 are the same as those in fig. 5, and the description is not repeated.

Fig. 7 is a cross-sectional view of the printed circuit board of fig. 3 in yet another embodiment. The cutting direction of fig. 7 is the same as that of fig. 4.

Compared with the solution of fig. 6, the difference of the solution of fig. 7 is that the laser hole 221 in the TOP-L02-L03-L04 layer of fig. 6 is changed into the laser hole 222 in the TOP-L02-L03-L04-L05 layer, i.e. the laser hole 222 penetrates from the TOP layer to the L02, L03, L04, and L05 layers, and the copper foil 207 of the TOP layer is connected with the copper foil 208 of the L02 layer, the copper foil 212 of the L03 layer, the copper foil 213 of the L04 layer, and the copper foil 214 of the L05 layer in a low impedance manner.

Except for the above differences, the other parts in the scheme of fig. 7 are the same as those in fig. 6, and the description is not repeated.

Fig. 8 is a cross-sectional view of the printed circuit board of fig. 3 in yet another embodiment.

Compared with the scheme of fig. 4, the scheme of fig. 8 is different in that the TOP layer laser hole 211 is provided with a laser hole 270, a laser hole 271, a laser hole 272, a laser hole 273, a laser hole 274, a laser hole 275, a laser hole 276, a laser hole 277, a laser hole 278, a through hole 295, a laser hole 268, a laser hole 262 and a through hole 267 in sequence in the Z direction. The laser hole 206, the laser hole 201, the laser hole 200, the laser hole 211, the laser hole 270, the laser hole 271, the laser hole 272, the laser hole 273, the laser hole 274, the laser hole 275, the laser hole 276, the laser hole 277, the laser hole 278, the laser hole 268 and the laser hole 262 realize low-impedance connection from the TOP layer copper foil 207 to the L02 layer copper foil 208. The projection of the sensitive signal line 40 of the TOP layer completely falls in the copper foil 208 of the L02 layer, and the copper foil 208 of the L02 layer completely covers the projection of the sensitive signal line 40 of the TOP layer on the L02 layer, i.e. the sensitive signal line 40 of the TOP layer has a complete reference plane, i.e. the copper foil 208, on the adjacent L02 layer. The TOP layer ground copper foil 207, the L02 layer ground copper foil 208, the L03 layer ground copper foil 212, the L04 layer ground copper foil 213, the L05 layer ground copper foil 214, and the BOTTOM layer ground copper foil 210 are connected by the through

holes

202 and 205 with low impedance. The

vias

295 and 267 connect the TOP layer ground copper foil 207, the L02 layer ground copper foil 208, the L03 layer ground copper foil 252, the L04 layer ground copper foil 253, the L05 layer ground copper foil 254 and the BOTTOM layer ground copper foil 255 with low impedance.

A BGA (Ball Grid Array) device 297 is arranged between a through hole 202 and a through hole 256 of a BOTTOM layer of the printed circuit board 310, and a welding pad 90, a welding pad 91, a welding pad 92, a welding pad 93, a welding pad 94, a welding pad 95 and a welding pad 96 are respectively arranged at the pin position of the body of the BGA device 297; arranging a laser hole 80 of an L05-BOTTOM layer on the bonding pad 90 to be connected with the signal routing line 70 of the L05 layer; arranging a laser hole 81 of an L05-BOTTOM layer on the bonding pad 91 to be connected with the signal routing 71 of the L05 layer; arranging a laser hole 82 of the L05-BOTTOM layer on the bonding pad 92 to be connected with the signal routing 72 of the L05 layer; the bonding pad 93 is provided with a laser hole 83 of an L05-BOTTOM layer and is connected with the signal wiring 73 of the L05 layer; arranging the laser hole 84 of the L05-BOTTOM layer on the bonding pad 94 to be connected with the signal routing 74 of the L05 layer; the laser hole 85 of the L05-BOTTOM layer is disposed on the pad 95 to be connected to the signal trace 75 of the L05 layer.

Arranging a signal routing 285, a signal routing 286, a signal routing 287 and a signal routing 288 on the L04 layer; the L03 layer is provided with a signal trace 280, a signal trace 281, a signal trace 282, and a signal trace 283. That is, between the through hole 202 and the through hole 256, various signal traces are disposed in the areas of the layer L03, the layer L04, and the layer L05 where the TOP layer sensitive signal line 40 is projected, and BGA devices (only BGA devices are exemplified and device types are not limited) are disposed in the areas of the layer BOTTOM where the TOP layer sensitive signal line 40 is projected, so that through holes connected to the TOP layer ground copper foil 207 and the layer L02 ground copper foil 208 cannot be disposed in the areas between the through hole 202 and the through hole 256, but laser holes 200, 211, 270, 271, 272, 273, 274, 275, 276, 277, 278 are disposed in the areas between the through hole 202 and the through hole 256, and power and clock traces are disposed in the TOP layer around the TOP layer sensitive signal line 40, and do not interfere with the sensitive signal line 40, and meet design requirements. Between the through hole 202 and the through

hole

256, 1 to 20 rows of laser holes may be disposed.

Except for the above differences, the other parts in the scheme of fig. 8 are the same as those in fig. 4, and the description is not repeated.

Fig. 9 is a simplified top view diagram of a top layer of a printed circuit board according to another embodiment of the present application.

Compared with the scheme of fig. 3, the scheme of fig. 9 is different in that the aperture disk edge of the laser aperture 43 and the aperture disk edge of the laser aperture 39 are not tangent, and the distance between the aperture disk edge of the laser aperture 43 and the aperture disk edge of the laser aperture 39 is L23, wherein 0< -L23 > is less than or equal to 1.5mm.

The sensitive signal line 53 and the sensitive signal line 54 are arranged between the ground copper foil 52 and the ground copper foil 207, and the sensitive signal line 53 and the sensitive signal line 54 form a sensitive differential trace (for example, the swing of a 25GB/S differential trace signal is only 30mV, and is very easily interfered by an electric field generated by a signal trace and a power trace around the same layer). A gap 57 (copper foil free region) is provided between the sensitive signal line 53 and the sensitive signal line 54, and a gap 55 (copper foil free region) is provided between the sensitive signal line 53 and the ground copper foil 207; a gap 56 (no copper foil area) is provided between the sensitive signal line 54 and the ground copper foil 52. The line widths,

gaps

57, 55, 56, and thicknesses of the TOP to L02 layer insulating layers of the

sensitive signal lines

53 and 54 are set to meet the impedance control requirements (e.g., 100 ohms) of the differential traces.

Except for the above differences, the other parts in the scheme of fig. 9 are the same as those in fig. 3, and the description is not repeated.

Fig. 10 is a simplified top view schematic diagram of a top layer of a printed circuit board according to yet another embodiment of the present application.

Compared with the solution of fig. 3, the difference of the solution of fig. 10 is that a signal trace 60 (e.g., a clock trace, etc.) is disposed on the right side of the TOP layer copper foil 52, the signal trace 60 is connected to a signal via 803 (the signal via includes a signal via and a signal laser via, which are only exemplified by the signal via 803 and are not limited to the type of the signal via), the signal via 803 is disposed on the right side of the via 37, and a power via 804 (the power via includes a power via and a power laser via, which are only exemplified by the power via 804 and are not limited to the type of the power via) is disposed below the signal via 803 and on the right side of the laser via 39. A gap 63 (i.e., a copper-free region) is provided between the ground copper foil 52 and the signal trace 60, the width of the gap 63 is L31, L31 ≧ 2mil (preferably L31 ≧ 3 mil), and consideration is given to the processing capability of etching by the PCB manufacturer. The gap (i.e., the copper-free region) between the power via 804 and the copper foil 52 of the TOP layer is L34, L34 ≧ 2mil (preferably L34 ≧ 3 mil). The gap between the signal via 803 and the TOP layer copper foil 52 is L32, L32 ≧ 2mil (preferably L32 ≧ 3 mil).

The power trace 61 is provided on the right side of the TOP layer ground copper foil 207, the gap 62 (i.e., the copper-free region) is provided between the ground copper foil 207 and the power trace 61, the width of the gap 62 is L30, L30 ≧ 2mil (preferably L30 ≧ 3 mil), and the etching processability of the PCB manufacturer is mainly considered. The power trace 61 is connected to the power pad 811, the power pin (not shown in fig. 10) of the component 801 is soldered to the power pad 811, and the gap between the power pad 811 and the TOP layer copper foil 207 is L33, which is ≧ 2mil (preferably L33 ≧ 3 mil). The signal pin (not shown in fig. 10) of the component 801 is soldered to the signal pad 802, and the gap between the signal pad 802 and the copper foil 207 on the TOP layer is L35, and L35 ≧ 2mil (preferably L35 ≧ 3 mil).

The sensitive signal line 40 (e.g., rf trace, differential trace, etc.) is disposed on the left side of the TOP layer ground copper foil 52, and a gap 51 is disposed between the ground copper foil 52 and the sensitive signal line 40, wherein the width of the gap 51 is L32. A gap 50 is provided between the copper foil 52 and the sensitive signal line 40, the width of the gap 50 being L33. Preferably L32= L33. When the sensitive signal line 40 has an impedance control requirement, the line width of the sensitive signal line 40, the gap 51, the gap 50, and the thicknesses of the TOP layer to the L02 layer insulating layer are required to satisfy the impedance control of the sensitive signal line 40 (e.g., the rf trace requires 50 ohms). The sensitive signal line 40 transmits a microphone signal that is low frequency and impedance control need not be considered.

The first trace in the solution of fig. 10 includes power pads 811 and signal pads 802 of the component 801 on the left side of the ground copper foil 200, and the first trace includes the power trace 61.

Fig. 11 is a simplified top view diagram of a top layer of a printed circuit board according to yet another embodiment of the present application.

Compared with fig. 10, fig. 11 shows that the signal traces 60 (e.g., clock traces, etc.), the signal vias 803 (signal vias include signal vias and signal laser vias, which are only exemplified by the signal vias 803 without limitation of the types of the signal vias), the power vias 804 (power vias include power vias and power laser vias, which are only exemplified by the power vias 804 without limitation of the types of the power vias) and the signal vias 60 in fig. 10 are removed, instead of the board edges 333 of the PCB 310, that is, the ground copper foils 207 and 52 are disposed in a narrow space between the power traces 61, the power pads 811 and 802 of the component 801 and the board edges 333 of the PCB 310, the sensitive signal lines 40 are disposed between the ground copper foils 207 and 52, the gaps 51 (i.e., no-copper areas) are disposed between the sensitive signal lines 40 and the ground copper foils 207, the gaps 50 (i.e., no-copper areas) are disposed between the sensitive signal lines 40 and the ground copper foils 52, and the gaps 68 (i.e., no-copper areas) are disposed between the ground copper foils 52 and the gaps 68 between the PCB 52 and the PCB 310, and the gaps 68 are preferably maintained at a width of 0.0.50 mm, or more than 0.0.50 mm, and 0 mm of the PCB 310, and the PCB is removed by a milling cutter used. Fig. 11 shows a situation that the routing area of the sensitive signal 40 is close to the right edge 333 of the PCB 310, and the first line and the first trace are not distributed on the right edge 331 of the PCB 310, that is, the first line and the first trace are distributed on the left side of the routing area of the sensitive signal 40.

The first line in the solution of fig. 11 includes a power pad 811 and a signal pad 802 of the element 801 on the left side of the ground copper foil 200, etc., a signal via 803 on the right side of the ground copper foil 52 (the signal via includes a signal via and a signal laser via, exemplified only by the signal via 803 without limitation of the type of the signal via), a power via 804 (the power via includes a power via and a power laser via, exemplified only by the power via 804 without limitation of the type of the power via), etc. The first traces include signal traces 60 (e.g., clock traces, etc.), power traces 61.

Except for the above differences, the other parts in the scheme of fig. 11 are the same as those in fig. 10, and the description is not repeated.

Fig. 12 is a simplified top view schematic diagram of a top layer of a printed circuit board according to another embodiment of the present application.

In comparison with fig. 11, fig. 12 removes laser via 34 between laser via 41 and board edge 333, via 35, laser via 36 between laser via 58 and board edge 333, via 37, laser via 38 between laser via 42 and board edge 333, and laser via 39 between laser via 43 and board edge 333 in fig. 11, while a plurality of single row laser vias are provided in copper foil 52 between sensitive signal line 40 and board edge 333: the laser via 41, the laser via 366, the laser via 58, the laser via 388, the laser via 42, the laser via 43, that is, the ground copper foil 52 is electrically connected to the laser via 41, the laser via 366, the laser via 58, the laser via 388, the laser via 42, the laser via 43. The laser holes 41, 366, 58, 388, 42, 43 are arranged in parallel with the sensitive signal lines 40 in the vertical direction. Due to the limited space of the PCB 310, no vias can be added between the sensitive signal lines 40 and the board edges 333. The gap 68 (i.e., the copper-free area) between the ground copper foil 52 and the plate edge 333 of the PCB 310 has a width L50 ≧ 0.15mm (preferably L50 ≧ 0.2 mm), and the gap 68 is used to maintain a safe distance between the ground copper foil 52 and the plate edge of the PCB 310, so as to prevent a milling cutter from scratching the ground copper foil 52 when a PCB manufacturer processes the plate edge 333 of the PCB 310, which results in an oxidation problem of the exposed ground copper foil 52. A gap 50 is arranged between the sensitive signal line 40 and the ground copper foil 52, and the width of the gap is L33. Except for the above differences, the other parts in the scheme of fig. 12 are the same as those in fig. 11, and the description is not repeated.

The application scenario shown in fig. 12 mainly occurs in a small PCB board size, and a very high density vehicle-mounted tracker (belonging to a vehicle-mounted wireless device), a vehicle-mounted recorder (belonging to a vehicle-mounted wireless device), etc., that is, a sensitive signal line 40 (e.g., a radio frequency trace) is disposed near a board edge 333, various lines and components (e.g., a power trace 61, a component 801, a power pad 811 of the component 801, and a signal pad 802 in fig. 13) are disposed on the right side of the sensitive signal line 40, a ground copper foil 207 is disposed between the various lines and components and the sensitive signal line 40, and a laser hole 206, a laser hole 30, a pass-through 205, a laser hole 201, a laser hole 32, a through hole 202, a laser hole 211, a laser hole 31, a laser hole 200, a laser hole 207, etc. are disposed in the ground copper foil 207.

Fig. 13 is a simplified top view schematic diagram of a top layer of a printed circuit board according to another embodiment of the present application. FIG. 14 is a partial cross-sectional view of a printed circuit board according to an embodiment of the present invention between the top layer and the layer 2;

FIG. 15 is a partial cross-sectional view of a printed circuit board according to yet another embodiment of the present application, taken between the top layer and layer 2; FIG. 16 is a partial cross-sectional view of a printed circuit board according to another embodiment of the present application, taken between the top layer and layer 2; fig. 17 is a partial cross-sectional view of a printed circuit board between the top layer and the 2 nd layer according to another embodiment of the present application.

In comparison with fig. 12, fig. 13 has laser holes 41, 366 removed from fig. 12, the board edge 333 in fig. 12 is a regular straight line, and the vertical direction in fig. 13 is from bottom to top: the laser holes 43, the laser holes 42, the laser holes 388, the laser holes 58 are distributed at the same positions, and the shape of the board edge 334 is the same as that of fig. 12, but the board edge 334 is retracted towards the left at the laser holes 58, that is, the notch 330 is cut, various circuits and elements (for example, the power trace 61, the element 801, the power pad 811 of the element 801, and the signal pad 802 in fig. 12) are arranged at the left side of the sensitive signal line 40, and no space is shifted to the left, so that through holes and laser holes cannot be arranged at the notch 330, only the ground wire 99 is added at the position of the board edge 334 between the sensitive signal line 40 and the notch 330, and the design basically meets the design requirements of the sensitive signal line 40 (for example, a radio frequency trace, a microphone sampling signal, and the like) because the board edge 334 between the sensitive signal line 40 and the notch 330 does not have an interference source.

Because the PCB board 310 is limited in space, the left side of the sensitive signal line 40 cannot be added with a through hole, and the vertical direction is from the bottom to the top: laser holes 43 to 58 are distributed, only a single row of laser holes can be added: laser aperture 43, laser aperture 42, laser aperture 388, laser aperture 58.

A gap 50 is arranged between the sensitive signal line 40 and the ground copper foil 52 and the ground line 99, and the width of the gap is L33. A gap 50 is provided between the sensitive signal line 40 and the sensitive signal line, and the gap width is L33.

The gap 689 (i.e., the copper-free area) between the ground copper foil 52 and the board edge 334 of the PCB 310 is larger than or equal to 0.15mm (preferably, larger than or equal to 0.2 mm) in width L50 of the gap 689, and the gap 689 is used for maintaining a safe distance between the ground copper foil 52 and the board edge of the PCB 310, so as to prevent a milling cutter from scratching the ground copper foil 52 and exposing the ground copper foil 52 to an oxidation problem when the PCB manufacturer processes the board edge 334 of the PCB 310.

A gap 688 (i.e., a copper-free area) between the ground wire 99 and the board edge 334 of the PCB 310 is formed, a width L50 of the gap 688 is not less than 0.15mm (preferably, the width L50 is not less than 0.2 mm), and the gap 688 is used for maintaining a safe distance between the ground wire 99 and the board edge of the PCB 310, so that the ground copper foil 52 is prevented from being scratched by a milling cutter when the board edge 334 of the PCB 310 is machined by a PCB manufacturer, and the ground copper foil 52 is prevented from being exposed and oxidized. Except for the above differences, the other parts in the scheme of fig. 13 are the same as those in fig. 11, and the description is not repeated.

The application scenario shown in fig. 13 mainly occurs in a small-sized PCB, a very high-density vehicle-mounted tracker (belonging to a vehicle-mounted wireless device), a vehicle event data recorder (belonging to a vehicle-mounted wireless device), and the like.

FIG. 14 is a partial cross-sectional view of the TOP layer and the L02 layer (layer 2) of FIG. 13 taken along the A1 position in the vertical direction, horizontally to the laser hole 206, laser hole 30; fig. 15 is a partial cross-sectional view of the TOP layer and the L02 layer (layer 2) in fig. 13 in the vertical direction along the A2 position in the horizontal direction of the via 205;

fig. 16 is a partial cross-sectional view of the TOP layer and the L02 layer (layer 2) in fig. 13 in the vertical direction along the A3 position in the horizontal direction of the via 202 and the laser via 388; fig. 17 is a partial sectional view of the TOP layer and the L02 layer (layer 2) in fig. 13 in the vertical direction along the A4 position in the horizontal direction of the laser hole 211, the laser hole 31, and the laser hole 42. The ground copper foil 208 of the L02 layer in fig. 13 to 17 is electrically connected to the ground copper foil 207 of the TOP layer through the laser via 206, the laser via 30, the via 205, the laser via 201, the laser via 32, the via 202, the laser via 200, and the laser via 33, and the ground copper foil 208 is electrically connected to the ground copper foil 52 of the TOP layer through the laser via 43, the laser via 42, the laser via 388, and the laser via 58.

Compared with fig. 10, fig. 18 shows that the power traces 61, the components 801, the power pads 811 and the signal pads 802 of the components 801 in fig. 10 are removed, and the power traces 60 (e.g., clock traces, etc.), the signal vias 803 (including signal vias and signal laser vias, exemplified only by signal vias 803, without limitation on the types of signal vias), the power vias 804 (including power vias and power laser vias, exemplified only by power vias 804, without limitation on the types of power vias) and the board edge 333 of the PCB 310 are replaced by the board edge 331 of the PCB 310, the ground copper foils 207 and 52 are disposed in a narrow space, the sensitive signal line 40 is disposed between the ground copper foils 207 and 52, the gap 51 (i.e., a copper-free area) is disposed between the sensitive signal line 40 and the ground copper foil 207, the gap 50 (i.e., a copper-free area) is disposed between the sensitive signal line 40 and the ground copper foils 52, the gap 69 (i.e., a copper-free area) is disposed between the sensitive signal line 40 and the ground copper foils 52, and the board edge 331 of the PCB 310, and the PCB 310 has a gap 69 (i.e., a gap 69 is greater than or equal to 0.0 mm), and the PCB 310 is not damaged, and the PCB 310 is removed, and the gap is used for maintaining the gap 207 is preferably equal to maintain the gap 207, and equal to 0 mm.

Fig. 18 shows a situation where the routing area of the sensitive signal 40 is close to the left board edge 331 of the PCB 310, that is, a situation where the first line and the first trace are distributed on the right side of the routing area of the sensitive signal 40. While the left board edge 331 of the PCB 310 does not have the first trace and the first trace distributed.

The first trace in the solution of fig. 18 includes signal vias 803 on the right side of the ground copper foil 52 (signal vias include signal vias and signal laser vias, exemplified only by signal vias 803 without limitation of the type of signal vias), power vias 804 (power vias include power vias and power laser vias, exemplified only by power vias 804 without limitation of the type of power vias), and the like. The first traces include signal traces 60 (e.g., clock traces, etc.).

Except for the above differences, the other parts in the scheme of fig. 18 are the same as those in fig. 10, and the description is not repeated.

It should be noted that, in order to prove the design rationality and practicability of the radio frequency signal (sensitive signal) structure in the printed circuit board provided in the foregoing embodiment of the present invention, the sensitive signal (radio frequency signal) structure in fig. 18 is applied to the automobile data recorder in cooperation with the WiFi antenna, and taking the automobile data recorder as an example, the following is a process of WiFi active test analysis of the automobile data recorder:

the experimental environment comprises an OTA darkroom and a network analyzer. Table 1 gives S11 active test data for WiFi antennas in the tachograph: the S11 value of the WiFi antenna is-10.329dB under a 2412MHz frequency band, the S11 value of the WiFi antenna is-10.387dB under a 2442MHz frequency band, the S11 value of the WiFi antenna is-11.003dB under a 2484MHz frequency band, and the S11 values of the WiFi antenna in the 2412MHz, 2442MHz and 2484MHz frequency bands are all less than-10 dB, so that the requirement of a driving recorder (a broadband product) on the S11 parameter of the WiFi antenna is met. Namely, within the bandwidth range of 100MHz working at 2.4 GHz-2.5 GHz, the VSWR is less than 2, the requirement of a driving recorder (belonging to a broadband product) for transmitting high-throughput data by 2.4G Wi-Fi on the bandwidth is completely met, and the design of a radio frequency signal (sensitive signal) structure in the printed circuit board provided by the embodiment of the invention is proved to be reasonable and scientific.

TABLE 1S 11 test data for WiFi antennas

Channel with a plurality of channels	Specification of test requirements	Test data	Whether or not to meet the requirements
				2412	<-10dB	-10.465dB	Satisfy the requirement of
2442	<-10dB	-10.493dB	Satisfy the requirement of
				2484	<-10dB	-11.015dB	Satisfy the requirement of

In addition, the design rationality and the practicability of the radio frequency signal (radio frequency signal) structure in the printed circuit board provided by the embodiment of the present invention are that the sensitive signal (radio frequency signal) structure in fig. 11 is applied to a vehicle-mounted tracker (belonging to a wireless vehicle-mounted device) in cooperation with an LTE antenna, and taking the vehicle-mounted tracker as an example, the following is a process of active test analysis for transmission and reception of 5 bands of the vehicle-mounted tracker:

the experimental environment comprises an OTA darkroom and a network analyzer. Table 2 shows the active test data table of the LTE antenna for transmitting and receiving in 4 bands of the whole machine. As can be seen from Table 2, the transmission test selects 5 LTE bands including LTE Band 38, LTE Band 39, LTE Band 40, LTE Band 41 and LTE Band 34, wherein when the LTE Band 38 selects a 38150 channel, the working frequency is 2610MHz, and the transmission power in TRP mode is 20.53dBm; when the LTE Band 38 selects 38150 channel, the working frequency is 2610MHz, and the receiving sensitivity is-95.86 dBm in the TIS mode. When 3855 channels are selected by the LTE Band 39, the working frequency is 1910MHz, and the transmitting power in the TRP mode is 19.88dBm; when the LTE Band 39 selects a 3855 channel, the working frequency is 1910MHz, and the transmitting power in a TIS mode is-92.27 dBm; when the LTE Band 40 selects a 39550 channel, the working frequency is 2390MHz, and the transmitting power in the TRP mode is 20.89dBm; when the LTE Band 40 selects a 39550 channel, the working frequency is 2390MHz, and the receiving sensitivity is-95.97 dBm in a TIS mode. When the LTE Band 41 selects a 41490 channel, the working frequency is 2680MHz, and the transmitting power in the TRP mode is 20.23dBm; when the LTE Band 41 selects a 41490 channel, the working frequency is 2680MHz, and the receiving sensitivity is-95.9 dBm in the TIS mode. When the LTE Band 34 selects a 36275 channel, the working frequency is 2017.5MHz, and the transmitting power in a TRP mode is 19.25dBm; when the LTE Band 34 selects a 36275 channel, the working frequency is 2017.5MHz, and the receiving sensitivity in a TIS mode is-93.26 dBm. The test data meets the design requirements of the vehicle-mounted tracker (belonging to wireless vehicle-mounted equipment) whether the receiving sensitivity is within the LTE allowable range in the TRP mode transmitting power or the TIS mode.

Table 2 active test data table for LTE antenna transmitting and receiving in 4 bands of the whole machine

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the present application.

In this application, unless expressly stated or limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, or integral parts; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as the case may be.

It should be noted that, in the description of the present application, the terms "first" and "second" are used merely for convenience in describing different components, and are not to be construed as indicating or implying a sequential relationship, relative importance, or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature.

The embodiments or implementation manners in the present application are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other.

In the description of the present application, reference to the description of the terms "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this application, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A printed circuit board, comprising:

and/or, a plurality of second via holes set in the second copper foil, the second via holes run through the second copper foil, and the second copper foil is connected with the third copper foil through the copper of the hole wall of the second via holes.

2. The printed circuit board of claim 1, wherein the first plurality of vias comprises a first plurality of laser vias and a first plurality of vias, and wherein the second plurality of vias comprises a second plurality of laser vias and a second plurality of vias.

3. The printed circuit board of claim 2, wherein the first and second vias extend through the printed circuit board, and wherein the bottom layer, each of the intermediate layers, and the top layer are electrically connected to the second via through the first via;

and/or, the second laser hole extends to the third copper foil from the second copper foil, a second copper column is arranged in the second laser hole, and the second copper foil and the third copper foil are electrically connected through the second copper column.

4. The printed circuit board according to claim 3, wherein the arrangement direction of a plurality of the first through holes is the same as the routing direction of the sensitive signal lines, and one or more first laser holes are disposed between two adjacent first through holes;

and/or the arrangement direction of the second through holes is the same as the routing direction of the sensitive signal line, and one or more second laser holes are arranged between every two adjacent second through holes.

5. The printed circuit board of claim 4, wherein at least one first laser hole is disposed between two adjacent first through holes;

and/or at least one second laser hole is arranged between two adjacent second through holes.

6. The printed circuit board according to claim 5, wherein at least two first laser holes are arranged between two adjacent first through holes; the arrangement direction of at least two first laser holes is vertical to the routing direction of the sensitive signal line;

and/or at least two second laser holes are arranged between two adjacent second through holes, and the arrangement direction of the at least two second laser holes is vertical to the routing direction of the sensitive signal line.

7. The printed circuit board of claim 6, wherein two adjacent first laser holes are tangent, or the edge distance between two adjacent first laser holes is less than or equal to 1.5mm;

the two adjacent second laser holes are tangent, or the edge distance between the two adjacent second laser holes is smaller than or equal to 1.5mm;

the adjacent first laser holes are tangent to the first through holes, or the edge distance between the adjacent first laser holes and the first through holes is smaller than or equal to 1.5mm;

the adjacent second laser holes are tangent to the second through holes, or the edge distance between the adjacent second laser holes and the second through holes is smaller than or equal to 1.5mm.

8. The printed circuit board according to claim 3, wherein the arrangement direction of a plurality of the first through holes is the same as the routing direction of the sensitive signal lines, and one or more first laser holes are disposed between two adjacent first through holes;

9. The printed circuit board according to any one of claims 1 to 8, wherein a plurality of the sensitive signal lines are disposed in the routing region, two adjacent sensitive signal lines are disposed at an interval, the sensitive signal line adjacent to one side of the first copper foil is disposed at an interval with the first copper foil, and the sensitive signal line adjacent to one side of the second copper foil is disposed at an interval with the second copper foil.

10. The printed circuit board of claim 9, further comprising at least one first line and/or first trace;

the first line and/or the first trace are/is positioned on one side, away from the trace area, of the first copper foil; and/or the first line and/or the first trace are/is positioned on one side of the second copper foil, which is deviated from the trace area;

the first circuit comprises one or more of a power supply pad, a signal via hole and a power supply via hole; the first wire comprises one or more of a power supply wire or a power supply copper foil and a signal wire.

11. The printed circuit board of claim 10, wherein the trace area is disposed on the top layer, at least one of the bottom layer and each of the middle layers is further disposed with a second trace and/or a second line, and the second trace and/or the second line is located within a projection range of the first copper foil, the trace area and the second copper foil;

12. The printed circuit board of claim 10, wherein the trace area is disposed on the top layer, at least one of the middle layers further has a second trace and a second circuit disposed thereon, and the bottom layer has an electronic component disposed thereon, wherein the second trace, the second circuit, and the electronic component are located within a projection range of the first copper foil, the trace area, and the second copper foil.