CN115987454A

CN115987454A - Demodulation decoding method, demodulation decoding device, storage medium and electronic equipment

Info

Publication number: CN115987454A
Application number: CN202211642674.2A
Authority: CN
Inventors: 庄永昌
Original assignee: China Telecom Corp Ltd
Current assignee: China Telecom Corp Ltd
Priority date: 2022-12-20
Filing date: 2022-12-20
Publication date: 2023-04-18

Abstract

The disclosure relates to a demodulation decoding method, a demodulation decoding device, a storage medium and an electronic device, and relates to the technical field of computers, wherein the method comprises the following steps: firstly, in response to receiving a modulation signal sent by a sending end through each modulation subchannel, demodulating the modulation signal to obtain a sequence to be decoded corresponding to the modulation signal, decoding a plurality of subsections to be decoded obtained by dividing the sequence to be decoded by using a plurality of subsections decoders respectively based on a first preset threshold value respectively set for each subsection to be decoded to obtain a plurality of decoding subsections respectively corresponding to the plurality of subsections to be decoded, determining a plurality of target decoding subsections according to the plurality of decoding subsections, and performing subsection conversion and subsection combination on the plurality of target decoding subsections to obtain a decoding bit sequence corresponding to the sequence to be decoded. Therefore, the multiple subsegment decoders are used for decoding the multiple subsegments to be decoded, which have mapping relation with the modulation sub-channels, so that the decoding time is shortened, and the spectral efficiency and the reliability of the system are improved.

Description

Demodulation decoding method, demodulation decoding device, storage medium and electronic equipment

Technical Field

The disclosed embodiment relates to the technical field of computers, in particular to a demodulation and decoding method, a demodulation and decoding device, a storage medium and electronic equipment.

Background

In one of the important directions of channel coding research in the sixth generation mobile communication standard (6 th generation mobile networks), channel coding and decoding and modulation and demodulation are combined as a whole to be designed, and a modulation channel is equalized to improve transmission efficiency or improve the spectral efficiency and reliability of a system. The channel coding and decoding and the modulation and demodulation are two independent parts in the traditional digital communication system, and the channel coding and decoding and the modulation and demodulation are respectively and independently carried out, but the polarization phenomenon exists in the modulation channel, so that the spectral efficiency and the reliability of the system are reduced. To be made intoTo overcome the above problems, block Coded Modulation (BCM) was introduced, but BCM relies on the design of excellent Block codes. In order to overcome the defects of the BCM and improve the flexibility, multilevel Coding Modulation (MLC) is introduced, and both the block code and the convolutional code can become component codes, thereby reducing the complexity of the block code design. Polar code, which is a kind of block code, can be used as component code of BCM code to form multilayer Polar code Modulation (MLPC), and when decoding the i-th layer in Successive erasure (SC) decoding, the input probability of the SC decoder is based on the demodulation probability known from the decoding result of the SC of the previous i-1 layer. Thus, MLPC has the following disadvantages: 1) The conventional polar code encoding can start encoding after receiving K information bits, while the MLPC encoder only receives

The information bits are coded only after the information bits are coded, m is the number of stages of multi-level coding modulation, usually, information bits are sent by a signal sink in a serial mode, under the condition that the code length is the same, the coding delay is averagely increased by m times, and the decoding time of simultaneous decoding of a plurality of SC decoders is the decoding time of N bits, so that the MLPC improves the efficiency and the reliability of frequency spectrum which are obtained by replacing coding time with sacrifice; 2) The MLPC needs m codecs to work simultaneously, the bit sequence with the length of mN is coded and decoded, and compared with the coding and decoding processing of the polarization code with the length of N, the hardware complexity and the power consumption are also multiplied; 3) MLPC belongs to the equalization technology on the encoding side, and once the channel quality changes, the encoder needs to receive a channel quality detection report sent by the receiving end and then can correspondingly adjust the code rate, so that the MLPC is not suitable for broadcast channels and fast-changing channels.

It is to be noted that the information invented in the background section above is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

In order to overcome the problems in the related art, the present disclosure provides a demodulation and decoding method, apparatus, storage medium, and electronic device, so as to at least solve the problems in the related art that the decoding time is long and the spectral efficiency and reliability of the system are reduced.

According to an aspect of the present disclosure, there is provided a demodulation and decoding method, the method including:

in response to receiving a modulation signal sent by a sending end through each modulation sub-channel, demodulating the modulation signal to obtain a sequence to be decoded corresponding to the modulation signal;

decoding a plurality of subsections to be decoded obtained by dividing the sequence to be decoded by utilizing a plurality of subsection decoders respectively, and obtaining a plurality of decoding subsections corresponding to the subsections to be decoded respectively based on a first preset threshold value respectively set for each subsection to be decoded;

determining a plurality of target decoding subsegments according to the plurality of decoding subsegments;

and performing sub-segment conversion and sub-segment combination on the target decoding sub-segments to obtain a decoding bit sequence corresponding to the sequence to be decoded.

Optionally, the decoding subsegments include completely decoded subsegments, the decoding is performed on the multiple subsegments to be decoded obtained by dividing the sequence to be decoded by using multiple subsegment decoders, and multiple decoding subsegments respectively corresponding to the multiple subsegments to be decoded are obtained based on first preset thresholds respectively set for each subsegment to be decoded, including:

according to a first preset threshold value corresponding to each of the plurality of subsections to be decoded and a second preset threshold value set for an initial merging path, performing non-continuous deletion list non SCL decoding on the plurality of subsections to be decoded by using the plurality of subsection decoders to obtain a plurality of target merging paths; the initial merging path is a path obtained by merging after decoding according to each subsection to be decoded;

determining a plurality of the fully decoded subsegments based on the plurality of target merge paths.

Optionally, the obtaining a plurality of target merging paths by using the plurality of subsegment decoders to perform non-sequential deletion list non scl decoding on the plurality of subsegments to be decoded according to a first preset threshold corresponding to each of the plurality of subsegments to be decoded and a second preset threshold set for an initial merging path includes:

circularly executing a preset step in the process of decoding the subsegments to be decoded by using the subsegment decoder until the decoded current bit is the tail bit of the subsegment to be decoded, aiming at each subsegment to be decoded, and obtaining a first path probability set of a complete first decoding path corresponding to the subsegment to be decoded based on the bit probability of decoding each bit in the subsegment to be decoded in the process of decoding the subsegment to be decoded by using the corresponding subsegment decoder continuously deleting list SCL;

based on the first path probability set, selecting complete alternative merging paths which meet preset freezing bit constraint conditions and have the path number less than or equal to the second preset threshold value from complete initial merging paths consisting of a plurality of complete first decoding paths to determine as the target merging path;

the presetting step comprises the following steps:

when the decoded current bit is any bit except the tail bit in the subsegment to be decoded, aiming at each subsegment to be decoded, in the process of utilizing the corresponding subsegment decoder to perform continuous deletion list SCL decoding on the subsegment to be decoded, based on the bit probability of decoding each bit in the subsegment to be decoded, obtaining a second path probability set of a non-complete first decoding path corresponding to the subsegment to be decoded;

selecting non-complete alternative merging paths which meet preset freezing bit constraint conditions and have the path number less than or equal to a second preset threshold value from non-complete initial merging paths consisting of a plurality of non-complete first decoding paths based on the second path probability set;

selecting alternative decoding paths with the path number smaller than or equal to a first preset threshold value corresponding to each subsection to be decoded from a plurality of incomplete second decoding paths obtained by dividing each incomplete alternative merging path;

and taking the next bit in the process of decoding the subsegment to be decoded as the current bit, and judging whether the current bit is the tail bit.

Optionally, the selecting, based on the second path probability set, a non-complete alternative merging path that meets a preset freezing bit constraint condition and has a number of paths less than or equal to the second preset threshold from non-complete initial merging paths composed of multiple non-complete first decoding paths includes:

performing path splitting among subsections on the plurality of incomplete first decoding paths to obtain a plurality of incomplete initial merging paths;

checking each incomplete initial merging path by using the preset freezing bit constraint condition, and determining the incomplete initial merging path which meets the preset freezing bit constraint condition as an incomplete third decoding path;

according to the path probability value corresponding to the incomplete third decoding path, sequentially selecting the path with the maximum probability value from the incomplete third decoding paths without replacing the path until the number of the selected paths is less than or equal to the second preset threshold value, and taking the selected incomplete third decoding path as the incomplete alternative merging path; path probability values corresponding to the non-full third coding paths are determined according to the plurality of second path probability sets.

Optionally, the selecting, from a plurality of non-complete second decoding paths obtained by dividing each non-complete alternative merging path, an alternative decoding path whose path number is less than or equal to a first preset threshold corresponding to each sub-segment to be decoded includes:

sub-segment division is carried out on each incomplete alternative merging path to obtain an incomplete second decoding path corresponding to each sub-segment to be decoded;

when the number of paths with different probability values in the non-complete second decoding paths corresponding to the subsegments to be decoded is less than or equal to a first preset threshold corresponding to the subsegments to be decoded, taking a plurality of corresponding non-complete second decoding paths as alternative decoding paths corresponding to the subsegments to be decoded;

when the number of paths with different probability values in the non-complete second decoding paths corresponding to the subsegment to be decoded is larger than a first preset threshold corresponding to the subsegment to be decoded, sequentially selecting the path with the maximum probability value from the plurality of non-complete second decoding paths without putting back, only reserving one path with the same probability value when selecting the path until the number of the selected paths is equal to the first preset threshold, and taking the selected path as an alternative decoding path corresponding to the subsegment to be decoded.

Optionally, the sub-segment division is performed on each of the incomplete alternative merging paths to obtain an incomplete second decoding path corresponding to each of the sub-segments to be decoded, where the sub-segment division includes:

and sub-segment division is carried out on the non-complete alternative merging path according to the number of the sub-segments to be decoded, so as to obtain a non-complete second decoding path corresponding to each sub-segment to be decoded.

Optionally, the determining a plurality of fully decoded subsegments based on the plurality of target merging paths includes:

the target merging paths are checked based on a preset checking mode, and the target merging path which passes the checking and has the maximum probability is determined as a complete decoding path;

and sub-segment division is carried out on the complete decoding path to obtain the plurality of complete decoding sub-segments.

Optionally, the determining a plurality of target decoding subsegments according to the plurality of decoding subsegments includes:

respectively mapping each completely decoded sub-segment according to a preset sub-segment mapping rule to obtain a plurality of initial decoded sub-segments;

and mapping the bits in all the initial decoding subsections according to a preset bit mapping rule to obtain the plurality of target decoding subsections.

Optionally, the performing sub-segment conversion and sub-segment combination on the plurality of target decoding sub-segments to obtain a decoding bit sequence corresponding to the sequence to be decoded includes:

selecting target bits from the decoding bits contained in the target decoding subsections, and converting the target bits into final bits according to a preset subsection conversion rule;

and combining to obtain a decoding bit sequence corresponding to the sequence to be decoded based on the final decoding subsegment corresponding to the final bit.

Optionally, the first preset threshold is determined according to any one or more of modulation sub-channel capacity, channel reliability, simulation effect, or actual measurement result of the communication network corresponding to the sub-segment to be decoded; the first preset threshold value comprises at least two different values.

According to an aspect of the present disclosure, there is provided a demodulation decoding apparatus, the apparatus including:

the demodulation unit is used for responding to the received modulation signals sent by the sending end through each modulation sub-channel, demodulating the modulation signals and obtaining sequences to be decoded corresponding to the modulation signals;

the decoding unit is used for decoding a plurality of subsections to be decoded obtained by dividing the sequence to be decoded by utilizing a plurality of subsections decoders respectively, and obtaining a plurality of decoding subsections corresponding to the plurality of subsections to be decoded respectively based on a first preset threshold value respectively arranged for each subsections to be decoded;

a determining unit, configured to determine a plurality of target decoding subsegments according to the plurality of decoding subsegments;

and the conversion merging unit is used for performing sub-segment conversion and sub-segment merging on the target decoding sub-segments to obtain a decoding bit sequence corresponding to the sequence to be decoded.

Optionally, the decoding subsegments include fully-decoded subsegments, and the decoding unit 502 is further configured to:

Optionally, the decoding unit is further configured to:

circularly executing a preset step in the process of decoding the subsegments to be decoded by using the subsegment decoder until the decoded current bit is the tail bit of the subsegment to be decoded, aiming at each subsegment to be decoded, and obtaining a first path probability set of a complete first decoding path corresponding to the subsegment to be decoded based on the bit probability of decoding each bit in the subsegment to be decoded in the process of continuously deleting a list SCL (service class language) of the subsegment to be decoded by using the corresponding subsegment decoder;

based on the first path probability set, selecting complete alternative merging paths which meet preset freezing bit constraint conditions and have the path number smaller than or equal to the second preset threshold value from complete initial merging paths consisting of a plurality of complete first decoding paths to determine as the target merging paths;

the presetting step comprises the following steps:

Optionally, the decoding unit is further configured to:

each incomplete initial merging path is checked by using the preset freezing bit constraint condition, and the incomplete initial merging path which meets the preset freezing bit constraint condition is determined as a incomplete third decoding path;

sequentially selecting the paths with the maximum probability values from the incomplete third decoding paths without putting back according to the path probability values corresponding to the incomplete third decoding paths until the number of the selected paths is less than or equal to the second preset threshold value, and taking the selected incomplete third decoding paths as the incomplete alternative merging paths; path probability values corresponding to the non-full third coding paths are determined according to the plurality of second path probability sets.

Optionally, the decoding unit is further configured to:

and sub-segment division is carried out on the incomplete alternative merging path according to the number of the sub-segments to be decoded, and an incomplete second decoding path corresponding to each sub-segment to be decoded is obtained.

Optionally, the decoding unit is further configured to:

Optionally, the determining unit is further configured to:

Optionally, the transform combining unit is further configured to:

According to an aspect of the present disclosure, there is provided a computer-readable storage medium having a computer program stored thereon, the computer program, when executed by a processor, implementing the demodulation and decoding method of any one of the above.

According to an aspect of the present disclosure, there is provided an electronic device including:

a processor; and

a memory for storing executable instructions of the processor;

wherein the processor is configured to perform any one of the above demodulation decoding methods via execution of the executable instructions.

To sum up, the demodulation and decoding method provided by the embodiment of the present disclosure may first demodulate a modulation signal sent by a sending end through each modulation subchannel in response to receiving the modulation signal, to obtain a sequence to be decoded corresponding to the modulation signal, decode a plurality of subsections to be decoded obtained by dividing the sequence to be decoded respectively by using a plurality of subsections decoders based on a first preset threshold value respectively set for each subsection to be decoded, to obtain a plurality of decoding subsections respectively corresponding to the plurality of subsections to be decoded, determine a plurality of target decoding subsections according to the plurality of decoding subsections, perform subsection transformation and subsection combination on the plurality of target decoding subsections, and obtain a decoding bit sequence corresponding to the sequence to be decoded. Therefore, the decoding time is shortened by decoding the plurality of subsegments to be decoded by the plurality of subsegment decoders respectively, the decoding complexity is reduced to a certain extent, the number of alternative paths can be correspondingly adjusted at any time according to a channel quality detection report of a receiving end based on the first preset threshold value respectively set for each subsegment to be decoded, the response speed is improved, and the method can be applied to receiving of a one-way transmission system.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 schematically illustrates a flowchart of steps of a demodulation and decoding method provided in an embodiment of the present disclosure;

fig. 2 is a flowchart schematically illustrating steps of obtaining a plurality of decoding subsections provided by an embodiment of the present disclosure;

fig. 3 is a flowchart schematically illustrating steps of obtaining a target merging path according to an embodiment of the present disclosure;

fig. 4 is a flow chart schematically illustrating steps provided by an embodiment of the present disclosure to determine a plurality of decoding subsections;

FIG. 5 is a flow chart schematically illustrating steps provided by an embodiment of the present disclosure to determine a plurality of target decoding subsections;

FIG. 6 is a flow chart schematically illustrating the steps provided by an embodiment of the present disclosure to determine a decoded bit sequence;

fig. 7 schematically illustrates a block diagram of a demodulation decoding apparatus provided in an embodiment of the present disclosure;

fig. 8 schematically illustrates an electronic device for implementing the demodulation and decoding method according to an embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

The technical scheme of the embodiment of the disclosure can be applied to various communication systems. For example, the Mobile communication System includes a 5G communication System, a Global System for Mobile communications (GSM) System, a Code Division Multiple Access (CDMA) System, a Wideband Code Division Multiple Access (WCDMA) System, a General Packet Radio Service (GPRS), a Long Term Evolution (LTE) System, an LTE Frequency Division Duplex (FDD) System, an LTE Time Division Duplex (TDD), a Universal Mobile Telecommunications System (UMTS), and the like.

Fig. 1 is a flowchart of steps of a demodulation and decoding method provided in this disclosure, where the method may be executed by a receiving end, the receiving end may be a device for demodulating and decoding a modulated signal of a sending end, the receiving end may be an access network device or a terminal device, and the receiving end may also be another device that needs to perform channel decoding. As shown in fig. 1, the method may include:

step S101, in response to receiving a modulation signal sent by a sending end through each modulation sub-channel, demodulating the modulation signal to obtain a sequence to be decoded corresponding to the modulation signal.

In the embodiment of the present disclosure, after receiving the modulation signal sent by the sending end through each modulation subchannel, the receiving end may demodulate the modulation signal to obtain the sequence to be decoded. Specifically, the process of demodulating the modulated signal may be an inverse process corresponding to the generation of the modulated signal on the transmitting end, and the disclosure is not limited thereto. The sending end may be an access network device or a terminal device, or may also be other devices that need to perform channel coding, and the modulated signal may be obtained by mapping different coding sub-segments to modulation sub-channels with different channel capacities. It should be noted that the modulation subchannel may be an equivalent channel of the modulation channel, and is not an independent physical channel.

It should be noted that in the encoding process, a bit sequence to be encoded with a length of N may be divided into m sub-segments to be encoded 1,m with a length of N, sub-segment 1 to be encoded 2,m sub-segments to be encoded 2, which are subjected to sub-segment conversion, and then bit mapping is performed to obtain m sub-segments to be encoded 3,m sub-segments to be encoded 3, which are subjected to polarization code encoding to obtain m encoded sub-segments, then, the m encoded sub-segments are respectively corresponding to p modulation sub-channels, and finally, the m encoded sub-segments are modulated to obtain a modulation signal, N, N and m may both be an integral power of 2, and p is a positive integer.

Step S102, a plurality of subsegments to be decoded obtained by dividing the sequence to be decoded are decoded by a plurality of subsegment decoders respectively, and a plurality of decoding subsegments respectively corresponding to the plurality of subsegments to be decoded are obtained based on first preset thresholds respectively set for each subsegment to be decoded.

In the embodiment of the disclosure, a sequence to be decoded may be divided to obtain a plurality of subsections to be decoded, the plurality of subsections to be decoded correspond to a plurality of coding subsections obtained at a coding side one by one, then the plurality of subsections to be decoded are decoded by a plurality of subsections decoders respectively, and a plurality of decoding subsections corresponding to the plurality of subsections to be decoded are obtained based on a first preset threshold value respectively set for each subsections to be decoded. The sub-segment decoders are used for decoding a plurality of sub-segments to be decoded respectively, each sub-segment to be decoded may correspond to one sub-segment decoder, the plurality of sub-segment decoders decode the corresponding sub-segments to be decoded respectively to obtain the decoded sub-segments corresponding to each sub-segment to be decoded, and the sub-segment decoders may be SCL (sequential deletion List) decoders.

In the embodiment of the present disclosure, the sequence to be decoded is divided into a plurality of subsegments to be decoded, and specifically, the number of the subsegments to be decoded obtained by dividing may be the same as the number of the subsegments to be encoded obtained by dividing at the encoding side. For example, the encoding side divides into m subsegments to be encoded in the encoding process, and the m subsegments to be encoded are subjected to subsegment transformation, bit mapping, subsegment mapping and subsegment encoding to obtain m encoding subsegments, so that correspondingly, the decoding side can divide the sequence to be decoded into m subsegments to be decoded in the decoding process, and thus m subsegments to be decoded are obtained, wherein m can be an integer power of 2. The number of the specific division subsegments can be set in advance according to actual situations.

It should be noted that the first preset threshold may include a path number threshold set according to each sub-segment to be decoded, and the first preset thresholds corresponding to different sub-segments to be decoded may be different or the same. Specifically, the path number threshold set for each sub-segment to be decoded in the first preset threshold may be determined according to the number of corresponding adjustment paths of a channel quality detection report at a receiving end, so that the decoding path number may be suitable for a broadcast channel and a fast-changing channel, or may be determined according to any one or more of the capacity of a modulation sub-channel corresponding to the sub-segment to be decoded, the reliability of the channel, the simulation effect, or the actual measurement result of the communication network.

Step S103, a plurality of target decoding subsegments are determined according to the plurality of decoding subsegments.

In the embodiment of the present disclosure, the plurality of decoding subsections may be subjected to mapping conversion based on the corresponding decoding mapping rules, so as to obtain the corresponding plurality of target decoding subsections respectively. Specifically, the sub-segment mapping may be performed together with respect to the whole sub-segment, and the bit mapping may be performed sequentially with respect to each bit, and the decoding mapping rule may be a mapping rule that is processed in inverse manner with respect to the coding mapping rule on the coding side.

And step S104, performing sub-segment conversion and sub-segment combination on the target decoding sub-segments to obtain a decoding bit sequence corresponding to the sequence to be decoded.

In the embodiment of the present disclosure, sub-segment conversion and sub-segment combination may be performed on a plurality of target decoding sub-segments according to a preset sub-segment conversion mode, and a result after the sub-segment conversion and the sub-segment combination is taken as a decoding bit sequence corresponding to a sequence to be decoded, where the preset sub-segment conversion mode may be a conversion rule that is inverse to a coding-side sub-segment conversion rule.

To sum up, the demodulation and decoding method provided by the embodiment of the present disclosure may first demodulate a modulation signal in response to receiving the modulation signal sent by a sending end through each modulation subchannel, to obtain a sequence to be decoded corresponding to the modulation signal, decode a plurality of subsections to be decoded obtained by dividing the sequence to be decoded respectively by using a plurality of subsections decoders, obtain a plurality of decoding subsections corresponding to the plurality of subsections to be decoded respectively based on a first preset threshold value set for each subsection to be decoded respectively, determine a plurality of target decoding subsections according to the plurality of decoding subsections, perform subsection transformation and subsection combination on the plurality of target decoding subsections, and obtain a decoding bit sequence corresponding to the sequence to be decoded. Therefore, the decoding time is shortened by respectively decoding a plurality of subsegments to be decoded by a plurality of subsegment decoders, the decoding complexity is reduced to a certain extent, the number of alternative paths can be correspondingly adjusted at any time according to a channel quality detection report of a receiving end based on a first preset threshold value respectively set for each subsegment to be decoded, the response speed is improved, and the method can be applied to the receiving of a one-way transmission system.

Optionally, the decoding subsegments in the embodiment of the present disclosure may include completely decoded subsegments, where the completely decoded subsegments may represent that the head and tail bits of two adjacent completely decoded subsegments correspond to consecutive bits in the sequence to be decoded, that is, the tail bit of the last completely decoded subsegment and the head bit of the next completely decoded subsegment correspond to consecutive bits in the sequence to be decoded. The above decoding, by using the multiple sub-segment decoders, the multiple sub-segments to be decoded obtained by dividing the sequence to be decoded respectively, and obtaining, based on the first preset threshold value respectively set for each sub-segment to be decoded, an operation of the multiple decoding sub-segments respectively corresponding to the multiple sub-segments to be decoded, as shown in fig. 2, may specifically include:

step S1021, according to a first preset threshold value corresponding to each of the plurality of subsections to be decoded and a second preset threshold value set for an initial merging path, performing non-continuous deletion list non SCL decoding on the plurality of subsections to be decoded by using the plurality of subsection decoders to obtain a plurality of target merging paths; the initial merging path is obtained by merging after each subsection to be decoded is decoded.

In the embodiment of the disclosure, a plurality of subsections to be decoded may be processed in parallel, each subsection to be decoded corresponds to a subsection decoder, the corresponding subsection decoder is used to decode the subsections to be decoded in a non-continuous deletion list non scl, and the number of paths obtained by decoding is screened out based on a first preset threshold value corresponding to each subsection to be decoded and a second preset threshold value set for an initial merging path, so as to obtain a plurality of target merging paths. The initial merging path may be a path obtained by merging after decoding each sub-segment to be decoded, and the target merging path may represent that each decoding path corresponding to each decoded sub-segment is merged into one decoding path after decoding each sub-segment to be decoded is completed.

Step S1022, based on the target merging paths, determining a plurality of fully decoded subsections.

In the embodiment of the present disclosure, a preset Check manner may be performed on the obtained multiple target combining paths, where the preset Check manner may be a combination of Cyclic Redundancy Check (CRC), parity Check (PC), cyclic Redundancy Check and Parity Check, or other Check manners, and the target combining path that passes the Check and has the largest path probability is obtained as a complete decoding path, and then sub-segment conversion and sub-segment combination are performed on the complete decoding path to determine a corresponding multiple complete decoding sub-segments.

Optionally, in the embodiment of the present disclosure, the operation of performing non-sequential deletion list nonSCL decoding on the multiple subsegments to be decoded by using the multiple subsegment decoders according to the first preset threshold and the second preset threshold set for the initial merging path, where the first preset threshold corresponds to the multiple subsegments to be decoded, respectively, to obtain multiple target merging paths may specifically include:

step S201, circularly executing a preset step in the process of decoding the subsegments to be decoded by using the subsegment decoder until the current decoded bit is the tail bit of the subsegment to be decoded, aiming at each subsegment to be decoded, and obtaining a first path probability set of a complete first decoding path corresponding to the subsegment to be decoded based on the bit probability of decoding each bit in the subsegment to be decoded in the process of continuously deleting SCL (list of bits) of the subsegment to be decoded by using the corresponding subsegment decoder.

In the embodiment of the present disclosure, a preset step may be cyclically executed in a process of decoding a to-be-decoded sub-segment by using a sub-segment decoder, that is, in a bit-by-bit decoding process, a preset step needs to be executed for decoding each bit until a current bit of decoding corresponds to a tail bit of the to-be-decoded sub-segment, for each to-be-decoded sub-segment, a continuous deletion list SCL decoding is respectively executed for each bit included in the to-be-decoded sub-segment by using a corresponding sub-segment decoder, a bit probability of each bit decoding in the to-be-decoded sub-segment is determined in the decoding process, and then a first path probability set corresponding to a complete first decoding path is determined according to a bit probability of each bit decoding in the to-be-decoded sub-segment, where the complete first decoding path may be a decoding path composed of a corresponding decoding sub-segment from a head bit to a tail bit in the decoding process of the to-be-decoded sub-segment, the number of the complete first decoding path may be plural, and correspondingly, the first path probability set may be a set corresponding to a probability set corresponding to each complete first decoding path.

For example, assuming that there are 4 bits in the sub-segment 1 to be decoded, which may be [ a, b, c, d ], if the decoding process has been decoded from the head bit a to the tail bit d, that is, a decoding path composed of the bits a to b and b to c and c to d may be decoded as a complete first decoding path, and a bit probability of decoding the bit a as 0/1 may be [0.8,0.2], a bit probability of the bit b as [0.4,0.6], a bit probability of the bit c as [0.31,0.69], a bit probability of the bit d as [0.7,0.3], thus, 16 complete first decoding paths may be obtained, that is, 0.8 in the bits a- [0.8,0.2] may be the first bit probability as path 1, 0.4 in the bits b- [0.4,0.6] may be the second bit probability as path 1, and a bit probability of the bits c- [ 25 zxft ] may be the last bit probability of three paths as 34577, 3432: 0.8-0.4-0.31-0.7. Similarly, the bit probability of path 2 can be expressed as: the bit probability for path 3, 0.8-0.4-0.69-0.7, is expressed as: the bit probability of path 4, 0.8-0.6-0.69-0.7, is expressed as: the bit probability for path 5, 0.8-0.6-0.31-0.7, is expressed as: the bit probability of 0.2-0.4-0.31-0.7, path 6 is expressed as: the bit probability of 0.2-0.4-0.69-0.7, path 7 is expressed as: the bit probability for path 8, 0.2-0.6-0.69-0.7, is expressed as: 0.2-0.6-0.31-0.7, the bit probability for path 9 is expressed as: 0.8-0.4-0.31-0.3, the bit probability for path 10 is expressed as: the bit probability for path 11, 0.8-0.4-0.69-0.3, is expressed as: the bit probability for path 12, 0.8-0.6-0.69-0.3, is expressed as: the bit probability for path 13, 0.8-0.6-0.31-0.3, is expressed as: the bit probability for path 14, 0.2-0.4-0.31-0.3, is expressed as: the bit probability for path 15, 0.2-0.4-0.69-0.3, is expressed as: the bit probability of 0.2-0.6-0.69-0.3, path 16 is expressed as: 0.2-0.6-0.31-0.3. The path probability value corresponding to each path can be calculated based on the bit probability value corresponding to each bit decoding, so that the path probability of path 1 is 0.06944, the path probability of path 2 is 0.15456, the path probability of path 3 is 0.23184, the path probability of path 4 is 0.10416, the path probability of path 5 is 0.01736, the path probability of path 6 is 0.03864, the path probability of path 7 is 0.05796, the path probability of path 8 is 0.02604, the path probability of path 9 is 0.02976, the path probability of path 10 is 0.06624, the path probability of path 11 is 0.09936, the path probability of path 12 is 3535 zxft 3584, the path probability of path 13 is 0.00744, the path 14 is 3284, the path probability of path 84 is 0.09936, the path probability of path 12 is 3535 zxft, the path probability of path 13 is a first path 4225, and the path probability of a first path 4225 is 4262. The path decoding probability set which can be expressed according to the first path 4223. The first path.

Step S202, based on the first path probability set, selecting, from complete initial merging paths composed of multiple complete first decoding paths, complete candidate merging paths that meet a preset freezing bit constraint condition and whose number of paths is less than or equal to the second preset threshold value, and determining the complete candidate merging paths as the target merging path.

In this embodiment of the disclosure, all completely first decoding paths obtained by decoding may be first spliced to form a completely initial merging path, then a path probability value corresponding to each completely initial merging path is determined based on the first path probability set, a completely initial merging path meeting a preset freezing bit constraint condition is selected from the multiple completely initial merging paths according to the number of paths indicated by a second preset threshold as a completely alternative merging path, and the selected completely alternative merging path is determined as a target merging path, that is, the number of paths of the completely alternative merging path may be less than or equal to the second preset threshold.

In step S201, the preset steps to be executed may include steps S203 to S206, as shown in fig. 3, specifically as follows:

step S203, when the decoded current bit is any bit except tail bit in the subsegment to be decoded, aiming at each subsegment to be decoded, in the process of utilizing the corresponding subsegment decoder to continuously delete list SCL decoding on the subsegment to be decoded, based on the bit probability of decoding each bit in the subsegment to be decoded, a second path probability set of the non-complete first decoding path corresponding to the subsegment to be decoded is obtained.

In the embodiment of the disclosure, when each sub-segment to be decoded is decoded in parallel, when the current bit to be decoded is any bit except the tail bit in the sub-segment to be decoded, the corresponding sub-segment decoder may be used to decode the continuous deletion list SCL for each sub-segment to be decoded, during the decoding process, the bit probability of decoding each bit in the sub-segment to be decoded is determined, and then, according to the bit probability of decoding each bit in the sub-segment to be decoded, the second path probability set corresponding to the incomplete first decoding path is determined, wherein the incomplete first decoding path may be a decoding path composed of a head bit to a current bit in the corresponding decoding sub-segment during the decoding process of the sub-segment to be decoded, the current bit may be the bit to be decoded in the sub-segment to be decoded which the corresponding sub-segment decoder in the sub-segment to be decoded is decoding, the number of the incomplete first decoding paths may be plural, and correspondingly, the second path probability set may be a set corresponding to the path probability set corresponding to each incomplete first decoding path.

For example, assuming that there are 4 bits in the sub-segment 1 to be decoded, which may be [ a, b, c, d ], if the decoding process has been performed from bit a to bit c, that is, a decoding path composed of bit a to bit b and bit b to bit c may be used as a non-complete first decoding path, and a bit probability of decoding bit a as 0/1 may be [0.8,0.2], a bit probability of bit b as [0.4,0.6], a bit probability of bit c as [0.31,0.69], so that 8 non-complete first decoding paths may be obtained, that is, 0.8 in bit a- [0.8,0.2] may be a first bit probability as path 1, 0.4 in bit b- [0.4,0.6] may be a second bit probability as path 1, 0.31 in bit c- [0.31,0.69] may be a third bit probability as path 1, and an available bit probability of bit c [ 3238 zxft 3234 ] may be expressed as: 0.8-0.4-0.31. Similarly, the bit probability of path 2 can be expressed as: the bit probability for path 3, 0.8-0.4-0.69, is expressed as: the bit probability of path 4, 0.8-0.6-0.69, is expressed as: the bit probability for path 5, 0.8-0.6-0.31, is expressed as: the bit probability for path 6, 0.2-0.4-0.31, is expressed as: the bit probability for path 7, 0.2-0.4-0.69, is expressed as: the bit probability for path 8, 0.2-0.6-0.69, is expressed as: 0.2-0.6-0.31. The path probability value corresponding to each path can be calculated based on the bit probability value corresponding to each bit decoding, so that the path probability of path 1 is 0.0992, the path probability of path 2 is 0.2208, the path probability of path 3 is 0.3312, the path probability of path 4 is 0.1488, the path probability of path 5 is 0.0248, the path probability of path 6 is 0.0552, the path probability of path 7 is 0.0828, the path probability of path 8 is 0.0372 can be obtained, a corresponding second path probability set can be formed according to the path probability value of each non-complete first decoding path, and the second path probability set can be expressed as {0.0992,0.2208,0.3312,0.1488,0.0248,0.0552,0.0828,0.0372}.

And step S204, selecting non-complete alternative merging paths which accord with a preset freezing bit constraint condition and the number of which is less than or equal to a second preset threshold value from non-complete initial merging paths consisting of a plurality of non-complete first decoding paths based on the second path probability set.

In the embodiment of the present disclosure, all the obtained incomplete first decoding paths may be first spliced to form an incomplete initial merging path, then the path probability value of the incomplete initial merging path is determined according to the second path probability set, and the incomplete initial merging path meeting the preset freezing bit constraint condition is selected from the multiple incomplete initial merging paths according to the path number indicated by the second preset threshold as the incomplete alternative merging path, that is, the path number of the incomplete alternative merging path may be less than or equal to the second preset threshold.

Step S205, selecting, from a plurality of incomplete second decoding paths obtained by dividing each incomplete alternative merging path, an alternative decoding path whose path number is less than or equal to a first preset threshold corresponding to each sub-segment to be decoded.

In the embodiment of the present disclosure, each incomplete alternative merging path may be divided into sub-segments according to the number of each sub-segment to be decoded, to obtain a plurality of incomplete second decoding paths, and then, from the plurality of incomplete second decoding paths, according to a first preset threshold set for the sub-segments to be decoded corresponding to the incomplete second decoding paths, the incomplete second decoding path whose path number is less than or equal to the first preset threshold is selected as the alternative decoding path corresponding to each sub-segment to be decoded.

Step S206, taking the next bit in the process of decoding the subsegment to be decoded as the current bit, and judging whether the current bit is the tail bit.

In the embodiment of the present disclosure, a next bit of decoding processing of a corresponding sub-segment decoder in each sub-segment to be decoded may be used as a current bit, and it is determined whether the current bit corresponds to a tail bit in the sub-segment to be decoded, if not, steps S203 to S206 may be executed again, and if the current bit is the tail bit, steps S201 to S202 may be executed.

It should be noted that, in steps 201 to 206, since in the decoding process, the incomplete first decoding path or the complete first decoding path is obtained by dividing the incomplete alternative merging path or the complete alternative merging path, when the incomplete alternative merging path or the complete alternative merging path is generated, the same incomplete first decoding path may simultaneously appear in different incomplete alternative merging paths or complete alternative merging paths, so that after the incomplete alternative merging path or the complete alternative merging path is divided, a plurality of the same incomplete first decoding paths or complete first decoding paths may be obtained. Meanwhile, the path probability values of the plurality of non-full first coding paths or the full first coding path may be completely equal. Therefore, in order to avoid confusing a plurality of incomplete first decoding paths with equal path probability values or the same incomplete first decoding path or complete first decoding path with multiple occurrences of the complete first decoding path and the path probability values, the path probability values of the plurality of incomplete first decoding paths or complete first decoding paths with equal path probability values need to be processed. In one implementation, if the path probability values of the multiple incomplete first decoding paths or the complete first decoding paths are completely equal, one additional bit may be added after the last bit of the path probability value of the first decoding path with equal probability value, and 1, 2, 3, … is assigned, so that the path probability values of the multiple incomplete first decoding paths or the complete first decoding paths are unequal, and the added additional bit is only used for distinguishing the incomplete first decoding paths or the complete first decoding paths with equal path probability values, and does not participate in numerical calculation of the decoding process. In another implementation, if the path probability values of the plurality of non-full first decoding paths or full first decoding paths are completely equal, a label may be added to the non-full first decoding paths or full first decoding paths with equal probability values, and the added label is used to distinguish the non-full first decoding paths or full first decoding paths with equal probability values.

It should be noted that when a plurality of subsegment decoders are used for decoding a plurality of subsegments to be decoded, the plurality of subsegments to be decoded can be decoded through the non-continuous deletion list non SCL, and when each subsegment to be decoded is decoded by using the subsegment decoder, the subsegment to be decoded can be decoded through the continuous deletion list SCL.

Optionally, when the decoded current bit is any bit except the tail bit in the sub-segment to be decoded, in the embodiment of the present disclosure, the operation of selecting the incomplete alternative merging path, which meets the preset frozen bit constraint condition and has a number of paths less than or equal to the second preset threshold, from the incomplete initial merging paths composed of the multiple incomplete first decoding paths based on the second path probability set may specifically include:

performing path splitting among subsections on the plurality of incomplete first decoding paths to obtain a plurality of incomplete initial merging paths; each incomplete initial merging path is checked by using the preset freezing bit constraint condition, and the incomplete initial merging path which meets the preset freezing bit constraint condition is determined as a incomplete third decoding path; according to the path probability value corresponding to the incomplete third decoding path, sequentially selecting the path with the maximum probability value from the incomplete third decoding paths without replacing the path until the number of the selected paths is less than or equal to the second preset threshold value, and taking the selected incomplete third decoding path as the incomplete alternative merging path; path probability values corresponding to the non-full third coding paths are determined according to the plurality of second path probability sets.

In the embodiment of the present disclosure, path splitting between sub-segments may be performed between first decoding paths corresponding to each sub-segment to be decoded, and a plurality of incomplete initial merging paths are obtained by splicing, for example, if the sub-segment 1 to be decoded corresponds to the path 1.1 and the path 1.2, and if the sub-segment 2 to be decoded corresponds to the path 2.1 and the path 2.2, path splitting between sub-segments may be performed between first decoding paths corresponding to each sub-segment to be decoded, so as to obtain [ path 1.1-path 2.1], [ path 1.1-path 2.2], [ path 1.2-path 2.1], [ path 1.2-path 2.2], as an incomplete initial merging path.

In the embodiment of the present disclosure, each incomplete initial merging path is checked by using a preset frozen bit constraint condition, the incomplete initial merging path that meets the preset frozen bit constraint condition is determined as a incomplete third decoding path, or the preset frozen bit constraint condition check is performed on each incomplete initial merging path, and a path that passes the check is determined as a incomplete third decoding path. Specifically, the checking of the preset frozen bit constraint condition on the incomplete initial merging path may include checking whether an xor operation result of corresponding bits in the incomplete initial merging path is consistent with the frozen bit based on a preset sub-segment transformation rule and a preset mapping rule when the final bit is the frozen bit. This can improve decoding performance. The freeze bit may be represented by any set value (e.g., 0,1, etc.) or an identifier, etc., and the embodiments of the present disclosure are not limited thereto.

In this embodiment of the disclosure, the paths with the maximum probability values are sequentially selected from the incomplete third decoding paths without being put back according to the path probability values corresponding to the incomplete third decoding paths until the number of the selected paths is less than or equal to a second preset threshold, the selected incomplete third decoding paths are used as the incomplete alternative merging paths, the incomplete third decoding paths may be arranged according to the path probability values corresponding to the incomplete third decoding paths, the incomplete third decoding paths with the maximum probability values are sequentially selected without being put back from the arrangement sequence until the number of the selected paths is less than or equal to the second preset threshold, and the selected incomplete third decoding paths are used as the incomplete alternative merging paths.

For example, it is assumed that the incomplete first decoding path corresponding to the sub-segment 1 to be decoded has a path 1.1, a path 1.2, a path 1.3, and a path 1.4, the incomplete first decoding path corresponding to the sub-segment 2 to be decoded has a path 2.1, a path 2.2, a path 2.3, and a path 2.4, and path splitting between sub-segments is performed on the incomplete first decoding paths corresponding to different sub-segments to be decoded, and an incomplete alternative merging path meeting a preset freezing bit constraint condition and having a path number less than or equal to a second preset threshold may be selected, where the second preset threshold may be 8, and then the incomplete initial merging path may be [ path 1.1-path 2.1], [ path 1.2-path 2.1], [ path 1.3-path 2.1], [ path 1.4-path 2 path 1.3 ], [ path 1.4-path 2 path 1.2 path 4-path ] and [ path 4.2.2 path 4-2 path ], [ path 4 path 4.2 path ], [ path ] path. If [ path 1.3-path 2.3], [ path 1.4-path 2.3], [ path 1.1-path 2.4], [ path 1.2-path 2.4], [ path 1.3-path 2.4], [ path 1.4-path 2.4] do not meet the preset freeze bit constraint condition, the above paths can be deleted, and [ path 1.1-path 2.3], [ path 1.2-path 2.3] is deleted according to the path probability value corresponding to the incomplete initial merging path, so that the number of paths is equal to a second preset threshold, and thus the incomplete alternative merging paths [ path 1.1-path 2.1], [ path 1.2-path 2.1], [ path 1.3-path 2.1], [ path 1.4-path 2.1], [ path 1.1-path 2.2], [ path 1.3-path 2.1] and [ path 1.4-path 2.2.2 ] can be obtained.

Optionally, in the embodiment of the present disclosure, the operation of selecting, from a plurality of non-complete second decoding paths obtained by dividing each non-complete alternative merging path, an alternative decoding path whose path number is less than or equal to a first preset threshold corresponding to each sub-segment to be decoded may specifically include:

sub-segment division is carried out on each incomplete alternative merging path to obtain an incomplete second decoding path corresponding to each sub-segment to be decoded; when the number of paths with different probability values in the non-complete second decoding paths corresponding to the subsegments to be decoded is less than or equal to a first preset threshold corresponding to the subsegments to be decoded, taking the paths with different probability values in the corresponding multiple non-complete second decoding paths as alternative decoding paths corresponding to the subsegments to be decoded; and when the number of paths with different probability values in the non-complete second decoding paths corresponding to the subsegments to be decoded is greater than a first preset threshold value corresponding to the subsegments to be decoded, sequentially selecting the path with the maximum probability value from the plurality of non-complete second decoding paths without putting back, only reserving one path with the same probability value when selecting the path until the number of the selected paths is equal to the first preset threshold value, and taking the selected path as an alternative decoding path corresponding to the subsegments to be decoded.

It should be noted that, in the embodiment of the present disclosure, the paths with different probability values in the non-complete second decoding paths corresponding to the sub-segments to be decoded may be different non-complete first decoding paths in the non-complete second decoding paths. And sequentially selecting the paths with the maximum probability values from the plurality of non-complete second decoding paths without replacing, wherein only one path with the same probability value is reserved when the paths are selected, and the paths can be the non-complete first decoding paths with the maximum probability values sequentially selected from the plurality of non-complete second decoding paths.

In the embodiment of the present disclosure, each incomplete alternative merging path is sub-segment divided to obtain an incomplete second decoding path corresponding to each sub-segment to be decoded, and the sub-segment division may be performed on each incomplete alternative merging path according to the number of the sub-segments to be decoded, so that an incomplete second decoding path corresponding to each sub-segment to be decoded may be obtained.

In the embodiment of the present disclosure, the number of paths with different probability values in the incomplete second decoding path corresponding to each sub-segment to be decoded may be detected, and when the number of paths is less than or equal to a first preset threshold corresponding to the sub-segment to be decoded, the corresponding incomplete second decoding paths with different probability values in all the incomplete second decoding paths may be used as alternative decoding paths corresponding to the sub-segment to be decoded; when the number of the paths is greater than a first preset threshold corresponding to the subsection to be decoded, the paths with the maximum probability value can be sequentially selected from a plurality of incomplete second decoding paths without being replaced, only one path with the same probability value is reserved when the paths are selected until the number of the selected paths is equal to the first preset threshold, and the selected paths are used as alternative decoding paths corresponding to the subsection to be decoded.

It should be noted that the first preset threshold may be determined according to any one or more of modulation subchannel capacity, channel reliability, simulation effect, or actual measurement result of the communication network corresponding to the subsegment to be decoded, the first preset thresholds corresponding to different subsegments to be decoded may be different or the same, and the first preset threshold may include at least two different values, that is, the decoding path obtained when decoding different subsegments to be decoded needs to be screened according to the first preset threshold corresponding to each subsegment to be decoded, and if the number of paths obtained by decoding exceeds the first preset threshold, the problem of too large data size and long processing time in decoding processing may be caused.

Optionally, in the embodiment of the present disclosure, the performing sub-segment division on each of the non-complete alternative merging paths to obtain an operation of a non-complete second decoding path corresponding to each of the sub-segments to be decoded may specifically include:

For example, assuming that there are 8 subsections to be decoded, the path length of the incomplete alternative merging path is 128 bits, the subsection division is performed on the incomplete alternative merging path according to the number of the subsections to be decoded, the subsections can be divided according to 8 bits, the length of the obtained subsections obtained by the division is 16 bits, and thus, an incomplete second decoding path corresponding to each subsection to be decoded can be obtained.

Optionally, when the current bit of the decoding is a tail bit in the sub-segment to be decoded, in the embodiment of the present disclosure, based on the first path probability set, selecting, from the complete initial merging paths composed of multiple complete first decoding paths, a complete alternative merging path that meets a preset freezing bit constraint condition and has a path number less than or equal to the second preset threshold as the operation of determining the target merging path may specifically include:

performing path splitting among subsections on the complete first decoding paths to obtain a plurality of complete initial merging paths; checking each complete initial merging path by using the preset freezing bit constraint condition, and determining the complete initial merging path which meets the preset freezing bit constraint condition as a complete third decoding path; sequentially selecting the paths with the maximum probability values from the complete third decoding paths without putting back according to the path probability values corresponding to the complete third decoding paths until the number of the selected paths is less than or equal to the second preset threshold value, and taking the selected complete third decoding paths as the complete alternative merging paths; path probability values corresponding to the full third coding path are determined according to the plurality of second path probability sets; and determining the selected complete alternative merging path as the target merging path.

In the embodiment of the present disclosure, the specific operation content of the above steps is as described above, and is not described herein again.

For example, suppose that the complete first decoding path corresponding to the sub-segment 1 to be decoded includes path 1.1, path 1.2, path 1.3, path 1.4, and path 1.5, and the complete first decoding path corresponding to the sub-segment 2 to be decoded includes path 2.1, path 2.2, path 2.3, path 2.4, and path 2.5, and the path splitting among the sub-segments is performed on the complete first decoding paths corresponding to different sub-segments to be decoded, and a complete alternative merging path meeting a preset freeze bit constraint condition and having a number of paths less than or equal to a second preset threshold is selected, where the second preset threshold may be 8, a complete initial merged path can be obtained as [ path 1.1-path 2.1], [ path 1.2-path 2.1], [ path 1.3-path 2.1], [ path 1.4-path 2.1], [ path 1.5-path 2.1], [ path 1.1-path 2.2], [ path 1.2-path 2.2], [ path 1.3-path 2.2], [ path 1.4-path 2.2], [ path 1.5-path 2.2], [ path 1.1-path 2.3], [ path 1.2-path 2.3], [ path 1.3-path 2.3], [ path 1.4-path 2.3], [ path 1.5-path 2.3], [ path 1.1-path 2.4], [ path 1.4-path 2.4], [ path 1.4 ] path 2.5-path 2.5] path 2.3], [ path 1.5-path 1-path 2.5] path 2.5-path 2.5] path 1-path 2.5, path 2.5-path 2.5] and [ path 1.5-path 2.5. If it is detected that [ path 1.3-path 2.3], [ path 1.4-path 2.3], [ path 1.5-path 2.3], [ path 1.1-path 2.4], [ path 1.2-path 2.4], [ path 1.3-path 2.4], [ path 1.4-path 2.4], [ path 1.5-path 2.4], [ path 1.1-path 2.5], [ path 1.2-path 2.5], [ path 1.3-path 2.5], [ path 1.4-path 2.5], [ path 1.5-path 2.5] do not comply with the preset freeze bit constraint, the above-mentioned path can be deleted and, according to the path probability value corresponding to the complete initial merged path, deleting [ path 1.1-path 2.3], [ path 1.2-path 2.3], so that the number of paths is equal to a second preset threshold, and thus, the complete alternative merged paths are [ path 1.1-path 2.1], [ path 1.2-path 2.1], [ path 1.3-path 2.1], [ path 1.4-path 2.1], [ path 1.5-path 2.1], [ path 1.1-path 2.2], [ path 1.2-path 2.2], [ path 1.3-path 2.2], [ path 1.4-path 2.2], [ path 1.5-path 2.2] can be obtained.

Optionally, in the embodiment of the present disclosure, the determining a plurality of fully decoded subsegments based on the plurality of target merging paths as shown in fig. 4 includes:

step S301, verifying the multiple target merging paths based on a preset verification manner, and determining the target merging path that passes the verification and has the highest probability as a complete decoding path.

In the embodiment of the present disclosure, a preset check manner may be used to check the multiple target combining paths, and the target combining path that passes the check and has the highest probability is selected as the complete decoding path, where the preset check manner may include, but is not limited to, cyclic redundancy check and parity check. The cyclic redundancy check code may be generated according to the mixed bits and the pure information bits/information bits in the sub-segments to be encoded, and the check code bits may be arranged in the pure information bits/information bits in the sub-segments to be encoded. If a plurality of check code schemes are adopted, a plurality of check codes can be generated according to corresponding mixed bits and pure information bits/information bits in the subsegments to be coded, and bits of the plurality of check codes can be arranged on the pure information bits/information bits in the subsegments to be coded.

Step S302, sub-segment division is carried out on the complete decoding path, and the plurality of complete decoding sub-segments are obtained.

In the embodiment of the present disclosure, the sub-segment division may be performed on the complete decoding path according to the number of the sub-segments to be decoded, or the sub-segment division may be performed on the complete decoding path according to the sub-segment length indicated by each sub-segment to be decoded, so as to obtain the complete decoding sub-segment corresponding to each sub-segment to be decoded.

Optionally, in the embodiment of the present disclosure, the determining a plurality of target decoding subsegments according to the plurality of decoding subsegments may specifically include, as shown in fig. 5:

and step S1031, respectively mapping each completely decoded sub-segment according to a preset sub-segment mapping rule to obtain a plurality of initial decoded sub-segments.

In the embodiment of the present disclosure, each completely decoded sub-segment may be mapped according to a preset sub-segment mapping rule, so as to obtain an initial decoded sub-segment corresponding to each completely decoded sub-segment, where the preset sub-segment mapping rule may be an inverse process of the sub-segment mapping rule corresponding to the encoding side.

Step S1032, mapping the bits in all the initial decoding subsegments according to a preset bit mapping rule, and obtaining the plurality of target decoding subsegments.

In the embodiment of the present disclosure, the bits in all the initial decoding subsections may be mapped according to a preset bit mapping rule, and a plurality of target decoding subsections are obtained based on the mapping result, where the preset bit mapping rule may be an inverse process of a bit mapping rule corresponding to the encoding side.

Optionally, in the embodiment of the present disclosure, the performing sub-segment transformation and sub-segment merging on the multiple target decoding sub-segments to obtain the decoding bit sequence corresponding to the sequence to be decoded may specifically include, as shown in fig. 6:

step S1041, selecting a target bit from the decoded bits included in the target decoded subsegments, and transforming the target bit into a final bit according to a preset subsegment transformation rule.

In the embodiment of the present disclosure, the predetermined sub-segment transformation rule may be a rule that is processed in an inverse manner with respect to the sub-segment transformation rule on the encoding side. Since the sub-segment to be encoded at the encoding side may include at least one of the frozen bit, the information bit, the constant 0 bit, the pure information bit, and the mixed bit, the sub-segment transformation rule at the encoding side may be used to define that the exclusive-or operation only involving the frozen bit results in the constant 0 bit, the exclusive-or operation only involving the information bit results in the pure information bit, and the exclusive-or operation involving the frozen bit and the information bit results in the mixed bit. Correspondingly, the preset sub-segment transformation rule of the decoding side in the decoding process can be inverse processing based on a constant 0 bit, can be inverse processing based on a pure information bit, and can also be inverse processing based on a mixed bit, specifically, the sub-segment transformation rule can be determined based on the constant 0 bit to be obtained by enabling a frozen bit to participate in an exclusive or operation, the sub-segment transformation rule can be determined based on the pure information bit to be obtained by enabling an information bit to participate in the exclusive or operation, the sub-segment transformation rule can be determined based on the mixed bit to be obtained by enabling a signal frozen bit and the information bit to participate in the exclusive or operation, the frozen bit is directly obtained by the frozen bit, and the information bit is directly obtained by the information bit.

Step S1042, based on the final decoding subsegment corresponding to the final bit, combining to obtain a decoding bit sequence corresponding to the sequence to be decoded.

In the embodiment of the present disclosure, the corresponding final decoding subsections can be obtained according to the final bit composition, and then the final decoding subsections are combined to obtain the decoding bit sequence corresponding to the sequence to be decoded.

Fig. 7 schematically illustrates a demodulation and decoding apparatus provided in an embodiment of the present disclosure, and as shown in fig. 7, the demodulation and decoding apparatus 50 may include:

a demodulating unit 501, configured to demodulate a modulation signal sent by a sending end through each modulation subchannel in response to receiving the modulation signal, and obtain a sequence to be decoded corresponding to the modulation signal;

a decoding unit 502, configured to decode, by using a plurality of sub-segment decoders, the plurality of sub-segments to be decoded obtained by dividing the sequence to be decoded, respectively, and obtain, based on a first preset threshold value that is set for each sub-segment to be decoded, a plurality of decoding sub-segments that correspond to the plurality of sub-segments to be decoded, respectively;

a determining unit 503, configured to determine a plurality of target decoding sub-segments according to the plurality of decoding sub-segments;

and a transform merging unit 504, configured to perform sub-segment transform and sub-segment merging on the multiple target decoding sub-segments, so as to obtain a decoding bit sequence corresponding to the sequence to be decoded.

To sum up, the demodulation and decoding apparatus provided in the embodiment of the present disclosure may demodulate a modulation signal in response to receiving the modulation signal sent by a sending end through each modulation sub-channel, to obtain a sequence to be decoded corresponding to the modulation signal, decode, by using a plurality of sub-segment decoders, a plurality of sub-segments to be decoded obtained by dividing the sequence to be decoded respectively, based on a first preset threshold value respectively set for each sub-segment to be decoded, to obtain a plurality of decoding sub-segments corresponding to the plurality of sub-segments to be decoded respectively, determine a plurality of target decoding sub-segments according to the plurality of decoding sub-segments, perform sub-segment transformation and sub-segment combination on the plurality of target decoding sub-segments, and obtain a decoding bit sequence corresponding to the sequence to be decoded. Therefore, the decoding time is shortened by decoding the plurality of subsegments to be decoded by the plurality of subsegment decoders respectively, the decoding complexity is reduced to a certain extent, the number of alternative paths can be correspondingly adjusted at any time according to a channel quality detection report of a receiving end based on the first preset threshold value respectively set for each subsegment to be decoded, the response speed is improved, and the method can be applied to receiving of a one-way transmission system.

Optionally, the decoding subsegments include a fully-decoded subsegment, and the decoding unit 502 is further configured to:

according to a first preset threshold value corresponding to the plurality of subsegments to be decoded respectively and a second preset threshold value set for an initial merging path, performing non-continuous deletion list non SCL decoding on the plurality of subsegments to be decoded by using the plurality of subsegment decoders to obtain a plurality of target merging paths; the initial merging path is a path obtained by merging after decoding according to each subsection to be decoded;

Optionally, the decoding unit 502 is further configured to:

the presetting step comprises the following steps:

Optionally, the decoding unit 502 is further configured to:

the target merging paths are verified based on a preset verification mode, and the target merging path which passes the verification and has the maximum probability is determined to be a complete decoding path;

Optionally, the determining unit 503 is further configured to:

Optionally, the transform combining unit 504 is further configured to:

The specific details of each module in the above demodulation and decoding apparatus have been described in detail in the corresponding demodulation and decoding method, and therefore are not described herein again.

It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.

Moreover, although the steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.

In an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.

As will be appreciated by one skilled in the art, aspects of the present disclosure may be embodied as a system, method or program product. Accordingly, various aspects of the present disclosure may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.) or an embodiment combining hardware and software aspects that may all generally be referred to herein as a "circuit," module "or" system.

An electronic device 600 according to this embodiment of the disclosure is described below with reference to fig. 8. The electronic device 600 shown in fig. 8 is only an example and should not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.

As shown in fig. 8, the electronic device 600 is embodied in the form of a general purpose computing device. The components of the electronic device 600 may include, but are not limited to: the at least one processing unit 610, the at least one memory unit 620, a bus 630 connecting different system components (including the memory unit 620 and the processing unit 610), and a display unit 640.

Wherein the storage unit stores program code that is executable by the processing unit 610 to cause the processing unit 610 to perform steps according to various exemplary embodiments of the present disclosure as described in the above section "exemplary methods" of this specification. For example, the processing unit 610 may execute step S101 shown in fig. 1, and in response to receiving a modulation signal sent by a sending end through each modulation subchannel, demodulate the modulation signal to obtain a sequence to be decoded corresponding to the modulation signal; step S102, a plurality of subsegments to be decoded obtained by dividing the sequence to be decoded are decoded by a plurality of subsegment decoders respectively, and a plurality of decoding subsegments corresponding to the subsegments to be decoded are obtained based on a first preset threshold value respectively set for each subsegment to be decoded; step S103, determining a plurality of target decoding subsegments according to the plurality of decoding subsegments; and step S104, performing sub-segment conversion and sub-segment combination on the target decoding sub-segments to obtain a decoding bit sequence corresponding to the sequence to be decoded.

The storage unit 620 may include readable media in the form of volatile memory units, such as a random access memory unit (RAM) 6201 and/or a cache memory unit 6202, and may further include a read-only memory unit (ROM) 6203.

The memory unit 620 may also include a program/utility 6204 having a set (at least one) of program modules 6205, such program modules 6205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may comprise an implementation of a network environment.

Bus 630 may be one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

The electronic device 600 may also communicate with one or more external devices 700 (e.g., keyboard, pointing device, bluetooth device, etc.), with one or more devices that enable a user to interact with the electronic device 600, and/or with any devices (e.g., router, modem, etc.) that enable the electronic device 600 to communicate with one or more other computing devices. Such communication may occur via an input/output (I/O) interface 650. Also, the electronic device 600 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network such as the Internet) via the network adapter 660. As shown, the network adapter 660 communicates with the other modules of the electronic device 600 over the bus 630. It should be understood that although not shown in the figures, other hardware and/or software modules may be used in conjunction with the electronic device 600, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.

Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, and may also be implemented by software in combination with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which may be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

In an exemplary embodiment of the present disclosure, there is also provided a computer readable storage medium having stored thereon a program product capable of implementing the above-described method of the present specification. In some possible embodiments, various aspects of the disclosure may also be implemented in the form of a program product comprising program code for causing a terminal device to perform the steps according to various exemplary embodiments of the disclosure described in the "exemplary methods" section above of this specification, when the program product is run on the terminal device.

The program product for implementing the above method according to the embodiments of the present disclosure may employ a portable compact disc read only memory (CD-ROM) and include program codes, and may be run on a terminal device, such as a personal computer. However, the program product of the present disclosure is not limited thereto, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

A computer readable signal medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations for the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., through the internet using an internet service provider).

Furthermore, the above-described figures are merely schematic illustrations of processes included in methods according to exemplary embodiments of the present disclosure, and are not intended to be limiting. It will be readily understood that the processes shown in the above figures are not intended to indicate or limit the chronological order of the processes. In addition, it is also readily understood that these processes may be performed, for example, synchronously or asynchronously in multiple modules.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A demodulation and decoding method, the method comprising:

2. The method according to claim 1, wherein said decoding subsegments comprise completely decoded subsegments, said decoding is performed on a plurality of subsegments to be decoded obtained by dividing said sequence to be decoded by using a plurality of subsegment decoders, and a plurality of decoding subsegments respectively corresponding to said plurality of subsegments to be decoded are obtained based on a first preset threshold value respectively set for each subsegment to be decoded, including:

according to a first preset threshold value corresponding to each of the plurality of subsections to be decoded and a second preset threshold value set for an initial merging path, performing non-continuous deletion list non SCL decoding on the plurality of subsections to be decoded by using the plurality of subsection decoders to obtain a plurality of target merging paths; the initial merging path is a path obtained by merging after each subsection to be decoded is decoded;

3. The method according to claim 2, wherein said obtaining a plurality of target merging paths by using the plurality of subsegment decoders to perform non-sequential deletion list nonSCL decoding on the plurality of subsegments to be decoded according to a first preset threshold corresponding to each of the plurality of subsegments to be decoded and a second preset threshold set for an initial merging path comprises:

the presetting step comprises the following steps:

when the current decoded bit is any bit except the tail bit in the subsegment to be decoded, aiming at each subsegment to be decoded, in the process of utilizing the corresponding subsegment decoder to continuously delete a list SCL (clock signal description) to decode the subsegment to be decoded, based on the bit probability of decoding each bit in the subsegment to be decoded, obtaining a second path probability set of a non-complete first decoding path corresponding to the subsegment to be decoded;

selecting non-complete alternative merging paths which accord with a preset freezing bit constraint condition and the number of which is less than or equal to a second preset threshold value from non-complete initial merging paths consisting of a plurality of non-complete first decoding paths based on the second path probability set;

4. The method according to claim 3, wherein said selecting, based on the second path probability set, a non-complete alternative merging path that meets a preset freezing bit constraint condition and has a number of paths less than or equal to the second preset threshold from non-complete initial merging paths composed of a plurality of non-complete first coding paths, comprises:

5. The method according to claim 3, wherein the selecting, from a plurality of non-complete second decoding paths obtained by dividing each of the non-complete alternative merging paths, an alternative decoding path whose path number is less than or equal to a first preset threshold corresponding to each of the subsegments to be decoded includes:

when the number of paths with different probability values in the non-complete second decoding paths corresponding to the subsegments to be decoded is less than or equal to a first preset threshold corresponding to the subsegments to be decoded, taking the paths with different probability values in the corresponding multiple non-complete second decoding paths as alternative decoding paths corresponding to the subsegments to be decoded;

6. The method according to claim 5, wherein said dividing each of said incomplete alternative merging paths into sub-segments to obtain a non-complete second decoding path corresponding to each of said sub-segments to be decoded comprises:

7. The method of claim 2, wherein said determining a plurality of said fully decoded subsegments based on said plurality of target merge paths comprises:

8. The method of claim 1, wherein said determining a plurality of target coding sub-segments based on said plurality of coding sub-segments comprises:

9. The method according to claim 1, wherein said performing sub-segment transform and sub-segment merging on said plurality of target decoding sub-segments to obtain a decoding bit sequence corresponding to said sequence to be decoded comprises:

10. The method according to any one of claims 1 to 9, wherein the first preset threshold is determined according to any one or more of modulation subchannel capacity, channel reliability, simulation effect, or communication network measurement result corresponding to the sub-segment to be decoded; the first preset threshold value comprises at least two different values.

11. A demodulation and decoding apparatus, characterized in that the apparatus comprises:

the demodulation unit is used for demodulating the modulation signals in response to the reception of the modulation signals sent by the sending end through each modulation sub-channel to obtain the sequences to be decoded corresponding to the modulation signals;

the decoding unit is used for decoding a plurality of subsegments to be decoded obtained by dividing the sequence to be decoded by utilizing a plurality of subsegment decoders respectively, and obtaining a plurality of decoding subsegments corresponding to the plurality of subsegments to be decoded respectively based on first preset thresholds respectively arranged for each subsegment to be decoded;

a determining unit, configured to determine a plurality of target decoding subsections according to the plurality of decoding subsections;

12. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the demodulation and decoding method according to any one of claims 1 to 10.

13. An electronic device, comprising:

a processor; and

a memory for storing executable instructions of the processor;

wherein the processor is configured to perform the demodulation decoding method of any one of claims 1-10 via execution of the executable instructions.