CN115987300A

CN115987300A - FPGA (field programmable Gate array) realization method for solving different lifting values of 64-parallelism LDPC (Low Density parity check) decoder

Info

Publication number: CN115987300A
Application number: CN202211606051.XA
Authority: CN
Inventors: 杜念通; 姚静; 尤喜成
Original assignee: Chengdu Chengfeng Technology Co ltd
Current assignee: Chengdu Chengfeng Technology Co ltd
Priority date: 2022-12-12
Filing date: 2022-12-12
Publication date: 2023-04-18

Abstract

The invention relates to a Field Programmable Gate Array (FPGA) realizing method for solving different lifting values by a 64-parallelism LDPC decoder, which comprises the following steps of: demodulating to obtain a group of variable node input matrix X in decoder _1*i The set of variable node input matrices represent i minimum load routing LLRs for the variable nodes; inputting the set of variable nodes into the matrix X by using the decoding parallelism P _1*i Equally dividing into Q parts to obtain the variable node remodeling matrix X of the group _{_new} When the input matrix X is _Q*P When the cyclic shift value CS corresponding to the variable node is greater than or less than P, the intermediate variable CS is judged _{_new} Whether it is equal to 0 to confirm the set of variable node reshaping matrices X _{_new} Shifting the number of rows; reshaping the matrix X from the set of variable nodes _{_new} Sequentially reshaping the variable node group by shifting the row number downwards to obtain a matrix X _{_new} The input data of (2) are subjected to data splicing. Therefore, the invention not only can reduce the parallelism degree of the decoding process, but also can save the hardware resource of the FPGA.

Description

FPGA (field programmable Gate array) realization method for solving different lifting values of 64-parallelism LDPC (Low Density parity check) decoder

Technical Field

The invention belongs to the field of wireless communication and digital signal processing, and relates to an FPGA (field programmable gate array) implementation method for decoding different lifting values by a 64-parallelism LDPC (Low Density parity check) decoder.

Background

The LDPC Code, that is, a Low Density Parity Check Code (LDPC), is a linear block Code with a sparse Check matrix proposed by Robert g.gallager in 1963, and has good performance approaching Shannon limit, low decoding complexity and flexible structure, and is a research hotspot in the field of channel coding in recent years. With the passage of time, LDPC codes have been widely used in digital Mobile communication systems in various scenes, become coding schemes in standards such as eee802.11ad, DVB-S2, and a middle-long code block coding scheme selected as a 5G standard enhanced Mobile BroadBand (enhanced Mobile BroadBand) service data channel is successfully distinguished from various coding schemes in 2016 (10) month.

The LDPC code has low decoding complexity, is very suitable for parallel decoding and supports high throughput transmission, and the properly designed LDPC code has a very low error code platform, so that the requirements on 5G high throughput transmission and reliability can be completely met. In 2001, lin Shu and the like combined with algebraic and geometric theories propose a brand-new structured LDPC code, and because a check matrix of the code has a quasi-cyclic structure, the code is named as a quasi-cyclic LDCP code (QC-LDPC Codes), and compared with an LDPC code with a random structure, the QC-LDPC code has more excellent performance in terms of hardware implementation and error code performance, and thus is greatly popular in practical application. In view of the excellent characteristics of QC-LDPC, NR LDPC codes also employ such a quasi-cyclic structure.

However, the 5G mentioned in the 3GPP protocol has more values of the boost value Zc, so when Zc is equal to the maximum value 384 specified in the protocol, the decoding using low parallelism is longer than the decoding using high parallelism, and the decoder using high parallelism also occupies too much hardware resources. How to realize less hardware resource occupation on the premise of ensuring the maximum throughput rate is a new research topic.

Disclosure of Invention

In view of this, the present invention provides an FPGA implementation method for decoding different lifting values by a 64-parallelism LDPC decoder, so as to solve the technical problem of how to achieve a small hardware resource occupation on the premise of ensuring a maximum throughput.

In order to achieve the above object, the present invention provides an FPGA implementation method for decoding different lifting values by a 64-parallelism LDPC decoder, wherein:

demodulating to obtain a set of variable node input moments in decoderArray X _1*i The set of variable node input matrices represent i least load routing LLRs for the variable nodes, where X _1*i ＝{A _1*0 ，A _1*1 ，A _1*2 ，……，A _1*(i-1) I = Zc, zc being the decoder de-boosting value;

inputting the set of variable nodes into the matrix X by using the decoding parallelism P _1*i Equally dividing into Q parts to obtain the variable node remodeling matrix X of the group _{_new} Wherein X is _{_new} ＝X _Q*P Said X is _Q*P The specific matrix of (a) is expressed as follows:

wherein Q = Zc/P, P =64, j ≦ 0,1,2 … … (P-1);

when the input matrix X is _Q*P When the cyclic shift value CS corresponding to the variable node is greater than or less than P, the intermediate variable CS is judged _{_new} Whether it is equal to 0 to confirm the set of variable node reshaping matrices X _{_new} Shifting the number of rows; wherein CS _{_new} = m% Q, CS being the input matrix X _Q*P M is the input matrix X when Zc is the maximum value _Q*P The cyclic shift value corresponding to the variable node of (a);

reshaping the matrix X from the set of variable nodes _{_new} Shifting down the number of rows to reshape the set of variable nodes into a matrix X _{_new} The input data of (2) is subjected to data splicing.

Preferably, when the input matrix X is _Q*P The cyclic shift value CS corresponding to the variable node of (1) is greater than P and CS _{_new} When not equal to 0, the set of variable nodes reshapes the matrix X _{_new} Line 0 to (Q-CS) _{_new} ) The row is shifted to the right by K bits, and the variable nodes of the group reshape the matrix X _{_new} Q-CS _{_new} Right-shifting (K-1) bits from row Q to row Q; when the input matrix X is _Q*P The cyclic shift value CS corresponding to the variable node of (1) is greater than P and CS _{_new} When equal to 0, the set of variable nodes reshapes the matrix X _{_new} Shift right by K bits.

Preferably, whenThe input matrix X _Q*P The cyclic shift value CS corresponding to the variable node of (1) is less than P and CS _{_new} When not equal to 0, the set of variable nodes reshapes the matrix X _{_new} Line 0 to (Q-CS) _{_new} ) The row is shifted to the right by M bits, and the set of variable nodes reshapes a matrix X _{_new} Q-CS _{_new} Line to line Q is right shifted by (M + 1) bits; when the input matrix X is _Q*P The cyclic shift value CS corresponding to the variable node of (1) is less than P and CS _{_new} When equal to 0, the set of variable nodes reshapes the matrix X _{_new} Right shifted by (m/Q) bits.

Further preferably, the calculation formula of K is specifically: k = (Zc + CS) _{_new} –m)/Q。

Further preferably, the calculation formula of M is specifically: m = (M-CS) _{_new} )/Q。

Further preferably, the decoder de-boost value Zc ≦ 384.

The invention has the beneficial effects that: the invention meets the requirement of high throughput decoding by adopting a mode of remolding the input matrix of the decoder, reduces the parallelism of the decoding process and saves the hardware resource of the FPGA.

Drawings

In order to make the object, technical scheme and beneficial effect of the invention more clear, the invention provides the following drawings for explanation:

FIG. 1 is a basic flow diagram of a method implemented in an embodiment of the invention;

fig. 2 is a graph showing FPGA resource occupation by cyclic shift directly after grouping according to an embodiment of the present invention.

Detailed Description

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

As mentioned in the 3GPP protocol, the whole coding/decoding core includes: base Graph (BG), lifting value (ZC), and cyclic shift value (CS). BG is a prerequisite for LDPC code PCM (Parity-Check matrix) design and also determines the macroscopic characteristics and overall performance of LDPC codes. BG has two cases, which can be represented by H matrix in general, and the H matrix is divided into A, B, C, D, 0 and I, wherein B is fixed to 4 × 4,0 to represent zero matrix, that is, matrix with all elements being 0, and I represents identity matrix, that is, matrix with main diagonal being 1. The H matrix is shown in table 1 and table 2 according to different base maps.

	22	4	42
				4	A	B	0
42	C	D	I

Table 1 base graph (46 x 68)

	10	4	38
				4	A	B	0
38	C	D	I

Table 2 base map (42 x 52)

The de-lifting value Zc of the LDPC decoder is obtained according to the coding mode. QC-LDPC is mainly embodied in the decoding process, the unit matrix of ZC Zc is used for filling the position of each point of a base graph, the cyclic shift of the unit matrix is completed according to different cyclic shift values (CS), and then the shifted unit matrix is multiplied by information, so that the function of information exchange is achieved. The essence of the LDPC decoding process is the process of information exchange between variable nodes (where the codes to be corrected are located) and check nodes (the number of layers where the codes to be corrected are located). However, there are LDPC decoders with parallelism of 128 on the market at present, and this study selects 64 as the decoding parallelism, which can better save hardware resources on the one hand, and on the other hand, it is very easy to implement cyclic shift by using Banyan network when the parallelism is 64. Therefore, the present invention provides an FPGA implementation method for decoding different lifting values by a 64-parallelism LDPC decoder, as shown in fig. 1, the specific steps are described as follows:

demodulating to obtain a group of variable node input matrix X in decoder _1*i The set of variable node input matrices represent i least load routing LLRs for the variable nodes, where X _1*i ＝{A _1*0 ，A _1*1 ，A _1*2 ，……，A _1*i I = Zc, zc being the decoder de-boost value. The LLR is obtained by demodulation of the message from the modulated signal carrying the messageAnd (6) carrying out the process. Commonly used demodulation methods include BPSQ, 16QAM, 64QAM and 256QAM, and the specific demodulation method is selected according to actual situations. As shown in table 3, the lifting value of Zc is more than that of 5G mentioned in the 3gpp TS 38.212v16.1.0 protocol, so that when Zc is equal to the maximum value 384 specified in the protocol, decoding with 64 parallelism is longer than that of a decoder with 384 parallelism.

TABLE 3 lifting value evaluation condition table of Zc

wherein Q = Zc/P, P =64, j ≦ is 0,1,2 … … (P-1);

when the input matrix X is _Q*P When the cyclic shift value CS corresponding to the variable node is greater than or less than P, the intermediate variable CS is judged _{_new} Whether it is equal to 0 to confirm that the set of variable nodal remodeling matrices X _{_new} Shifting the number of rows; wherein CS _{_new} = m% Q, CS being the input matrix X _Q*P The cyclic shift value corresponding to the variable node of (c), m is the input matrix A when Zc is the maximum value _Q*P The cyclic shift value corresponding to the variable node of (a); the decoder de-boosting maximum value Zc to 384;

reshaping the matrix X from the set of variable nodes _{_new} Shifting down the number of rows to reshape the set of variable nodes into a matrix X _{_new} The input data of (2) are subjected to data splicing. In the embodiment of the invention, the data can be moved downwards in the algorithm principle, but the situation of downward movement does not occur in the actual FPGA operation, so that the downward movement can be realizedThe data splicing is realized through late data splicing because a special grouping mode is adopted when the 384 is split into 64, and the data needs to be spliced according to the split array sequence. For example, assuming the first three sets of data are shifted to the right by K bits and the second three sets of data are shifted to the right by K-1 bits, the data concatenation order is the first data of group 4, the first data of group 5, the first data of group 6, the first data of group 1, the first data of group 2, the first data of group 3, the second data of group 4.

When the input matrix X is _Q*P The cyclic shift value CS corresponding to the variable node of (1) is greater than P and CS _{_new} When not equal to 0, the set of variable nodes reshapes the matrix X _{_new} Line 0 to (Q-CS) _{_new} ) The row is shifted to the right by K bits, and the group of variable nodes reshapes a matrix X _{_new} Q-CS _{_new} Right-shifting (K-1) bits from row Q to row Q; when the input matrix X is _Q*P The cyclic shift value CS corresponding to the variable node of (1) is greater than P and CS _{_new} When equal to 0, the set of variable nodes reshapes the matrix X _{_new} Shift right by K. The calculation formula of K is specifically as follows: k = (Zc + CS) _{_new} –m)/Q。

When the input matrix X is _Q*P The cyclic shift value CS corresponding to the variable node of (1) is less than P and CS _{_new} When not equal to 0, the set of variable nodes reshapes the matrix X _{_new} Line 0 to (Q-CS) _{_new} ) The row is shifted to the right by M bits, and the variable nodes of the group reshape the matrix X _{_new} Q-CS _{_new} Line to line Q is right shifted by (M + 1) bits; when the input matrix X is _Q*P The cyclic shift value CS corresponding to the variable node of (1) is less than P and CS _{_new} When equal to 0, the set of variable nodes reshapes the matrix X _{_new} Right shifted by (m/Q) bits. The calculation formula of M is specifically as follows: m = (M-CS) _{_new} )/Q。

For a better understanding of the embodiments of the present invention, the following are specified:

firstly, the FPGA implementation needs to be explained, namely written Verilog codes are converted into hardware resources with fixed sizes, so that 64 parallelism degrees used in decoding mean that 64 LLRs (log-likelihood ratio) contained in each variable node can be processed at one time, wherein the LLRs are represented as probability values of 0 or 1; however, the number of LLRs for each variable node is the same as Zc, and the cyclic shift values (CS) corresponding to different zcs are different, so the purpose of this embodiment is how to implement data processing of 384 LLRs when the resource size is fixed to 64, and it should be noted that the number of LLRs corresponding to each variable node after demodulation is determined by the code lifting value, and the decoded lifting value is fixed to 64.

Aiming at the decoding process of the QC-LDPC code division layer minimum sum, the information transmission of check nodes and variable nodes is completed through matrix circulation in the decoding process. When the lifting value Zc is equal to 384, it is equivalent to fill 384 × 384 as the unit matrix size to the position where the variable node of the base matrix is 1. The specific implementation is illustrated by the basic figure 1 under the standard protocol of 5G mobile communication.

(1) Inputting parameters:

suppose the demodulated LLR is an ordered array, and let the information contained in the 1 st variable node be X _1*384 Contains 384 LLRs, and then: x _1*384 ＝[0 1 2 3 4……383]。

Since the lifting value of the 3gpp TS 38.212v16.1.0 protocol specifies that the lifting value during encoding should be the same as the lifting value during decoding, but the size of the FPGA in the present technical solution is only 64, the actual encoding lifting value and the decoding lifting value are different, assuming that the lifting value Zc _ encode =384 during encoding and the lifting value Zc _ decode =64 during decoding;

assuming that a cyclic shift value corresponding to the first variable node is m;

(2) in the technical scheme, the decoding parallelism P is 64, that is, 64 LLRs can be processed at most once, so that the LLRs of the variable node are averagely divided into 6 parts (that is, Q is equal to 6), that is, the variable node is reshaped into the following matrix X _Q*P ＝X _6*64 ：

Wherein, the calculation formula of Q is as follows: q = Zc/P, P ≦ 64

(3) Assuming that the cyclic shift number (CS) is m when Zc =384

The relevant parameters are calculated as follows:

K＝(384+n-m)/6，

M＝(CS-CS _{_new} )/6，

CS _{_new} ＝m％6；

the subdivision is discussed below:

when CS is greater than 64 and CS _{_new} When not equal to 0, then X _{_new} Line 0 to line 6 minus CS _{_new} Moving by K, X to the right _{_new} 6 th to CS _{_new} The rows are shifted to the right by K-1 bits through row 6.

When CS is greater than 64 and CS _{_new} When 0 is equal, then X _{_new} Shift right by K bits.

When CS is less than or equal to 64 and n is not equal to 0, then X _{_new} Line 0 to line 6 minus CS _{_new} By shifting the rows to the right by M bits, X _{_new} 6 th to CS _{_new} The rows are shifted to the right by- (M + 1) bits from row 6, i.e., by M +1 bits to the left.

When CS is less than 64 and n is equal to 0, then A is shifted to the right by-CS divided by 6 bits, i.e., CS divided by 6 bits is shifted to the left.

(3) Only 64 LLRs are processed each time in the FPGA realization process, so that data splicing is carried out after all 6 groups of data are circularly shifted, and the splicing sequence is determined by the number of shift lines downwards, so that data with 64-parallelism and 384-parallelism can be realized.

(4) And transmitting the shifted data to the next module (namely, a check node updating module), finishing the addition and subtraction function, and finishing data splicing after the 6 groups of data are processed.

As shown in fig. 2, the LUT (i.e., look-up table) in the FPGA is essentially a RAM in which data is stored in advance. When a signal is input, look-up table is carried out according to the address pointed by the signal, and the content corresponding to the address is found out for output. The occupied FPGA resource before grouping is 23314, and the occupied FPGA resource after grouping is reduced to 1464 by the implementation method of the embodiment of the invention; similarly, the occupied FPGA resource before FF (trigger) grouping in the FPGA is 7430, and the occupied FPGA resource after the grouping by the implementation method of the embodiment of the invention is reduced to 401.

In summary, the embodiment of the present invention completes the decoding requirement of the promotion value 384 by using the decoder with the coding promotion value 64, reduces the parallelism of the decoding process, and saves the hardware resources of the FPGA; meanwhile, the method can be analogized to 64 solution 384, and can analogize and realize the LLR corresponding to any lifting value Zc specified by the 64 solution 3GPP TS 38.212V16.1.0 protocol.

Finally, it is noted that the above-mentioned preferred embodiments illustrate rather than limit the invention, and that, although the invention has been described in detail with reference to the above-mentioned preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention as defined by the appended claims.

Claims

1. A FPGA realization method for solving different lifting values by a 64-parallelism LDPC decoder is characterized by comprising the following steps:

demodulating to obtain a group of variable node input matrix X in decoder _1*i The set of variable node input matrices represent i least load routing LLRs for the variable nodes, where X _1*i ＝{A _1*0 ，A _1*1 ，A _1*2 ，……，A _1*(i-1) I = Zc, zc being the decoder de-boost value;

wherein Q = Zc/P, P =64, j ≦ 0,1,2 … … (P-1);

2. The FPGA realization method of 64-parallelism LDPC decoder de-lifting values according to claim 1, characterized in that: when the input matrix X is _Q*P The cyclic shift value CS corresponding to the variable node of (1) is greater than P and CS _{_new} When not equal to 0, the set of variable nodes reshapes the matrix X _{_new} Line 0 to (Q-CS) _{_new} ) The row is shifted to the right by K bits, and the group of variable nodes reshapes a matrix X _{_new} Q-CS _{_new} Line to line Q is right shifted by (K-1) bits; when the input matrix X is _Q*P The cyclic shift value CS corresponding to the variable node of (1) is greater than P and CS _{_new} When equal to 0, the set of variable nodes reshapes the matrix X _{_new} Shift right by K.

3. The FPGA realization method of 64-parallelism LDPC decoder de-lifting values according to claim 1, characterized in that: when the input matrix X _Q*P The cyclic shift value CS corresponding to the variable node of (1) is less than P and CS _{_new} When not equal to 0, the set of variable nodes reshapes the matrix X _{_new} Line 0 to (Q-CS) _{_new} ) The row is shifted to the right by M bits, and the set of variable nodes reshapes a matrix X _{_new} Q-CS _{_new} Line to line Q is right shifted by (M + 1) bits; when the input matrix X is _Q*P The cyclic shift value CS corresponding to the variable node of (1) is less than P and CS _{_new} When equal to 0, the set of variable nodes reshapes the matrix X _{_new} Right shifted by (m/Q) bits.

4. The FPGA implementation method of the low-parallelism high-throughput LDPC decoder according to claim 2, wherein: the calculation formula of K is specifically as follows: k = (Zc + CS) _{_new} –m)/Q。

5. The FPGA implementation method of the de-lifting value of the 64-parallelism LDPC decoder according to claim 3, wherein: the calculation formula of M is specifically as follows: m = (M-CS) _{_new} )/Q。

6. The FPGA implementation method of the de-lifting value of the 64-parallelism LDPC decoder according to claim 3, wherein: the decoder solution lifting value Zc ≦ 384.