CN115987218A

CN115987218A - Oscillator circuit

Info

Publication number: CN115987218A
Application number: CN202211650940.6A
Authority: CN
Inventors: 柴军营; 杨书山
Original assignee: Beijing Zesheng Technology Co ltd
Current assignee: Suzhou Zesheng Microelectronics Co ltd
Priority date: 2022-12-21
Filing date: 2022-12-21
Publication date: 2023-04-18

Abstract

The application provides an oscillator circuit, including: the temperature drift compensation device comprises a first current module, a second current module, a temperature drift compensation module, a first comparison module and a second comparison module. The first sub-current module and the second sub-current module alternately provide a first preset current to generate a first voltage of the first sub-current module and a second voltage of the second sub-current module. The third sub-current module and the fourth sub-current module alternately provide a second preset current to generate a third voltage and a fourth voltage. The first predetermined current is 2 times the second predetermined current. After receiving the start signal, the temperature drift cancellation module provides current for the first resistor and the first capacitor through the first current source to obtain a fifth voltage. Through the comparison of the first voltage, the second voltage, the third voltage and the fourth voltage with the fifth voltage, the circuit is pressurized within a period of time by alternately using 2 times of current, the effect that the follow-up time exceeding due to the time delay of the comparator reaches the effect of no time delay is made up, and a stable clock signal is output.

Description

Oscillator circuit

Technical Field

The invention relates to the technical field of integrated circuits, in particular to an oscillator circuit.

Background

The oscillator circuit is one of the core circuits commonly used in analog and digital chips, and its main function is to provide a clock signal. In oscillator circuits, RC relaxation oscillators are a common structure in low power applications.

A conventional RC relaxation oscillator generally includes a first current source connected to a resistor, a second current source connected to a capacitor, a comparator, and an RS flip-flop. The voltage comparison result can be obtained by comparing the voltage across the resistor and the capacitor by a comparator. Based on the voltage comparison result, the RS trigger controls the capacitor to perform charging and discharging operations, and changes the voltage at two ends of the capacitor, so that the comparator determines a new voltage comparison result based on the voltages at two ends of the resistor and the capacitor again, and further generates a clock signal.

However, the comparator in the conventional RC relaxation oscillator is affected by the manufacturing process, and has a certain delay, so that the stability of the output frequency of the clock signal generated by the conventional RC relaxation oscillator is poor.

Disclosure of Invention

In order to overcome the technical problems in the prior art, an oscillator circuit capable of enabling the output frequency to be stable is provided.

The present application provides an oscillator circuit comprising: the temperature drift compensation circuit comprises a first current module, a second current module, a temperature drift compensation module, a first comparison module and a second comparison module; the first current module comprises a first sub-current module and a second sub-current module; the second current module comprises a third sub-current module and a fourth sub-current module; the currents provided by the first sub-current module, the second sub-current module, the third sub-current module and the fourth sub-current module are the same; the first comparison module and the second comparison module are the same; the temperature drift counteracting module comprises a first current source, a first resistor and a first capacitor, one end of the first current source is connected with the power-on starting module, one ends of the first resistor and the first capacitor are both connected with the other end of the first current source, the other ends of the first resistor and the first capacitor are grounded, and the first end and the second end of the first comparing module and the first end and the second end of the second comparing module are respectively connected with the other end of the first current source; the resistance value of the first resistor is kept in a constant range at different temperatures;

the first sub-current module and the second sub-current module are used for alternately providing a first preset current and generating a first voltage of the first sub-current module and a second voltage of the second sub-current module;

the third sub-current module and the fourth sub-current module are used for alternately providing a second preset current to generate a third voltage and a fourth voltage; the first preset current is 2 times of the second preset current;

the temperature drift counteracting module is used for providing current for the first resistor and the first capacitor through the first current source after receiving the starting signal to obtain fifth voltage;

when the starting signal is received and the first sub-current module stops providing current:

the second comparison module is used for comparing the third voltage with the fifth voltage, controlling the second sub-current module to provide a second preset current after the third voltage is greater than the fifth voltage and the target delay time elapses, and controlling the third sub-current module to stop providing the current;

the first comparison module is used for comparing the second voltage with the fifth voltage and outputting a first clock signal; and controlling the second sub-current module to stop providing current after the fifth voltage is greater than the second voltage and the target delay time passes;

in case the second sub-current module stops providing current:

the second comparison module is further used for comparing the fourth voltage with the fifth voltage, controlling the first sub-current module to provide a second preset current and controlling the fourth sub-current module to stop providing current after the fourth voltage is greater than the fifth voltage and the target delay time elapses;

the first comparison module is also used for comparing the first voltage with the fifth voltage and outputting a second clock signal; and controlling the first sub-current module to stop providing current after the fifth voltage is greater than the first voltage and the target delay time elapses; the first clock signal and the second clock signal are opposite.

In one embodiment, the first ends of the first sub-current module, the second sub-current module, the third sub-current module and the fourth sub-current module are connected with the power-on starting module; the second ends of the first sub-current module, the second sub-current module, the third sub-current module and the fourth sub-current module are all grounded;

the other end of the first current source is connected with the first end of the first comparison module; the third end of the second sub-current module is connected with the second end of the first comparison module; the third end of the third sub-current module is connected with the first end of the second comparison module; the other end of the first current source is connected with the second end of the second comparison module;

the third end of the first sub-current module is connected with the first end of the first comparison module; the other end of the first current source is connected with the second end of the first comparison module; the other end of the first current source is connected with the first end of the second comparison module; and the third end of the fourth sub-current module is connected with the second end of the second comparison module.

In one embodiment, upon receiving the start signal and the first sub-current module stopping providing current:

the other end of the first current source is conducted with the first end of the first comparison module;

the third end of the second sub-current module is communicated with the second end of the first comparison module;

the third end of the third sub-current module is conducted with the first end of the second comparison module;

the other end of the first current source is conducted with the second end of the second comparison module;

in case the second sub-current module stops providing current:

the third end of the first sub-current module is communicated with the first end of the first comparison module;

the other end of the first current source is conducted with the second end of the first comparison module;

the other end of the first current source is conducted with the first end of the second comparison module;

and the third end of the fourth sub-current module is conducted with the second end of the second comparison module.

In one embodiment, the second sub-current module comprises a second current source, a third current source and a second capacitor; the third sub-current module comprises a fourth current source and a third capacitor; the currents provided by the second current source, the third current source and the fourth current source are the same;

when receiving the starting signal and the first sub-current module stops providing current:

the second sub-current module is used for charging the second capacitor through a second current source and a third current source;

the third sub-current module is used for charging a third capacitor through a fourth current source after receiving the starting signal;

the second comparison module is used for comparing a third voltage at two ends of the third capacitor with a fifth voltage at two ends of the first capacitor, controlling the second current source to stop supplying current to the second capacitor and controlling the fourth current source to stop charging the third capacitor after the third voltage is greater than the fifth voltage and a target delay time elapses;

and the first comparison module is used for comparing the fifth voltage and the second voltage at the two ends of the first capacitor, outputting a clock signal and controlling the third current source to stop charging the second capacitor after the fifth voltage is greater than the second voltage and target delay time elapses.

In one embodiment, the second sub-current module further comprises a first switch, a second switch, and a third switch; one ends of a second current source and a third current source are connected with the power-on starting module, the other end of the second current source is connected with one end of the first switch, the other end of the third current source and a first common end of the other end of the first switch are respectively connected with one end of the second switch and one end of the third switch, the other end of the second switch is connected with one end of the second capacitor, and the other end of the second capacitor and the other end of the third switch are grounded; the first common end is connected with the second end of the first comparison module, the first end of the first comparison module and the second end of the second comparison module are both connected with the other end of the first current source, and the first end of the second comparison module is connected with the third end of the third sub-current module;

the second comparison module is used for controlling the first switch to be switched off after the third voltage is greater than the fifth voltage and the target delay time elapses, so that the second current source stops supplying current to the second capacitor;

and the first comparison module is used for comparing a fifth voltage and a second voltage at two ends of the first capacitor, outputting a clock signal, controlling the second switch to be switched off and controlling the third switch to be switched on after the fifth voltage is greater than the second voltage and a target delay time elapses, so that the third current source stops charging the second capacitor and discharges the second capacitor.

In one embodiment, the third sub-current module further comprises a first switch, a third switch, and a fourth switch; the third capacitor comprises a first sub capacitor and a second sub capacitor; one end of a fourth current source is connected with the power-on starting module, the other end of the fourth current source is connected with one end of the first switch, a second common end of the first sub-capacitor and the second sub-capacitor is connected with the other end of the first switch, the other end of the first sub-capacitor is respectively connected with a first end of the second comparing module and one end of the third switch, the other end of the third switch is connected with the other end of the first current source, the other end of the second sub-capacitor and one end of the fourth switch are grounded, and the other end of the fourth switch is connected with the second common end;

and the second comparison module is used for controlling the first switch to be switched off and controlling the fourth switch and the third switch to be switched on after the third voltage is greater than the fifth voltage and the target delay time elapses, so that the fourth current source stops charging the second sub-capacitor, and the voltage at two ends of the first sub-capacitor is controlled to be equal to the fifth voltage.

In one embodiment, the first sub-current module comprises a fifth current source, a sixth current source and a fourth capacitor; the fourth sub-current module comprises a seventh current source and a fifth capacitor; the current provided by the fifth current source, the sixth current source and the seventh current source is the same as the current provided by the second current source, the third current source and the fourth current source;

in case the second sub-current module stops providing current:

the first sub-current module is used for charging the fourth capacitor through a fifth current source and a sixth current source;

the fourth sub-current module is used for charging the fifth capacitor through a seventh current source;

the second comparison module is used for comparing a fourth voltage and a fifth voltage at two ends of the seventh current source, controlling the sixth current source to stop supplying current to the fourth capacitor and controlling the fourth sub-current module to stop supplying current to the fifth capacitor after the fourth voltage is greater than the fifth voltage and a target delay time elapses;

the first comparison module is used for comparing the first voltage and the fifth voltage at two ends of the fourth capacitor and outputting a second clock signal; and controlling the fifth current source to stop supplying current to the fourth capacitor after the fifth voltage is greater than the first voltage and the target delay time elapses.

In one embodiment, the first sub-current module further includes a fourth switch, a third switch and a second switch, one end of a fifth current source and one end of a sixth current source are connected to the power-on starting module, the other end of the sixth current source is connected to one end of the fourth switch, the other end of the fourth switch and a third common end of the other end of the fifth current source are connected to one end of the third switch, the other end of the third switch is respectively connected to one end of a fourth capacitor and one end of the second switch, and the other end of the fourth capacitor and the other end of the second switch are grounded; the third common end is connected with the first end of the first comparison module; the second end of the first comparison module and the first end of the second comparison module are connected with the other end of the first current source; the second end of the second comparison module is connected with the third end of the fourth sub-current module;

the second comparison module is used for comparing a fourth voltage at two ends of the fifth capacitor with a fifth voltage at two ends of the first capacitor, and controlling the fourth switch to be switched on and switched off after the fourth voltage is greater than the fifth voltage and a target delay time is passed, so that the sixth current source stops charging the fourth capacitor;

the first comparison module is used for comparing a first voltage and a fifth voltage at two ends of the fourth capacitor and outputting a second clock signal; and after the fifth voltage is greater than the first voltage and the target delay time elapses, the third switch is controlled to be opened so that the fifth current source stops charging the fourth capacitor, and the second switch is controlled to be closed so that the fourth capacitor is discharged.

In one embodiment, the fourth sub-current module further comprises: the fifth capacitor comprises a third sub capacitor and a fourth sub capacitor; one end of a seventh current source is connected with the power-on starting module, the other end of the seventh current source is connected with one end of a fourth switch, one end of a third sub-capacitor, one end of a fourth sub-capacitor and one end of a first switch are all connected with the other end of the fourth switch, the other end of the first switch and the other end of the third sub-capacitor are grounded, the other end of the fourth sub-capacitor is connected with one end of a second switch, the other end of the second switch is connected with the other end of the first current source, the other end of the fourth sub-capacitor is connected with the second end of a second comparison module, and the first end of the second comparison module is connected with the other end of the first current source;

in case the second sub-current module stops providing current:

and the second comparison module is used for comparing a fourth voltage and a fifth voltage at two ends of the fourth sub-capacitor, controlling the fourth switch to be switched off after the fourth voltage is greater than the fifth voltage and a target delay time elapses, so that the seventh current source stops charging the third sub-capacitor, and switching on the second switch and the first switch, so that the voltages at two ends of the fourth sub-capacitor are equal to the fifth voltage.

In one embodiment, the first comparing module includes: the two third switches, the two second switches, the first comparator, the first inverter and the first RS trigger;

a second comparison module comprising: the two third switches, the two second switches, the second comparator, the second inverter and the second RS trigger;

the oscillator circuit further comprises a switch control unit; the switch controller comprises a first switch control unit and a second switch control unit;

one end of a third switch and one end of a second switch in the first comparison module are respectively connected with the first end of a first comparator; the other end of the third switch is connected with the other end of the first current source; the other end of the second switch is connected with the first public end;

one end of the other third switch and one end of the other second switch are respectively connected with the second end of the first comparator; the other end of the other third switch is connected with the third common end, and the other end of the other second switch is connected with the other end of the first current source;

the third end of the first comparator is respectively connected with the input end of the first inverter; the third end of the first comparator and the output end of the first phase inverter are respectively connected with the first RS trigger, the first output end of the first RS trigger is respectively connected with the second switches and the first input end of the first switch control unit, and the second output end of the first RS trigger is respectively connected with the third switches and the first input end of the second switch control unit;

one end of a third switch and one end of a second switch in the second comparison module are respectively connected with the first end of a second comparator; the other end of the third switch is connected with the other end of the fourth sub-capacitor, and the other end of the second switch is connected with the other end of the first current source;

one end of the other third switch and one end of the other second switch are respectively connected with the second end of the second comparator; the other end of the other third switch is connected with the other end of the first current source, and the other end of the other second switch is connected with the other end of the first sub-capacitor;

the third end of the second comparator is respectively connected with the input end of the second inverter; a third end of the second comparator and an output end of the second inverter are respectively connected with the second RS trigger, a first output end of the second RS trigger is connected with a second input end of the first switch control unit, and a second output end of the second RS trigger is connected with a second input end of the second switch control unit;

the third end of the first inverter is used for outputting a clock signal;

the first switch control unit is used for controlling the disconnection or the conduction of each first switch according to the output signal of the first output end of the first RS trigger and the output signal of the second output end of the second RS trigger;

the second switch control unit is used for controlling the disconnection or the connection of each second switch according to the output signal of the second output end of the first RS trigger and the output signal of the first output end of the second RS trigger;

the first RS trigger is used for transmitting an output signal of a first output end of the first RS trigger to each second switch so as to enable the second switches to be disconnected or connected; and transmitting an output signal of the second output terminal of the first RS flip-flop to each third switch to turn off or on the third switch.

In one embodiment, the first RS flip-flop and the second RS flip-flop are and gate flip-flops.

In one embodiment, the first resistor includes a first sub-resistor and a second sub-resistor, one end of the first sub-resistor is connected to the other end of the first signal source, the other end of the first sub-resistor is connected to one end of the second sub-resistor, the other end of the second sub-resistor is grounded, the first sub-resistor is a positive temperature coefficient resistor, and the second sub-resistor is a negative temperature coefficient resistor.

As can be seen from the above technical solutions, the present application provides an oscillator circuit, including: the temperature drift compensation device comprises a first current module, a second current module, a temperature drift compensation module, a first comparison module and a second comparison module. The first sub-current module and the second sub-current module are used for alternately providing a first preset current to generate a first voltage of the first sub-current module and a second voltage of the second sub-current module. And the third sub-current module and the fourth sub-current module are used for alternately providing a second preset current to generate a third voltage and a fourth voltage. And the first preset current is 2 times of the second preset current. The temperature drift cancellation module is used for providing current for the first resistor and the first capacitor through the first current source after receiving the starting signal, and obtaining a fifth voltage. At this time, when the start signal is received and the first sub-current module stops providing the current, the second comparison module may compare the third voltage with the fifth voltage, and control the second sub-current module to provide the second preset current and control the third sub-current module to stop providing the current after the third voltage is greater than the fifth voltage and the target delay time elapses. In case the second sub-current module stops providing current: the second comparison module is further used for comparing the fourth voltage with the fifth voltage, controlling the first sub-current module to provide a second preset current and controlling the fourth sub-current module to stop providing current after the fourth voltage is greater than the fifth voltage and the target delay time elapses; the first comparison module is also used for comparing the first voltage with the fifth voltage and outputting a second clock signal; and controlling the first sub-current module to stop providing current after the fifth voltage is greater than the first voltage and the target delay time elapses; the first clock signal and the second clock signal are opposite. Obviously, in different modes, the circuit can be pressurized by adopting 2 times of current, so that the time exceeding due to the time delay of the comparator is compensated, the effect of no time delay is further achieved, and the output clock signal is stable.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic diagram of a conventional oscillator circuit;

FIG. 2 is a schematic diagram of an oscillator circuit according to a first embodiment of the present application;

FIG. 3 is a schematic diagram of an oscillator circuit according to a second embodiment of the present application;

FIG. 4 is a schematic diagram of an oscillator circuit according to a third embodiment of the present application;

FIG. 5 is a schematic diagram of an oscillator circuit according to a fourth embodiment of the present application;

FIG. 6 is a schematic diagram of an oscillator circuit according to a fifth embodiment of the present application;

FIG. 7 is a schematic diagram of an oscillator circuit in a sixth embodiment of the present application;

FIG. 8 is a schematic diagram of an oscillator circuit in a seventh embodiment of the present application;

fig. 9 is a simulation diagram of an oscillator circuit of the present application.

Reference numerals:

10-an oscillator circuit; 100-a first current module; 110-a first sub-current module; 120-a second sub-current module;

111-a fifth current source; 112-a sixth current source; 113-a fourth capacitance; 114-a fourth switch; 115-a third switch; 116-a second switch;

121-a second current source; 122-a third current source; 123-a second capacitance; 124-a first switch; 200-a second current module; 210-a third sub-current module; 220-a fourth sub-current module;

211-a fourth current source; 212-a third capacitance; 2121 — a first sub-capacitance; 2122-a second sub-capacitor;

221-a seventh current source; 222-a fifth capacitance; 2221 — third sub-capacitance; 2222 — a fourth sub-capacitance;

300-temperature drift counteracting module; 310-a first current source; 320-a first resistance; 330-a first capacitance;

321-a first sub-resistor; 322-a second sub-resistance;

400-a first comparison module; 410-a first comparator; 420-a first inverter; 430 a first RS flip-flop;

500-a second comparison module; 510-a second comparator; 520-a second inverter; 530-a second RS flip-flop;

600-power-on start module; 700-a switch control unit; 710-a first switch control unit; 720-second switch control unit.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The numbering of the components as such, for example "first", "second", etc., in this application is used solely to distinguish between the objects depicted and not to imply any order or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings). In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present application and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be considered as limiting the present application.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature "under," "beneath," and "under" a second feature may be directly under or obliquely under the second feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

An OSC (oscillator) circuit is one of the core circuits commonly used in analog and digital chips to provide a basic clock source. Conventional RC relaxation oscillators are one structure commonly used in low power applications. A conventional RC relaxation oscillator circuit is shown in fig. 1 and generally comprises a first current source I1 connected to a resistor R, a second current source I2 connected to a capacitor C, a Comparator (Comparator) and an RS flip-flop. The voltage V2 at the two ends of the resistor and the voltage V1 at the two ends of the capacitor can be compared through the comparator to obtain a voltage comparison result. Based on the voltage comparison result, the RS trigger controls the capacitor to carry out charging and discharging operations, and changes the voltage at two ends of the capacitor, so that the comparator determines a new voltage comparison result based on the voltage at two ends of the resistor and the capacitor again, and then generates a clock signal.

Based on this, this application embodiment provides an oscillator circuit. The first sub-current module and the second sub-current module are used for alternately providing a first preset current to generate a first voltage of the first sub-current module and a second voltage of the second sub-current module. And the third sub-current module and the fourth sub-current module are used for alternately providing a second preset current to generate a third voltage and a fourth voltage. And the first preset current is 2 times of the second preset current. The temperature drift cancellation module is used for providing current for the first resistor and the first capacitor through the first current source after receiving the starting signal, and obtaining a fifth voltage. At this time, when the start signal is received and the first sub-current module stops providing the current, the second comparison module may compare the third voltage with the fifth voltage, and control the second sub-current module to provide the second preset current and control the third sub-current module to stop providing the current after the third voltage is greater than the fifth voltage and the target delay time elapses. In case the second sub-current module stops providing current: the second comparison module is also used for comparing the fourth voltage with the fifth voltage, controlling the first sub-current module to provide a second preset current after the fourth voltage is greater than the fifth voltage and the target delay time elapses, and controlling the fourth sub-current module to stop providing the current; the first comparison module is also used for comparing the first voltage with the fifth voltage and outputting a second clock signal; and controlling the first sub-current module to stop providing current after the fifth voltage is greater than the first voltage and the target delay time elapses; the first clock signal and the second clock signal are opposite. Obviously, in different modes, the circuit can be pressurized by adopting 2 times of current, so that the time exceeding due to the time delay of the comparator is compensated, the effect of no time delay is further achieved, and the output clock signal is stable.

In order to achieve the above object, the embodiments of the present application provide the following technical solutions, which are described in detail with reference to the accompanying drawings.

As shown in fig. 2, fig. 2 is an oscillator circuit 10 provided in the embodiment of the present application, including: a first current module 100, a second current module 200, a temperature drift cancellation module 300, a first comparison module 400, and a second comparison module 500; the first current module 100 includes a first sub-current module 110 and a second sub-current module 120; the second current module 200 includes a third sub-current module 210 and a fourth sub-current module 220; the currents provided by the first sub-current module 110, the second sub-current module 120, the third sub-current module 210 and the fourth sub-current module 220 are the same; the first and second comparison modules 400 and 500 are identical; the temperature drift cancellation module 300 includes a first current source 310, a first resistor 320 and a first capacitor 330, one end of the first current source 310 is connected to the power-on start module 600, one ends of the first resistor 320 and the first capacitor 330 are both connected to the other end of the first current source 310, the other ends of the first resistor 320 and the first capacitor 330 are grounded, and a first end and a second end of the first comparison module 400 and a first end and a second end of the second comparison module 500 are respectively connected to the other end of the first current source 310.

The resistance value of the first resistor 320 is maintained within a constant range at different temperatures. That is, the resistance of the first resistor 320 does not change with temperature.

It should be noted that the current provided by the first current source 310 may be the same as or different from the currents provided by the first sub-current module 110, the second sub-current module 120, the third sub-current module 210, and the fourth sub-current module 220. If the current provided by the first current source 310 is slightly larger than the currents provided by the first sub-current module 110, the second sub-current module 120, the third sub-current module 210, and the fourth sub-current module 220, it is necessary to set the resistance of the first resistor 320 to be larger than the resistance of the first resistor 320 under the condition that the currents are the same when the first resistor 320 is set.

As shown in fig. 2, the first ends of the first sub-current module 110, the second sub-current module 120, the third sub-current module 210, and the fourth sub-current module 220 are all connected to the power-on start module 600; the second ends of the first sub-current module 110, the second sub-current module 120, the third sub-current module 210 and the fourth sub-current module 220 are all grounded;

the other end of the first current source 310 is connected to the first end of the first comparing module 400; the third terminal of the second sub-current module 120 is connected to the second terminal of the first comparison module 400; the third terminal of the third sub-current module 210 is connected to the first terminal of the second comparison module 500; the other end of the first current source 310 is connected to the second end of the second comparing module 500;

the third terminal of the first sub-current module 110 is connected to the first terminal of the first comparison module 400; the other end of the first current source 310 is connected to the second end of the first comparing module 400; the other end of the first current source 310 is connected to the first end of the second comparing module 500; the third terminal of the fourth sub-current block 220 is connected to the second terminal of the second comparison block 500.

Specifically, the first sub-current module 110 and the second sub-current module 120 are configured to alternately provide a first predetermined current, and generate a first voltage of the first sub-current module 110 and a second voltage of the second sub-current module 120.

The third sub-current module 210 and the fourth sub-current module 220 are configured to alternately provide a second preset current to generate a third voltage and a fourth voltage; the first preset current is 2 times of the second preset current.

The temperature drift cancellation module 300 is configured to provide a current to the first resistor 320 and the first capacitor 330 through the first current source 310 after receiving the start signal, so as to obtain a fifth voltage.

It should be noted that the first sub-current module 110 is matched with the third sub-current module 210, and the second sub-current module 120 is matched with the fourth sub-current module 220.

Upon receiving the start signal and the first sub-current module 110 stopping providing the current:

the second comparing module 500 is configured to compare the third voltage with the fifth voltage, control the second sub-current module 120 to provide a second preset current after the third voltage is greater than the fifth voltage and a target delay time elapses, and control the third sub-current module 210 to stop providing current.

The target delay time may be determined by the third voltage provided by the third sub-current module 210 and the fourth sub-current module 220 or the variation of the fourth voltage. The delay time obtained by multiple experiments after the relevant person determines the comparator type may also be used, and is not limited herein.

A first comparing module 400 for comparing the second voltage with the fifth voltage and outputting a first clock signal; and controls the second sub-current module 120 to stop providing the current after the fifth voltage is greater than the second voltage and the target delay time elapses.

And when the second voltage is greater than or equal to the fifth voltage, outputting a high level, and when the second voltage is less than the fifth voltage, outputting a low level. When the second voltage is changed, a transformed first clock signal may be generated.

In case the second sub-current module 120 stops providing current:

the second comparing module 500 is further configured to compare the fourth voltage with the fifth voltage, control the first sub-current module 110 to provide the second preset current after the fourth voltage is greater than the fifth voltage and the target delay time elapses, and control the fourth sub-current module 220 to stop providing the current.

The first comparing module 400 is further configured to compare the first voltage with the fifth voltage and output a second clock signal; and, after the fifth voltage is greater than the first voltage and the target delay time elapses, controlling the first sub-current module 110 to stop providing the current; the first clock signal and the second clock signal are opposite.

When the first voltage is greater than or equal to the fifth voltage, a low level is output, and when the first voltage is less than the fifth voltage, a high level is output. When the first voltage is changed, a transformed second clock signal may be generated.

In the embodiment of the present application, the first sub-current module 110 and the second sub-current module 120 are configured to alternately provide the first preset current to generate a first voltage of the first sub-current module 110 and a second voltage of the second sub-current module 120. The third sub-current module 210 and the fourth sub-current module 220 are configured to alternately provide a second predetermined current to generate a third voltage and a fourth voltage. And the first preset current is 2 times of the second preset current. The temperature drift cancellation module 300 is configured to provide a current to the first resistor 320 and the first capacitor 330 through the first current source 310 after receiving the start signal, so as to obtain a fifth voltage. At this time, when the start signal is received and the first sub-current module 110 stops providing the current, the second comparing module 500 may compare the third voltage and the fifth voltage, and control the second sub-current module 120 to provide the second preset current and control the third sub-current module 210 to stop providing the current after the third voltage is greater than the fifth voltage and the target delay time elapses. In case the second sub-current module 120 stops providing current: the second comparing module 500 is further configured to compare the fourth voltage with the fifth voltage, control the first sub-current module 110 to provide a second preset current after the fourth voltage is greater than the fifth voltage and a target delay time elapses, and control the fourth sub-current module 220 to stop providing current; the first comparing module 400 is further configured to compare the first voltage with the fifth voltage and output a second clock signal; and, after the fifth voltage is greater than the first voltage and the target delay time elapses, controlling the first sub-current module 110 to stop providing the current; the first clock signal and the second clock signal are opposite. Obviously, in different modes, the circuit can be pressurized by adopting 2 times of current, so that the time exceeding due to the time delay of the comparator is compensated, the effect of no time delay is further achieved, and the output clock signal is stable.

The above embodiment describes the oscillator circuit 10, and the operation principle of the first sub-current module 110 when receiving the start signal and stopping supplying the current is further described with an embodiment. In one embodiment, referring to fig. 2, upon receiving the start signal and the first sub-current module 110 stopping supplying current:

the other end of the first current source 310 is connected to the first end of the first comparing module 400, the third end of the second sub-current module 120 is connected to the second end of the first comparing module 400, the third end of the third sub-current module 210 is connected to the first end of the second comparing module 500, and the other end of the first current source 310 is connected to the second end of the second comparing module 500.

In case the second sub-current module 120 stops providing current: the third terminal of the first sub-current module 110 is connected to the first terminal of the first comparing module 400, the other terminal of the first current source 310 is connected to the second terminal of the first comparing module 400, the other terminal of the first current source 310 is connected to the first terminal of the second comparing module 500, and the third terminal of the fourth sub-current module 220 is connected to the second terminal of the second comparing module 500.

In the embodiment of the application, the on-off of different modules is controlled, so that in two modes, after 2 times of current is alternately adopted for boosting in each clock signal, 1 time of current is continuously adopted for realizing the operation of a circuit, the time of delay time for boosting at 2 times of speed and for shortening 1 time of boosting is saved, and the clock signal can be stably output.

The above embodiment describes the oscillator circuit 10, and the second sub-current module 120 and the third sub-current module 210 in the oscillator circuit 10 are described with an embodiment. In one embodiment, as shown in fig. 3, the second sub-current module 120 includes a second current source 121, a third current source 122, and a second capacitor 123. The third sub-current module 210 includes a fourth current source 211 and a third capacitor 212. The currents supplied by the second current source 121, the third current source 122 and the fourth current source 211 are the same.

When the start signal is received and the first sub-current module 110 stops providing current:

and a second sub-current module 120 for charging a second capacitor 123 through a second current source 121 and a third current source 122.

Specifically, the second current source 121 and the third current source 122 simultaneously supply charges to the second capacitor 123, that is, supply the first preset current, and the voltage across the second capacitor 123 increases.

The third sub-current module 210 is configured to charge the third capacitor 212 through the fourth current source 211 after receiving the start signal.

Specifically, when receiving the start signal, the fourth current source 211 charges the third capacitor 212, i.e. provides a second predetermined current.

The second comparing module 500 is configured to compare a third voltage across the third capacitor 212 with a fifth voltage across the first capacitor 330, and control the second current source 121 to stop providing current to the second capacitor 123 and control the fourth current source 211 to stop charging the third capacitor 212 after the third voltage is greater than the fifth voltage and a target delay time elapses.

The first comparing module 400 is configured to compare the fifth voltage and the second voltage across the first capacitor 330, output a clock signal, and control the third current source 122 to stop charging the second capacitor 123 after the fifth voltage is greater than the second voltage and a target delay time elapses.

Specifically, when the start signal is received, the second current source 121 and the third current source 122 charge the second capacitor 123 at the same time, and the fourth current source 211 charges the third capacitor 212. The second comparing module 500 compares the third voltage across the third capacitor 212 with the fifth voltage across the first capacitor 330, and controls the second current source 121 to stop supplying current to the second capacitor 123 and the fourth current source 211 to stop charging the third capacitor 212 after the third voltage is greater than the fifth voltage and the target delay time elapses. The first comparing module 400 compares the fifth voltage and the second voltage across the first capacitor 330, outputs a clock signal, and controls the third current source 122 to stop charging the second capacitor 123 after the fifth voltage is greater than the second voltage and a target delay time elapses.

Further, in one embodiment, as shown in fig. 4, the second sub-current module 120 further includes a first switch 124 (S1), a second switch 116 (Q1), and a third switch 115 (Q1B); one end of the second current source 121 and one end of the third current source 122 are connected to the power-on starting module 600, the other end of the second current source 121 is connected to one end of the first switch 124 (S1), the other end of the third current source 122 and a first common end of the other end of the first switch 124 (S1) are respectively connected to one end of the second switch 116 (Q1) and one end of the third switch 115 (Q1B), the other end of the second switch 116 (Q1) is connected to one end of the second capacitor 123, and the other end of the second capacitor 123 and the other end of the third switch 115 (Q1B) are grounded; the first common terminal is connected to the second terminal of the first comparing module 400, the first terminal of the first comparing module 400 and the second terminal of the second comparing module 500 are both connected to the other terminal of the first current source 310, and the first terminal of the second comparing module 500 is connected to the third terminal of the third sub-current module 210.

The second comparing module 500 is configured to control the first switch 124 to be turned off after the target delay time elapses and the third voltage is greater than the fifth voltage, so that the second current source 121 stops supplying current to the second capacitor 123.

The first comparing module 400 is configured to compare the fifth voltage and the second voltage at two ends of the first capacitor 330, output a clock signal, and control the second switch 116 to be turned off and control the third switch 115 to be turned on after the fifth voltage is greater than the second voltage and a target delay time elapses, so that the third current source 122 stops charging the second capacitor 123 and discharges the second capacitor 123.

Further, in one embodiment, referring to fig. 4, the third sub-current module 210 further includes a first switch 124 (S1), a third switch 115 (Q1B), and a fourth switch 114 (S2). Wherein, the third capacitor 212 includes a first sub-capacitor 2121 and a second sub-capacitor 2122; one end of the fourth current source 211 is connected to the power-on start module 600, the other end of the fourth current source 211 is connected to one end of the first switch 124, the second common end of the first sub-capacitor 2121 and the second sub-capacitor 2122 is connected to the other end of the first switch 124, the other end of the first sub-capacitor 2121 is connected to the first end of the second comparison module 500 and one end of the third switch 115, the other end of the third switch 115 is connected to the other end of the first current source 310, the other end of the second sub-capacitor 2122 and one end of the fourth switch 114 are grounded, and the other end of the fourth switch 114 is connected to the second common end.

and the second comparing module 500 is configured to, after the third voltage is greater than the fifth voltage and the target delay time elapses, control the first switch 124 to be turned off, and control the fourth switch 114 and the third switch 115 to be turned on, so that the fourth current source 211 stops charging the second sub-capacitor 2122, and control the voltage across the first sub-capacitor 2121 to be equal to the fifth voltage.

In the embodiment of the present application, the second sub-current module 120 and the third sub-current module 210 cooperate to provide a clock signal, and save the delay by applying 2 times of current to increase the voltage, so that the instability of the output frequency caused by the delay of the comparator is avoided during the operation of the whole circuit.

The above embodiment describes the oscillator circuit 10, and the first sub-current block 110 in the oscillator circuit 10 is described with an embodiment. In one embodiment, as shown in fig. 5, the first sub-current module 110 includes a fifth current source 111, a sixth current source 112, and a fourth capacitor 113, and the fourth sub-current module 220 includes a seventh current source 221 and a fifth capacitor 222.

Wherein, the currents provided by the fifth current source 111, the sixth current source 112 and the seventh current source 221 are the same as the currents provided by the second current source 121, the third current source 122 and the fourth current source 211.

In case the second sub-current module 120 stops providing current:

a first sub-current module 110, configured to charge a fourth capacitor 113 through a fifth current source 111 and a sixth current source 112.

And a fourth sub-current module 220 for charging a fifth capacitor 222 through a seventh current source 221.

A second comparing module 500, configured to compare the fourth voltage and the fifth voltage across the seventh current source 221, and control the sixth current source 112 to stop providing the current to the fourth capacitor 113 and control the fourth sub-current module 220 to stop providing the current to the fifth capacitor 222 after the fourth voltage is greater than the fifth voltage and a target delay time elapses;

a first comparing module 400, configured to compare the first voltage and the fifth voltage at two ends of the fourth capacitor 113, and output a second clock signal; and, after the fifth voltage is greater than the first voltage and the target delay time elapses, the fifth current source 111 is controlled to stop supplying the current to the fourth capacitor 113.

Further, in one embodiment, as shown in fig. 6, the first sub-current module 110 further includes a fourth switch 114 (S2), a third switch 115 (Q1B), and a second switch 116 (Q1). One end of the fifth current source 111 and one end of the sixth current source 112 are connected to the power-on starting module 600, the other end of the sixth current source 112 is connected to one end of the fourth switch 114, the other end of the fourth switch 114 is connected to a third common end of the other end of the fifth current source 111 and one end of the third switch 115, the other end of the third switch 115 is connected to one end of the fourth capacitor 113 and one end of the second switch 116, and the other end of the fourth capacitor 113 and the other end of the second switch 116 are grounded; the third common terminal is connected to the first terminal of the first comparing module 400; the second terminal of the first comparing module 400 and the first terminal of the second comparing module 500 are connected to the other terminal of the first current source 310; the second terminal of the second comparing module 500 is connected to the third terminal of the fourth sub-current module 220.

The second comparing module 500 is configured to compare the fourth voltage across the fifth capacitor 222 with the fifth voltage across the first capacitor 330, and control the fourth switch 114 to be turned off after the fourth voltage is greater than the fifth voltage and a target delay time elapses, so that the sixth current source 112 stops charging the fourth capacitor 113;

a first comparing module 400, configured to compare the first voltage and the fifth voltage at two ends of the fourth capacitor 113, and output a second clock signal; and after the fifth voltage is greater than the first voltage and the target delay time elapses, the third switch 115 is controlled to be opened, so that the fifth current source 111 stops charging the fourth capacitor 113, and the second switch 116 is controlled to be closed, so that the fourth capacitor 113 is discharged.

Further, in one embodiment, as shown with reference to fig. 6, the fourth sub-current module 220 further includes: a fourth switch 114 (S2), a second switch 116 (Q1), and a first switch 124 (S1). Fifth capacitor 222 includes a third sub-capacitor 2221 and a fourth sub-capacitor 2222; one end of the seventh current source 221 is connected to the power-on start module 600, the other end of the seventh current source 221 is connected to one end of the fourth switch 114, one end of the third sub-capacitor 2221, one end of the fourth sub-capacitor 2222, and one end of the first switch 124 are all connected to the other end of the fourth switch 114, the other ends of the first switch 124 and the third sub-capacitor 2221 are grounded, the other end of the fourth sub-capacitor 2222 is connected to one end of the second switch 116, the other end of the second switch 116 is connected to the other end of the first current source 310, the other end of the fourth sub-capacitor 2222 is connected to the second end of the second comparison module 500, and the first end of the second comparison module 500 is connected to the other end of the first current source 310.

It should be noted that in the embodiment of the present application, except for the first resistor 320, other resistors are resistors of the same type and size, and except for the first capacitor 330, other capacitors are capacitors of the same type and size.

In case the second sub-current module 120 stops providing current:

the second comparing module 500 is configured to compare the fourth voltage and the fifth voltage across the fourth sub-capacitor 2222, and after the fourth voltage is greater than the fifth voltage and a target delay time elapses, control the fourth switch 114 to be turned off, so that the seventh current source 221 stops charging the third sub-capacitor 2221, and close the second switch 116 and the first switch 124, so that the voltage across the fourth sub-capacitor 2222 is equal to the fifth voltage.

In the embodiment of the present application, the first sub-current module 110 and the fourth sub-current module cooperate to provide another clock signal, and save the delay by applying 2 times of current to increase the voltage, so that the instability of the output frequency caused by the delay of the comparator is avoided during the operation of the whole circuit.

The above embodiments describe each power supply module in the oscillator circuit 10, and the first comparison module 400 and the second comparison module 500 are described in one embodiment. In one embodiment, as shown in fig. 7, the first comparison module 400 includes: two third switches 115 (Q1B), two second switches 116 (Q1), a first comparator 410, a first inverter 420, a first RS flip-flop 430. A second comparing module 500, comprising: two third switches 115 (Q1B), two second switches 116 (Q1), a second comparator 510, a second inverter 520, and a second RS flip-flop 530.

The oscillator circuit 10 further includes a switch control unit 700. The switch controller includes a first switch (S1) control unit 710 and a second switch (S2) control unit 720.

One end of a third switch 115 and one end of a second switch 116 in the first comparing module 400 are respectively connected with a first end of a first comparator 410; the other end of a third switch 115 is connected to the other end of the first current source 310; the other end of a second switch 116 is connected to the first common terminal.

One end of the other third switch 115 and one end of the other second switch 116 are connected to the second end of the first comparator 410, respectively; the other end of the other third switch 115 is connected to the third common terminal, and the other end of the other second switch 116 is connected to the other end of the first current source 310.

The third terminals of the first comparators 410 are respectively connected with the input terminals of the first inverters 420; the third terminal of the first comparator 410 and the output terminal of the first inverter 420 are respectively connected to the first RS flip-flop 430, the first output terminal of the first RS flip-flop 430 is respectively connected to the second switches 116 and the first input terminal of the first switch control unit 710, and the second output terminal of the first RS flip-flop 430 is respectively connected to the third switches 115 and the first input terminal of the second switch control unit 720.

One end of a third switch 115 and one end of a second switch 116 in the second comparing module 500 are respectively connected with a first end of a second comparator 510; the other terminal of the third switch 115 is connected to the other terminal of the fourth sub-capacitor 2222, and the other terminal of the second switch 116 is connected to the other terminal of the first current source 310.

One end of another third switch 115 and one end of another second switch 116 are connected to the second end of the second comparator 510, respectively; the other end of the third switch 115 is connected to the other end of the first current source 310, and the other end of the second switch 116 is connected to the other end of the first sub-capacitor 2121.

The third terminals of the second comparators 510 are respectively connected with the input terminals of the second inverters 520; a third terminal of the second comparator 510 and an output terminal of the second inverter 520 are respectively connected to the second RS flip-flop 530, a first output terminal of the second RS flip-flop 530 is connected to a second input terminal of the first switch control unit 710, and a second output terminal of the second RS flip-flop 530 is connected to a second input terminal of the second switch control unit 720.

Specifically, the third terminal of the first inverter 420 is used for outputting a clock signal.

The first switch control unit 710 is configured to control the respective first switches 124 to be turned off or turned on according to the output signal of the first output terminal of the first RS flip-flop 430 and the output signal of the second output terminal of the second RS flip-flop 530.

Specifically, when the output signals of the two RS flip-flops are high at the same time, the first switch 124 is controlled to be turned on, and otherwise, the first switch 124 is turned off.

The turn-off or turn-on second switch control unit 720 is used for controlling the turn-off or turn-on of each fourth switch 114 according to the output signal of the second output terminal of the first RS flip-flop 430 and the output signal of the first output terminal of the second RS flip-flop 530.

Specifically, when the output signals of the two RS flip-flops are high at the same time, the second switch 116 is controlled to be turned on, and otherwise, the second switch 116 is turned off.

The first RS flip-flop 430 is configured to transmit an output signal of a first output terminal of the first RS flip-flop 430 to each of the second switches 116, so that the second switches 116 are turned off or turned on; and transmits an output signal of the second output terminal of the first RS flip-flop 430 to each third switch 115 to turn off or on the third switch 115.

Optionally, the first RS flip-flop 430 and the second RS flip-flop 530 are and gate flip-flops.

In the embodiment of the present application, the first comparison module 400 and the second comparison module 500 are described, and the respective switches in the oscillator circuit 10 are controlled to be turned on and off by the cooperation of the respective devices, so that the respective parts perform their respective functions.

In one embodiment, as shown in fig. 8, the first resistor 320 includes a first sub-resistor 321 and a second sub-resistor 322, one end of the first sub-resistor 321 is connected to the other end of the first signal source, the other end of the first sub-resistor 321 is connected to one end of the second sub-resistor 322, the other end of the second sub-resistor 322 is grounded, the first sub-resistor 321 is a positive temperature coefficient resistor, and the second sub-resistor 322 is a negative temperature coefficient resistor.

The positive and negative temperature coefficients of the first sub-resistor 321 and the second word resistor can be cancelled, so that the first resistor 320 which does not change with temperature is obtained. And a fifth voltage insensitive to temperature may be obtained. The oscillator circuit 10 is not affected by temperature, which causes temperature drift and further affects the output frequency of the oscillator circuit 10.

Exemplary reference is made to fig. 1-9, wherein fig. 9 is a simulation of oscillator circuit 10 during operation. Wherein V1 is a first voltage across the fourth capacitor, V2 is a second voltage across the second capacitor, V31 is a third voltage across the first sub-capacitor, V4 is a fifth voltage across the first capacitor, V41 is a fourth voltage across the fifth capacitor, S1 is the first switch 124, S2 is the fourth switch 114, Q1 is the second switch 116, Q1B is the third switch 115, phase1 is the output clock signal, phase2 is the inverted signal of Phase1, phase _1 is the first signal output by the second comparator, and Phase _2 is the second signal after inverting the first signal.

Referring to fig. 9, in each waveform diagram in the area a, when the start signal is received, S1 is closed (at a high level), and the first sub-current block 110 does not operate due to the open of S2. The second current source 121 and the third current source 122 in the second sub-current module 120 charge the second capacitor 123 (as shown in fig. 9, V2 rises with a slope twice as large as V31), and the third sub-current module 210 is configured to charge the third capacitor 212 through the fourth current source 211 after receiving the start signal.

At this time, V31 starts to rise from 0, and after the voltage rises to be stable, the second comparing module 500 is configured to compare the third voltage across the third capacitor 212 with the fifth voltage across the first capacitor 330, that is, V31 is compared with V4, and after the third voltage is greater than the fifth voltage and the target delay time elapses (V31 is greater than V4 and the target delay time elapses), control the second current source 121 to stop providing the current to the second capacitor 123, and control the fourth current source 211 to stop charging the third capacitor 212. At this time, the second current source 121 stops supplying power. At this time, V2 is increased by the second preset current only from the third current source 122, and the slope of V2 is decreased. At this time, phase _1 is high and Phase _2 is low, and further, the output Q2 of the second RS flip-flop 530 is high and Q2B is low. Further, the first switch control unit 710 controls S1 to be turned off.

At this time, the first comparing module 400 is configured to compare the fifth voltage across the first capacitor 330 with the second voltage, and control the third current source 122 to stop charging the second capacitor 123 after the fifth voltage is greater than the second voltage and a target delay time elapses. In the above process, the clock signal (Phase 1 is high), phase2 is low after passing through the first inverter 420, and after Phase1 and Phase2 are input to the first RS flip-flop 430, the output Q1 is high and Q1B is low.

At this time, when the second sub-current module 120 and the third sub-current module 210 are both turned off by the control of the switches S1 and Q1, the output clock signal (Phase 1 is low), Q1 is low, Q1B is high, at this time, the second switch control unit 720 may control S2 to be turned on, and the first sub-current module 110 is used to charge the fourth capacitor 113 through the fifth current source 111 and the sixth current source 112, that is, the slope of V1 is 2 times the slope of V41. And a fourth sub-current module 220 for charging a fifth capacitor 222 through a seventh current source 221.

The second comparing module 500 is configured to compare the fourth voltage V41 across the fifth capacitor 222 with the fifth voltage V4 across the first capacitor 330, and control the fourth switch 114S2 to be turned off after the target delay time elapses when V41 is greater than V4, so that the sixth current source 112 stops charging the fourth capacitor 113; at this time, phase _1 is low and Phase _2 is high, and further, the output Q2 of the second RS flip-flop 530 is low and Q2B is high.

A first comparing module 400, configured to compare the first voltage V1 and the fifth voltage V4 at two ends of the fourth capacitor 113, and output a second clock signal, where Phase1 is at a low level, and Phase2 is at a high level after passing through the first inverter 420; and after the fifth voltage is greater than the first voltage and the target delay time elapses, the third switch 115 is controlled to be turned off, so that the fifth current source 111 stops charging the fourth capacitor 113, and the second switch 116 is controlled to be turned on, so that the fourth capacitor 113 is discharged.

Through the above example, it can be seen that the second sub-current module and the third sub-current module are used in cooperation, and the first sub-current module and the fourth sub-current module are used in cooperation to alternately generate clock signals, and meanwhile, the delay can be compensated, so that the output frequency of the oscillator circuit is stable.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.

Claims

1. An oscillator circuit, comprising: the temperature drift compensation circuit comprises a first current module, a second current module, a temperature drift compensation module, a first comparison module and a second comparison module; the first current module comprises a first sub-current module and a second sub-current module; the second current module comprises a third sub-current module and a fourth sub-current module; the currents provided by the first sub-current module, the second sub-current module, the third sub-current module and the fourth sub-current module are the same; the first comparison module and the second comparison module are the same; the temperature drift cancellation module comprises a first current source, a first resistor and a first capacitor, one end of the first current source is connected with the power-on starting module, one ends of the first resistor and the first capacitor are both connected with the other end of the first current source, the other ends of the first resistor and the first capacitor are grounded, and the first end and the second end of the first comparison module and the first end and the second end of the second comparison module are respectively connected with the other end of the first current source; the resistance value of the first resistor is kept in a constant range at different temperatures;

the temperature drift cancellation module is configured to provide current for the first resistor and the first capacitor through the first current source after receiving a start signal, so as to obtain a fifth voltage;

when a starting signal is received and the first sub-current module stops providing current:

the second comparing module is configured to compare the third voltage with the fifth voltage, and control the second sub-current module to provide the second preset current and control the third sub-current module to stop providing current after the third voltage is greater than the fifth voltage and a target delay time elapses;

the first comparison module is used for comparing the second voltage with the fifth voltage and outputting a first clock signal; and controlling the second sub-current module to stop providing current after the fifth voltage is greater than the second voltage and the target delay time elapses;

in the event that the second sub-current module stops providing current:

the second comparing module is further configured to compare the fourth voltage with the fifth voltage, and control the first sub-current module to provide the second preset current and control the fourth sub-current module to stop providing current after the fourth voltage is greater than the fifth voltage and a target delay time elapses;

the first comparing module is further configured to compare the first voltage with the fifth voltage and output a second clock signal; and controlling the first sub-current module to stop providing current after the fifth voltage is greater than the first voltage and the target delay time elapses; the first clock signal and the second clock signal are opposite.

2. The oscillator circuit of claim 1, wherein the first terminals of the first sub-current module, the second sub-current module, the third sub-current module, and the fourth sub-current module are connected to a power-on start module; the second ends of the first sub-current module, the second sub-current module, the third sub-current module and the fourth sub-current module are all grounded;

3. The oscillator circuit of claim 2, wherein upon receiving a start signal and the first sub-current module ceasing to provide current:

in the event that the second sub-current module stops providing current:

the other end of the first current source is connected with the first end of the second comparison module;

4. The oscillator circuit of claim 3, wherein the second sub-current block comprises a second current source, a third current source, and a second capacitor; the third sub-current module comprises a fourth current source and a third capacitor; the currents provided by the second current source, the third current source and the fourth current source are the same;

the second sub-current module is configured to charge the second capacitor through the second current source and the third current source;

the third sub-current module is used for charging the third capacitor through the fourth current source after receiving a starting signal;

the second comparing module is configured to compare a third voltage across the third capacitor with a fifth voltage across the first capacitor, and control the second current source to stop supplying current to the second capacitor and control the fourth current source to stop charging the third capacitor after the third voltage is greater than the fifth voltage and a target delay time elapses;

the first comparison module is configured to compare a fifth voltage at two ends of the first capacitor with the second voltage, output a clock signal, and control the third current source to stop charging the second capacitor after the fifth voltage is greater than the second voltage and the target delay time elapses.

5. The oscillator circuit of claim 4, wherein the second sub-current block further comprises a first switch, a second switch, and a third switch; one end of the second current source and one end of the third current source are connected with the power-on starting module, the other end of the second current source is connected with one end of the first switch, the other end of the third current source and a first common end of the other end of the first switch are respectively connected with one end of the second switch and one end of the third switch, the other end of the second switch is connected with one end of the second capacitor, and the other end of the second capacitor and the other end of the third switch are grounded; the first common end is connected with the second end of the first comparison module, the first end of the first comparison module and the second end of the second comparison module are both connected with the other end of the first current source, and the first end of the second comparison module is connected with the third end of the third sub-current module;

the second comparing module is configured to control the first switch to be turned off after the third voltage is greater than the fifth voltage and a target delay time elapses, so that the second current source stops supplying current to the second capacitor;

the first comparison module is configured to compare a fifth voltage across the first capacitor with the second voltage, output a clock signal, and control the second switch to be turned off and control the third switch to be turned on when the fifth voltage is greater than the second voltage and the target delay time elapses, so that the third current source stops charging the second capacitor and discharges the second capacitor.

6. The oscillator circuit of claim 5, wherein the third sub-current block further comprises the first switch, the third switch, and a fourth switch; the third capacitor comprises a first sub-capacitor and a second sub-capacitor; one end of the fourth current source is connected with the power-on starting module, the other end of the fourth current source is connected with one end of the first switch, a second common end of the first sub-capacitor and the second sub-capacitor is connected with the other end of the first switch, the other end of the first sub-capacitor is respectively connected with a first end of the second comparing module and one end of the third switch, the other end of the third switch is connected with the other end of the first current source, the other end of the second sub-capacitor and one end of the fourth switch are grounded, and the other end of the fourth switch is connected with the second common end;

and the second comparison module is configured to control the first switch to be turned off and control the fourth switch and the third switch to be turned on after the third voltage is greater than the fifth voltage and a target delay time elapses, so that the fourth current source stops charging the second sub-capacitor, and the voltage at two ends of the first sub-capacitor is controlled to be equal to the fifth voltage.

7. The oscillator circuit of claim 6, wherein the first sub-current block comprises a fifth current source, a sixth current source, and a fourth capacitance; the fourth sub-current module comprises a seventh current source and a fifth capacitor; the current provided by the fifth current source, the sixth current source and the seventh current source is the same as the current provided by the second current source, the third current source and the fourth current source;

in the event that the second sub-current module stops providing current:

the first sub-current module is configured to charge the fourth capacitor through the fifth current source and a sixth current source;

the fourth sub-current module is configured to charge the fifth capacitor through the seventh current source;

the second comparing module is configured to compare a fourth voltage across the seventh current source with the fifth voltage, and control the sixth current source to stop providing current to the fourth capacitor and control the fourth sub-current module to stop providing current to the fifth capacitor after the fourth voltage is greater than the fifth voltage and a target delay time elapses;

the first comparison module is used for comparing the first voltage at two ends of the fourth capacitor with the fifth voltage and outputting a second clock signal; and controlling the fifth current source to stop supplying current to the fourth capacitor after the fifth voltage is greater than the first voltage and the target delay time elapses.

8. The oscillator circuit according to claim 7, wherein the first sub-current module further includes the fourth switch, the third switch and a second switch, one end of the fifth current source and one end of the sixth current source are connected to the power-on start module, the other end of the sixth current source is connected to one end of the fourth switch, the other end of the fourth switch and a third common end of the other end of the fifth current source are connected to one end of the third switch, the other end of the third switch is connected to one end of the fourth capacitor and one end of the second switch, respectively, and the other end of the fourth capacitor and the other end of the second switch are grounded; the third common end is connected with the first end of the first comparison module; the second end of the first comparison module and the first end of the second comparison module are connected with the other end of the first current source; the second end of the second comparison module is connected with the third end of the fourth sub-current module;

the second comparing module is configured to compare a fourth voltage across the fifth capacitor with a fifth voltage across the first capacitor, and control the fourth switch to be turned off after the fourth voltage is greater than the fifth voltage and a target delay time elapses, so that the sixth current source stops charging the fourth capacitor;

the first comparison module is used for comparing the first voltage at two ends of the fourth capacitor with the fifth voltage and outputting a second clock signal; and after the fifth voltage is greater than the first voltage and the target delay time elapses, controlling the third switch to be turned off to stop the fifth current source from charging the fourth capacitor, and controlling the second switch to be turned on to discharge the fourth capacitor.

9. The oscillator circuit of claim 8, wherein the fourth sub-current block further comprises: the fourth switch, the second switch and the first switch, and the fifth capacitor comprises a third sub-capacitor and a fourth sub-capacitor; one end of the seventh current source is connected with the power-on starting module, the other end of the seventh current source is connected with one end of the fourth switch, one end of the third sub-capacitor, one end of the fourth sub-capacitor and one end of the first switch are all connected with the other end of the fourth switch, the other end of the first switch and the other end of the third sub-capacitor are grounded, the other end of the fourth sub-capacitor is connected with one end of the second switch, the other end of the second switch is connected with the other end of the first current source, the other end of the fourth sub-capacitor is connected with the second end of the second comparison module, and the first end of the second comparison module is connected with the other end of the first current source;

in the event that the second sub-current module stops providing current:

and the second comparison module is used for comparing a fourth voltage at two ends of the fourth sub-capacitor with the fifth voltage, and controlling the fourth switch to be switched on and off after the fourth voltage is greater than the fifth voltage and a target delay time is passed, so that the seventh current source stops charging the third sub-capacitor, and the second switch and the first switch are switched off, so that the voltages at two ends of the fourth sub-capacitor are equal to the fifth voltage.

10. The oscillator circuit of claim 9, wherein the first comparison module comprises: the two third switches, the two second switches, the first comparator, the first inverter and the first RS trigger;

the second comparing module comprises: the two third switches, the two second switches, the second comparator, the second inverter and the second RS trigger;

one end of one third switch and one end of one second switch in the first comparison module are respectively connected with the first end of one first comparator; the other end of the third switch is connected with the other end of the first current source; the other end of the second switch is connected with the first common end;

one end of the other third switch and one end of the other second switch are respectively connected with the second end of the first comparator; the other end of the third switch is connected with the third common end, and the other end of the second switch is connected with the other end of the first current source;

the third end of the first comparator is respectively connected with the input end of the first inverter; the third end of the first comparator and the output end of the first inverter are respectively connected with the first RS trigger, the first output end of the first RS trigger is respectively connected with the second switches and the first input end of the first switch control unit, and the second output end of the first RS trigger is respectively connected with the third switches and the first input end of the second switch control unit;

one end of one third switch and one end of one second switch in the second comparison module are respectively connected with the first end of one second comparator; the other end of the third switch is connected with the other end of the fourth sub-capacitor, and the other end of the second switch is connected with the other end of the first current source;

one end of the other third switch and one end of the other second switch are respectively connected with the second end of the second comparator; the other end of the third switch is connected with the other end of the first current source, and the other end of the second switch is connected with the other end of the first sub-capacitor;

the third end of the first inverter is used for outputting a clock signal;

the first switch control unit is configured to control the first switches to be turned off or turned on according to an output signal of a first output end of the first RS flip-flop and an output signal of a second output end of the second RS flip-flop;

the second switch control unit is configured to control the fourth switches to be turned off or turned on according to an output signal of the second output terminal of the first RS flip-flop and an output signal of the first output terminal of the second RS flip-flop;

the first RS flip-flop is configured to transmit an output signal of a first output end of the first RS flip-flop to each of the second switches, so that the second switches are turned off or turned on; and transmitting an output signal of the second output terminal of the first RS flip-flop to each of the third switches to turn off or on the third switch.

11. The oscillator circuit of claim 10, wherein the first RS flip-flop and the second RS flip-flop are and gate flip-flops.

12. The oscillator circuit according to any one of claims 1 to 11, wherein the first resistor comprises a first sub-resistor and a second sub-resistor, one end of the first sub-resistor is connected to the other end of the first signal source, the other end of the first sub-resistor is connected to one end of the second sub-resistor, the other end of the second sub-resistor is grounded, the first sub-resistor is a positive temperature coefficient resistor, and the second sub-resistor is a negative temperature coefficient resistor.