CN115986034A - Light emitting diode chip and preparation method thereof - Google Patents

Abstract

The disclosure provides a light emitting diode chip and a preparation method thereof, belonging to the technical field of photoelectron manufacturing. This emitting diode chip includes substrate, light emitting structure and anti-reflection coating, light emitting structure with anti-reflection coating is located respectively the two sides that the substrate is relative, anti-reflection coating includes a plurality of high refractive index layers and a plurality of low refractive index layer, a plurality of high refractive index layers with a plurality of low refractive index layer are range upon range of setting in turn on the substrate, anti-reflection coating is kept away from the surface of substrate has a plurality of shrinkage pools for light also can follow the pore wall of shrinkage pool and jets out, and through the pore wall external reflection of shrinkage pool, the shrinkage pool can make some light jet out anti-reflection coating sooner, reduces refraction and reflection frequency of this part light in anti-reflection coating, thereby reduces optical loss, further promotes the luminance of emitting diode chip.

Description

Light emitting diode chip and preparation method thereof

Technical Field

The disclosure relates to the technical field of photoelectron manufacturing, and in particular relates to a light emitting diode chip and a preparation method thereof.

Background

The Light Emitting Diode (abbreviated as LED) is a new product with great influence in the optoelectronic industry, has the characteristics of small volume, long service life, rich and colorful colors, low energy consumption and the like, and is widely applied to display equipment.

In order to improve the light extraction efficiency of the led, some reflective layers or anti-reflection layers are usually disposed in the led chip. For example, in the light emitting diode chip using the back surface of the substrate as the light emitting surface, the anti-reflection layer is disposed on the back surface of the substrate, which is beneficial to emitting light, so that the brightness of the light emitting diode chip is improved to a certain extent.

However, the brightness of the led chip provided with the anti-reflection layer is still insufficient to meet the requirement at present, and needs to be further improved.

Disclosure of Invention

The embodiment of the disclosure provides a light emitting diode chip and a manufacturing method thereof, which can further improve the brightness of the light emitting diode chip. The technical scheme is as follows:

in a first aspect, an embodiment of the present disclosure provides a light emitting diode chip, which includes a substrate, a light emitting structure, and an anti-reflection layer, where the light emitting structure and the anti-reflection layer are located on two opposite surfaces of the substrate, the anti-reflection layer includes a plurality of high refractive index layers and a plurality of low refractive index layers, the plurality of high refractive index layers and the plurality of low refractive index layers are alternately stacked on the substrate, and the anti-reflection layer is far away from the surface of the substrate and has a plurality of concave holes.

Optionally, the blind end of the recess hole is located in the low refractive index layer.

Optionally, the cross-sectional area of the recessed hole is positively correlated with the distance from the cross-section to the substrate.

Optionally, the bottom surface of the recessed hole is parallel to the surface of the substrate close to the anti-reflection layer, and an included angle formed between the side wall of the recessed hole and the bottom surface of the recessed hole is not smaller than a total reflection angle of the low refractive index layer.

Optionally, the concave hole is in a shape of a circular truncated cone.

Optionally, a ratio of a total area of the openings of the plurality of concave holes to an area of the surface of the anti-reflection layer away from the substrate is 10% to 20%.

Optionally, the low refractive index layer is SiO ₂ And (3) a layer.

Optionally, one side of the antireflection layer close to the substrate is the high refractive index layer, and one side far away from the substrate is the low refractive index layer.

Optionally, in the antireflection layer, the high refractive index layer closest to the substrate has a thickness of

In a second aspect, an embodiment of the present disclosure further provides a method for manufacturing a light emitting diode chip described in the previous aspect, where the method includes:

forming a light emitting structure on one surface of a substrate;

forming an antireflection layer on the other surface of the substrate, wherein the antireflection layer comprises a plurality of high-refractive-index layers and a plurality of low-refractive-index layers, and the plurality of high-refractive-index layers and the plurality of low-refractive-index layers are alternately stacked on the substrate;

and forming a plurality of concave holes on the surface of the anti-reflection layer far away from the substrate.

The beneficial effect that technical scheme that this disclosure embodiment provided brought includes at least:

the light emitting structure is arranged on one surface of the substrate, the anti-reflection layer is arranged on the other surface of the substrate, the anti-reflection layer is formed by alternately laminating a plurality of high-refractive-index layers and a plurality of low-refractive-index layers, and when light emitted by the light emitting structure passes through the anti-reflection layer and is reflected to one side of the substrate at the interface between the anti-reflection layer and the substrate and at the interface between the high-refractive-index layers and the low-refractive-index layers, the thicknesses of the high-refractive-index layers and the low-refractive-index layers are configured according to the light emitting wavelength of the light emitting structure, so that the reflected light at different interfaces has phase difference of odd times of pi and is offset with each other, the light reflected back to the substrate is reduced, the light efficiency of the light emitting diode chip is improved, and the brightness is improved. And because the surface of the anti-reflection layer far away from the substrate is also provided with a plurality of concave holes, light can also be emitted from the hole walls of the concave holes and is reflected outwards through the hole walls of the concave holes, the concave holes can enable a part of light to be emitted out of the anti-reflection layer more quickly, the refraction and reflection times of the part of light in the anti-reflection layer are reduced, the light loss is reduced, and the brightness of the light-emitting diode chip is further improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a light emitting diode chip according to an embodiment of the present disclosure;

fig. 2 is a flowchart of a method for manufacturing a light emitting diode chip according to an embodiment of the present disclosure;

fig. 3 is a flowchart illustrating a manufacturing process of a light emitting diode chip according to an embodiment of the present disclosure;

fig. 4 is a schematic view illustrating a manufacturing process of a light emitting diode chip according to an embodiment of the present disclosure;

fig. 5 is a schematic view illustrating a manufacturing process of a light emitting diode chip according to an embodiment of the present disclosure;

fig. 6 is a schematic view illustrating a manufacturing process of a light emitting diode chip according to an embodiment of the present disclosure;

fig. 7 is a schematic view of a manufacturing process of a light emitting diode chip according to an embodiment of the present disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a light emitting diode chip provided in an embodiment of the present disclosure. As shown in fig. 1, the light emitting diode chip includes a substrate 10, a light emitting structure 20, and an anti-reflection layer 30.

As shown in fig. 1, the light emitting structure 20 and the anti-reflection layer 30 are respectively disposed on two opposite surfaces of the substrate 10. The substrate 10 has a carrying surface and a back surface, the carrying surface is opposite to the back surface, the carrying surface and the back surface are two largest surfaces of the substrate 10, the light emitting structure 20 is located on the carrying surface of the substrate 10, and the anti-reflection layer 30 is located on the back surface of the substrate 10.

Illustratively, the substrate 10 may be a transparent substrate, such as a patterned sapphire substrate or the like.

The antireflection layer 30 includes a plurality of high refractive index layers 31 and a plurality of low refractive index layers 32, and the plurality of high refractive index layers 31 and the plurality of low refractive index layers 32 are alternately stacked and disposed on the substrate 10. The surface of anti-reflection layer 30 far from substrate 10 has a plurality of concave holes 30a.

By providing the light emitting structure 20 on one surface of the substrate 10 and providing the antireflection layer 30 on the other surface, the antireflection layer 30 is formed by alternately laminating a plurality of high refractive index layers 31 and a plurality of low refractive index layers 32. The thicknesses of the high refractive index layer 31 and the low refractive index layer 32 are configured according to the light emitting wavelength of the light emitting structure 20, so that when light emitted by the light emitting structure 20 passes through the antireflection layer 30 and is reflected to the side of the substrate 10 at the interface between the antireflection layer 30 and the substrate 10 and the interface between the high refractive index layer 31 and the low refractive index layer 32, light reflected by different interfaces has a phase difference of odd times pi, and the phase difference is cancelled, so that light reflected back to the substrate 10 is reduced, the light emitting efficiency of the light emitting diode chip is improved, and the brightness is improved. Because the surface of the anti-reflection layer 30 far away from the substrate 10 is also provided with the plurality of concave holes 30a, light can also be emitted from the hole walls of the concave holes 30a and is reflected outwards through the hole walls of the concave holes 30a, the concave holes 30a can enable a part of light to be emitted out of the anti-reflection layer 30 more quickly, the refraction and reflection times of the part of light in the anti-reflection layer 30 are reduced, the light loss is reduced, and the brightness of the light-emitting diode chip is further improved.

Illustratively, the high refractive index layer 31 and the low refractive index layer 32 may be alternately stacked by 10 to 20 layers. The total number of the high refractive index layer 31 and the low refractive index layer 32 is too many, which may increase the absorption of the anti-reflection layer 30 to light, and is not favorable for improving the light extraction efficiency of the led chip.

As shown in fig. 1, the blind end of the recess 30a is located in the low refractive index layer 32.

The recess 30a is blind, i.e. one end of the recess 30a is closed, and the blind end of the recess 30a is the closed end of the recess 30a. The blind end of the concave hole 30a is arranged in the low refractive index layer 32, so that light rays are emitted from the low refractive index layer 32 to the air when being emitted from the blind end of the concave hole 30a, the refractive index difference between the anti-reflection layer 30 and the air is smaller, the light rays can be emitted from the blind end of the concave hole 30a more easily, reflected light formed at the blind end of the concave hole 30a is reduced, the light emitting efficiency of the light emitting diode chip is further improved, and the brightness is improved.

As an example, the blind end of the recess 30a is located in the low refractive index layer 32 closest to the substrate 10 in fig. 1, and in other examples, the blind end of the recess 30a may be located in another low refractive index layer 32. The depth of the recess 30a can be determined according to the light emitting wavelength of the led chip, for example, by software simulation, the depth of the recess 30a can be determined appropriately, so that the light emitting brightness of the led chip can be improved better.

Alternatively, the cross-sectional area of the concave hole 30a is positively correlated with the distance from the cross-section to the substrate 10.

That is to say, the concave hole 30a may be in a horn shape, so that after the light is emitted from the hole wall of the concave hole 30a, the light is more easily reflected by the hole wall of the concave hole 30a and then emitted to the outside of the concave hole 30a, which is beneficial to further improving the brightness of the led chip. In the embodiment of the present disclosure, the hole wall of the concave hole 30a includes a side wall of the concave hole 30a and a bottom surface of the concave hole 30a, and the bottom surface of the concave hole 30a is an end surface of the blind end of the concave hole 30a.

As an example, the concave hole 30a has a truncated cone shape.

That is, the bottom surface of the concave hole 30a is a circular surface, and the side wall of the concave hole 30a is a tapered surface. The light emitted from the hole wall of the concave hole 30a can be emitted to the outside of the concave hole 30a by reflection of the tapered surface.

Illustratively, the diameter of the concave hole 30a is 3 μm to 5 μm. The diameter of recess 30a refers to the diameter at the opening of recess 30a, i.e., the diameter of the end of recess 30a distal from substrate 10. The larger the diameter of the concave hole 30a is, the larger the area of the side wall of the concave hole 30a is, and more light rays vertically emitted from the substrate 10 are reflected, so that light loss is generated, and the light emitting brightness is influenced. The small diameter of the concave hole 30a increases the difficulty of manufacturing.

In other examples, the recess 30a may have other shapes, for example, the cross-section of the recess 30a may be polygonal.

Optionally, the bottom surface of concave hole 30a is parallel to the surface of substrate 10 close to anti-reflection layer 30. The included angle formed by the side wall of the concave hole 30a and the bottom surface of the concave hole 30a is not less than the total reflection angle of the low refractive index layer 32.

When the light emitted from the led chip irradiates the bottom surface of the recess 30a, there is a possibility that the light is totally reflected, and the light that is not totally reflected is refracted from the bottom surface of the recess 30a and enters the recess 30a. The light refracted from the bottom surface of the concave hole 30a and entering the concave hole 30a partially irradiates the outside of the concave hole 30a directly, and also partially irradiates the side wall of the concave hole 30a, and is reflected by the side wall of the concave hole 30a for multiple times and then irradiates the outside of the concave hole 30a. When light is refracted at the bottom surface of the concave hole 30a, refraction is on the interface between the low refractive index layer 32 and the air, the total reflection angle of the included angle setting through the lateral wall of the concave hole 30a and the bottom surface of the concave hole 30a is not less than that of the low refractive index layer 32, can make the light emitted from the bottom surface of the concave hole 30a, more light can directly emit the concave hole 30a, irradiate the light on the lateral wall of the concave hole 30a, the concave hole 30a can also be emitted through less times of reflection, thereby reducing the light loss generated by reflecting the light by the lateral wall of the concave hole 30a, and being beneficial to further improving the light-emitting brightness of the light-emitting diode chip.

Illustratively, the low refractive index layer 32 is SiO ₂ And (3) a layer.

By means of SiO ₂ The layer is a low refractive index layer 32, siO ₂ The refractive index of (2) is low, and the difference of the refractive index with air is small, so that light rays can be favorably emitted from the bottom surface of the concave hole 30a.

In this example, the included angle between the sidewall of the recess 30a and the bottom of the recess 30a may be 46 ° to 50 °.

SiO ₂ The total reflection angle with the air is 46 degrees, so that the included angle formed by the side wall of the concave hole 30a and the bottom surface of the concave hole 30a is not less than 46 degrees.

Some of the light rays vertically emitted from the substrate 10 may irradiate the sidewalls of the recess 30a to be reflected, which may increase the number of times the light rays are reflected in the anti-reflection layer 30, thereby increasing the optical loss, and the larger the included angle between the sidewalls of the recess 30a and the bottom surface of the recess 30a is, the more the light rays irradiate the sidewalls of the recess 30a, which may increase the optical loss. In order to avoid the influence of too high light loss on the brightness of the light emitting diode chip, an included angle formed between the side wall of the concave hole 30a and the bottom surface of the concave hole 30a is set within 50 degrees.

As shown in fig. 1, the side of antireflection layer 30 close to substrate 10 is a high refractive index layer 31, and the side far from substrate 10 is a low refractive index layer 32.

One side of antireflection layer 30 close to substrate 10 is set as high refractive index layer 31, that is, the interface between antireflection layer 30 and substrate 10 is the interface between high refractive index layer 31 and substrate 10. The difference between the refractive index of the high refractive index layer 31 and the refractive index of the substrate 10 is large, and the refractive index of the high refractive index layer 31 is higher than that of the substrate 10, so that total reflection generated when light rays irradiate from the substrate 10 to the anti-reflection layer 30 can be avoided, and the brightness of the light emitting diode chip can be improved. For example, using TiO ₂ The layer is used as a high refractive index layer 31, and the side of the anti-reflection layer 30 close to the substrate 10 is set to be TiO ₂ The experimental test shows that the light-emitting efficiency of the light-emitting diode chip can be improved by about 0.5%.

As an example, in antireflection layer 30, high refractive index layer 31 closest to substrate 10 has a thickness of

If the thickness of the high refractive index layer 31 is too thick, the absorption of light emitted from the substrate 10 by the high refractive index layer 31 may be increased, which results in light loss, and is not favorable for improving the brightness of the led chip.

Illustratively, the high refractive index layer 31 may be TiO ₂ Layer, ga ₂ O ₂ Layer or SiN _x A layer.

Optionally, the ratio of the total area of the openings of the plurality of concave holes 30a to the area of the surface of the anti-reflection layer 30 far away from the substrate 10 is 10% to 20%.

The side walls of the concave holes 30a reflect a part of light rays vertically emitted from the surface of the substrate 10, which causes optical loss, and the larger the number of the concave holes 30a is, the larger the total area of the openings is, the larger the total area of the side walls of the concave holes 30a is, the more light rays vertically emitted from the substrate 10 irradiate the side walls of the concave holes 30a and are reflected, so that optical loss is formed, and the brightness of the light emitting diode chip is affected. Moreover, the excessive concave holes 30a may damage the structure of the anti-reflection layer 30, which is not favorable for improving the light emitting efficiency of the led chip and improving the brightness.

As shown in fig. 1, in the light emitting diode chip, the light emitting structure 20 includes an epitaxial structure 21 and an electrode 22, wherein the epitaxial structure 21 may include an N-type layer 212, a multi-quantum well layer 213, and a P-type layer 214 sequentially stacked on a substrate 10. The side of the epitaxial structure 21 remote from the substrate 10 has a recess that exposes the N-type layer 212. Illustratively, the N-type layer 212 includes an N-type GaN layer and the P-type layer 214 includes a P-type GaN layer. A u-type GaN layer 211 may be further disposed between the substrate 10 and the N-type GaN layer.

The electrode 22 includes a first electrode 221 and a second electrode 222, wherein the first electrode 221 is a P-electrode, is located on the P-type layer 214 and electrically connected to the P-type layer 214, and the second electrode 222 is an N-electrode, is located in the recess 21a and electrically connected to the N-type layer 212.

A transparent conductive layer 23 may be further disposed on the P-type layer 214, and the first electrode 221 may be located on the transparent conductive layer 23.

As shown in fig. 1, the light emitting structure 20 may further include a reflective layer 24, and the reflective layer 24 covers the surfaces of the epitaxial structure 21 and the electrode 22. The reflective layer 24 is for reflecting light emitted from the mqw layer 213 toward the substrate 10.

Illustratively, the reflective layer 24 may be a distributed bragg reflector DBR.

As shown in fig. 1, the light emitting structure 20 may further include a solder 25, the solder 25 being located on a surface of the reflective layer 24 remote from the substrate 10, the solder 25 being connected to the electrode 22.

The pad 25 may include a first pad 251 and a second pad 252, the first pad 251 being electrically connected to the first electrode 221, and the second pad 252 being electrically connected to the second electrode 222.

Fig. 2 is a flowchart of a method for manufacturing a light emitting diode chip according to an embodiment of the present disclosure. The method is used for preparing the light-emitting diode chip shown in fig. 1. As shown in fig. 2, the preparation method comprises:

in step S11, a light emitting structure 20 is formed on one surface of the substrate 10.

In step S12, an antireflection layer 30 is formed on the other surface of the substrate 10.

The antireflection layer 30 includes a plurality of high refractive index layers 31 and a plurality of low refractive index layers 32, and the plurality of high refractive index layers 31 and the plurality of low refractive index layers 32 are alternately stacked on the substrate 10.

In step S13, a plurality of concave holes 30a are formed on the surface of the anti-reflection layer 30 away from the substrate 10.

By providing the light emitting structure 20 on one surface of the substrate 10 and providing the antireflection layer 30 on the other surface, the antireflection layer 30 is formed by alternately laminating a plurality of high refractive index layers 31 and a plurality of low refractive index layers 32. The thicknesses of the high refractive index layer 31 and the low refractive index layer 32 are configured according to the light emitting wavelength of the light emitting structure 20, so that when light emitted by the light emitting structure 20 passes through the antireflection layer 30 and is reflected to the side of the substrate 10 at the interface between the antireflection layer 30 and the substrate 10 and the interface between the high refractive index layer 31 and the low refractive index layer 32, light reflected by different interfaces has a phase difference of odd times pi, and the phase difference is cancelled, so that light reflected back to the substrate 10 is reduced, the light emitting efficiency of the light emitting diode chip is improved, and the brightness is improved. Since the surface of the anti-reflection layer 30 away from the substrate 10 is further provided with the plurality of concave holes 30a, light can also be emitted from the hole walls of the concave holes 30a and is reflected outwards through the hole walls of the concave holes 30a, the concave holes 30a can enable a part of light to be emitted out of the anti-reflection layer 30 more quickly, the refraction and reflection times of the part of light in the anti-reflection layer 30 are reduced, the light loss is reduced, and the brightness of the light emitting diode chip is further improved.

Fig. 3 is a flowchart of a manufacturing process of a light emitting diode chip according to an embodiment of the present disclosure. Fig. 4 to 7 are schematic diagrams illustrating a manufacturing process of a light emitting diode chip according to an embodiment of the disclosure. The following describes a method for manufacturing the light emitting diode chip with reference to fig. 4 to 7. As shown in fig. 3, the preparation method includes:

in step S21, a substrate 10 is provided.

Alternatively, the substrate 10 is a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate 10 may be a flat substrate or a patterned substrate.

As an example, in the disclosed embodiment, the substrate 10 is a patterned sapphire substrate. The sapphire substrate is a common substrate, the technology is mature, and the cost is low.

In step S21, the sapphire substrate may be pretreated, placed in an MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber, and subjected to a baking process for 12 to 18 minutes.

In step S22, an N-type layer 212 is formed on one surface of the substrate 10.

Illustratively, the N-type layer 212 may be an N-type GaN layer.

Optionally, the growth temperature of the N-type layer 212 is 1000 ℃ to 1200 ℃; the growth pressure can be 50 Torr-200 Torr; the Si doping concentration in the N-type layer 212 may be 5 x 10 ¹⁸ cm ^-3 ～10 ²⁰ cm ^-3 (ii) a The thickness of the N-type layer 212 may be 1 μm to 4 μm.

In some examples, as shown in fig. 4, a u-type GaN layer 211 may also be formed on the substrate 10 before the N-type layer 212 is formed. Further, a buffer layer may be formed on the substrate 10 before the u-type GaN layer 211 is formed, and for example, the buffer layer may be an AlN buffer layer.

In step S23, a multiple quantum well layer 213 is formed on the N-type layer 212.

Illustratively, the multiple quantum well layer 213 includes a plurality of quantum well layers and quantum barrier layers alternately grown in a cycle. Alternatively, the number of periods in which the quantum well layers and the quantum barrier layers are alternately stacked may be 3 to 8. Illustratively, in the embodiments of the present disclosure, the number of periods in which the quantum well layers and the quantum barrier layers are alternately stacked is 5.

In step S24, a P-type layer 214 is formed on the multiple quantum well layer 213.

Illustratively, the P-type layer 214 may be a P-type GaN layer.

Alternatively, the growth temperature of the P-type layer 214 may be 850 ℃ to 1050 ℃; the growth pressure of the P-type layer 214 may be 100Torr to 600Torr.

Through steps S22 to S24, the epitaxial structure 21 is formed on the substrate 10.

In step S25, a groove 21a exposing the N-type layer 212 is formed on the P-type layer 214.

Illustratively, the groove 21a may be formed on the P-type layer 214 by means of plasma etching.

In step S26, a transparent conductive layer 23 is formed on the P-type layer 214.

As shown in fig. 5, a transparent conductive layer 23 is formed on the P-type layer 214.

Illustratively, the transparent conductive layer 23 may be formed by deposition using a transparent conductive material such as indium tin oxide ITO.

In step S27, the electrode 22 is formed.

As shown in fig. 5, the electrode 22 includes a first electrode 221 and a second electrode 222, wherein the first electrode 221 is a P electrode and is located on the transparent conductive layer 23, and the second electrode 222 is an N electrode and is located in the groove 21a and electrically connected to the N-type layer 212.

Illustratively, the electrode 22 may be deposited by metal sputtering.

In step S28, the reflective layer 24 is formed on the surfaces of the epitaxial structure 21 and the electrode 22.

As shown in fig. 6, a reflective layer 24 is formed on the epitaxial structure 21 and the electrode 22.

Illustratively, the reflective layer 24 may be a distributed bragg reflector DBR. A via hole may be formed on the reflective layer 24 at a position corresponding to the electrode 22 to facilitate connection of a subsequently formed solder joint 25 to the electrode 22.

In step S29, the solder 25 is formed on the reflective layer 24.

As shown in fig. 6, the pad 25 may include a first pad 251 and a second pad 252, the first pad 251 being electrically connected to the first electrode 221, and the second pad 252 being electrically connected to the second electrode 222. The solder bumps 25 may be deposited on the surface of the reflective layer 24 by metal sputtering.

Thus, the light emitting structure 20 is completed.

In step S30, an anti-reflection layer 30 is formed on the surface of the substrate 10 away from the light-emitting structure 20.

As shown in fig. 7, antireflection layer 30 includes a plurality of high refractive index layers 31 and a plurality of low refractive index layers 32. A plurality of high refractive index layers 31 and a plurality of low refractive index layers 32 are alternately stacked and disposed on the substrate 10.

Alternatively, the high refractive index layer 31 may be TiO ₂ Layer, ga ₂ O ₂ Layer or SiN _x Layer, the low refractive index layer 32 may be SiO ₂ And (3) a layer.

In step S31, a plurality of concave holes 30a are formed in the antireflection layer 30.

As shown in fig. 7, the recess 30a is a blind hole, and the blind end of the recess 30a is located in the low refractive index layer 32.

Illustratively, concave hole 30a may be formed on anti-reflection layer 30 by etching.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," "third," and similar terms in the description and claims of the present disclosure are not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprise" or "comprises", and the like, means that the element or item listed before "comprises" or "comprising" covers the element or item listed after "comprising" or "comprises" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, which may also change accordingly when the absolute position of the object being described changes.

The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.

Claims (10)

1. The utility model provides a light-emitting diode chip, characterized in that, includes substrate (10), light-emitting structure (20) and anti-reflection coating (30), light-emitting structure (20) with anti-reflection coating (30) are located respectively substrate (10) two opposite sides, anti-reflection coating (30) include a plurality of high refractive index layers (31) and a plurality of low refractive index layers (32), a plurality of high refractive index layers (31) with a plurality of low refractive index layers (32) are range upon range of setting in turn on substrate (10), anti-reflection coating (30) are kept away from the surface of substrate (10) has a plurality of shrinkage pools (30 a).

2. The light-emitting diode chip as claimed in claim 1, characterized in that the blind end of the recess (30 a) is located in the low-refractive-index layer (32).

3. The light-emitting diode chip as claimed in claim 2, characterized in that the cross-sectional area of the recess (30 a) is positively correlated with the distance of the cross-section from the substrate (10).

4. The light-emitting diode chip as claimed in claim 3, wherein the bottom surface of the recess hole (30 a) is parallel to the surface of the substrate (10) close to the anti-reflection layer (30), and the included angle formed by the side wall of the recess hole (30 a) and the bottom surface of the recess hole (30 a) is not less than the total reflection angle of the low refractive index layer (32).

5. The light-emitting diode chip as claimed in claim 3, characterized in that the recess (30 a) is in the shape of a circular truncated cone.

6. The light-emitting diode chip according to any one of claims 1 to 5, wherein a ratio of a total area of openings of the plurality of concave holes (30 a) to an area of a surface of the anti-reflection layer (30) away from the substrate (10) is 10% to 20%.

7. The light-emitting diode chip as claimed in any of claims 1 to 5, characterized in that the low-refractive-index layer (32) is SiO ₂ And (3) a layer.

8. The light-emitting diode chip according to any one of claims 1 to 5, wherein the side of the anti-reflection layer (30) close to the substrate (10) is the high refractive index layer (31), and the side far from the substrate (10) is the low refractive index layer (32).

9. The light-emitting diode chip as claimed in claim 8, wherein, of said anti-reflection layers (30), the high refractive index layer (31) closest to said substrate (10) has a thickness of

10. A preparation method of a light-emitting diode chip is characterized by comprising the following steps:

forming a light emitting structure (20) on one surface of a substrate (10);

forming an antireflection layer (30) on the other surface of the substrate (10), wherein the antireflection layer (30) comprises a plurality of high-refractive-index layers (31) and a plurality of low-refractive-index layers (32), and the plurality of high-refractive-index layers (31) and the plurality of low-refractive-index layers (32) are alternately stacked on the substrate (10);

and forming a plurality of concave holes (30 a) on the surface of the anti-reflection layer (30) far away from the substrate (10).

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