CN115985775A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, which are applied to the field of semiconductors. According to the manufacturing method of the semiconductor device, the plurality of nanowire plates which are transversely arranged are formed in the top semiconductor layer of the silicon-on-insulator substrate, and then the gate structure of the all-around gate is formed in the direction crossing the plurality of nanowire plates in the conventional mode of forming the gate structure of the fin field effect transistor. Because the invention forms the nanometer line board (channel) which is transversely arranged in the silicon substrate on the insulator containing the insulating buried layer, when the source electrode (source region) and the drain electrode (drain region) are formed in the subsequent steps, the inner isolating layer is not required to be formed firstly according to the existing forming mode of the all-around gate, and then the source electrode/the drain electrode are formed, thereby providing a novel method for forming the all-around gate, simplifying the forming steps of the all-around gate, and reducing the technical generation transition challenge from FinFET to GAA and the forming cost of the device.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for manufacturing the same.

Background

As the semiconductor industry enters nanometer technology process nodes, especially below 14nm technology nodes, the channel length of MOS devices is continuously reduced, and thus the short channel effect of MOS devices is particularly prominent. In order to solve the short channel effect of the MOS device, the MOS device is developed from a conventional planar structure to a three-dimensional structure such as a fin field effect transistor FinFET. The structure has the advantages that the fin type grid electrode is surrounded on three sides, the static control capability of the grid electrode is improved, and the short channel effect is reduced.

Further, as the semiconductor industry enters smaller nanotechnology process nodes, such as below 5nm technology nodes, and as the length of the MOS device channel is further reduced, new device structures and new materials need to be introduced to improve the device performance, so as to reduce the short channel effect of the MOS device. On one hand, semiconductor materials with high carrier mobility, such as germanium silicide SiGe, germanium Ge, III-V group materials and the like, become alternative materials of a channel, and the formation of the germanium silicide SiGe, the germanium Ge or the III-V group FinFET device on a silicon wafer is realized through an epitaxial process. On the other hand, new device structures such as Gate-All-Around-Gate (GAA) are becoming an alternative structure for hot-gates.

At present, the conventional method for forming a gate-all-around GAA structure is to form a channel on a silicon substrate by a plurality of nano-plates (nanotubes) stacked in a longitudinal direction, and then form a gate-all-around along a direction crossing the nano-plates stacked in the longitudinal direction. Then, an inner isolation layer is formed to protect the gate (full gate), and then the source and the drain are formed.

Disclosure of Invention

The present invention provides a method for forming a gate-all-around including laterally arranged nanowires based on a conventional fin field effect transistor forming process, so as to achieve the objective of reducing the technical generation transition challenge and cost.

In order to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor device, the method comprising:

providing a substrate, wherein the substrate is provided with a bottom semiconductor layer, an insulating buried layer and a top semiconductor layer which are sequentially stacked from bottom to top, and a plurality of first shallow trenches with the depth smaller than the thickness of the top semiconductor layer are formed in the top semiconductor layer;

forming a nanowire layer on the side wall of the first shallow groove;

etching the top semiconductor layers on two sides of the nanowire layer to the top surface of the insulating buried layer by taking the nanowire layer as a mask so as to form a plurality of discrete stacked structures;

forming a virtual grid and a side wall, wherein the virtual grid spans the plurality of stacked structures and surrounds the side walls and the top surfaces of partial areas of the stacked structures, and the side wall is positioned on the side wall of the virtual grid;

forming a source region and a drain region in the stacked structure at two sides of each virtual grid;

removing the virtual grid to form a first opening between the side walls, and removing the top semiconductor layer below the nanowire layer from the first opening to form a suspended nanowire channel in the first opening;

and sequentially forming a gate oxide layer and a metal gate in the first opening, wherein the gate oxide layer completely surrounds the nanowire channel, and the metal gate covers the surface of the gate oxide layer and at least fills the first opening.

Optionally, the substrate may be a silicon-on-insulator substrate, the material of the bottom semiconductor layer and the material of the top semiconductor layer include silicon, and the material of the buried insulating layer includes silicon dioxide.

Optionally, the nanowire layer material may include one or more combinations of silicon, germanium, and group III-V materials.

Optionally, the step of forming a nanowire layer on the sidewall of the first shallow trench may include:

epitaxially growing a nanowire layer on the top semiconductor layer and the surface of the first trench;

and selectively removing the nanowire layer covered on the bottom of the first shallow trench and the top surface of the top semiconductor layer by adopting a dry etching process.

Optionally, the step of forming a source region and a drain region in the stacked structure at two sides of each of the dummy gates may include:

removing the nanowire layer in the stacked structure of partial areas on two sides of the virtual grid and at least part of the top semiconductor layer below the nanowire layer so as to form second shallow trenches in the stacked structure on two sides of the virtual grid respectively;

and depositing a stress material layer in the second shallow trench, so that the stress material layer at least fills the second shallow trench to form the source region and the drain region.

Optionally, the stress material layer may include at least one of silicon, silicon phosphide, silicon carbon phosphide, and germanium silicide. Specifically, when the semiconductor device is an NMOS transistor, the stress material layer may include silicon; when the semiconductor device is a PMOS transistor, the stress material layer may include germanosilicide.

Optionally, the step of removing the dummy gate to form the first opening between the sidewalls may include:

depositing an insulating medium layer until the insulating medium layer covers the source region, the drain region and the virtual grid;

flattening the insulating dielectric layer and further exposing the top surface of the virtual grid;

and removing the virtual grid by adopting a combined process of dry etching and wet etching.

Optionally, the step of forming the gate oxide layer in the first opening may include:

performing a wet cleaning process or a thermal oxidation process on the substrate to form a first oxide layer on the bottom of the first opening and the top and sidewalls of the void located below the nanowire channel;

forming a second oxide layer on the first opening and a surface of the first oxide layer in the void by an atomic layer deposition process to form the gate oxide layer composed of the first oxide layer and the second oxide layer.

Optionally, the thickness of the first oxide layer may be 0.6nm to 4nm, and the thickness of the second oxide layer may be 1.5nm to 2nm. Specifically, when the semiconductor device is a core device, the thickness of the first oxide layer may be 0.6nm to 1nm, and the thickness of the second oxide layer may be 1.5nm to 2nm; when the semiconductor device is an input/output device, the thickness of the first oxide layer is 2nm to 4nm, and the thickness of the second oxide layer may be 1.5nm to 2nm.

Based on the manufacturing method of the semiconductor device, the invention also provides the semiconductor device manufactured by the manufacturing method, which specifically comprises the following steps:

the substrate is provided with a bottom semiconductor layer, an insulating buried layer and a top semiconductor layer which are sequentially stacked from bottom to top, and a plurality of transversely-arranged discrete nano plates are formed in the top semiconductor layer along the direction parallel to the surface of the substrate;

the gate oxide layer completely surrounds the nanowire channel, and the metal grid covers the surface of the gate oxide layer.

Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:

according to the manufacturing method of the semiconductor device, the plurality of nanowire plates which are transversely arranged are formed in the top semiconductor layer of the silicon-on-insulator substrate, and then the gate structure of the all-around gate is formed in the direction crossing the plurality of nanowire plates in the conventional mode of forming the gate structure of the fin field effect transistor. Because the invention forms the nanometer line board (channel) which is transversely arranged in the silicon substrate on the insulator containing the insulating buried layer, when the source electrode (source region) and the drain electrode (drain region) are formed in the subsequent steps, the inner isolating layer is not required to be formed firstly according to the existing forming mode of the all-around gate, and then the source electrode/the drain electrode are formed, thereby providing a novel method for forming the all-around gate, simplifying the forming steps of the all-around gate, and reducing the technical generation transition challenge from FinFET to GAA and the forming cost of the device.

Drawings

FIG. 1 is a flow chart of a method of fabricating a semiconductor device according to the present invention;

FIGS. 2a to 2j are schematic structural diagrams of a semiconductor device in a manufacturing process according to an embodiment of the present invention;

wherein the reference numbers are as follows:

100-a bottom semiconductor layer; 110-insulating buried layer;

120/120' -top semiconductor layer; 130/130' -nanowire layer;

101-a first shallow trench; 140-polysilicon layer of dummy gate;

150-a hard mask layer; 160/160' -side wall;

an S-source region; a D-drain electrode;

102-a second shallow trench; 103-a first opening;

104-a void; 170-high K dielectric layer;

180-metal gate; 251-a stacked structure;

261-a dummy gate; 171-a first oxide layer;

172-second oxide layer.

Detailed Description

As mentioned in the background, at present, as the semiconductor industry enters smaller nanotechnology process nodes, such as below 5nm technology nodes, and as the length of the MOS device channel is further reduced, a new device structure and a new material need to be introduced to improve the device performance, so as to reduce the short channel effect of the MOS device. On one hand, semiconductor materials with high carrier mobility, such as germanium silicide SiGe, germanium Ge, III-V group materials and the like, become alternative materials of a channel, and the formation of the germanium silicide SiGe, the germanium Ge or the III-V group FinFET device on a silicon wafer is realized through an epitaxial process. On the other hand, new device structures such as Gate-All-Around-Gate (GAA) are becoming an alternative structure for hot-gates.

At present, the conventional method for forming a gate-all-around GAA structure is to form a channel on a silicon substrate by a plurality of nano-plates (nanotubes) stacked in a longitudinal direction, and then form a gate-all-around along a direction crossing the nano-plates stacked in the longitudinal direction. Then, an inner isolation layer is formed to protect the gate (full gate), and then the source and the drain are formed.

Therefore, the invention provides a semiconductor device and a manufacturing method thereof, and provides a method for forming a full-ring gate comprising transversely arranged nanowires on the basis of the existing fin field effect transistor forming process, so as to achieve the purpose of reducing the technical generation transition challenge and the cost.

Referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Specifically, the manufacturing method of the semiconductor device comprises the following steps:

step S100, providing a substrate, wherein the substrate is provided with a bottom semiconductor layer, an insulating buried layer and a top semiconductor layer which are sequentially stacked from bottom to top, and a plurality of first shallow trenches with the depth smaller than the thickness of the top semiconductor layer are formed in the top semiconductor layer.

Step S200, forming a nanowire layer on the sidewall of the first shallow trench.

And step S300, taking the nanowire layer as a mask, and etching the top semiconductor layers on two sides of the nanowire layer to the top surface of the insulating buried layer to form a plurality of discrete stacked structures.

Step S400, forming a dummy gate and a sidewall, where the dummy gate spans over the plurality of stacked structures and surrounds the sidewalls and the top surface of the partial region of the stacked structures, and the sidewall is located on the sidewall of the dummy gate.

Step S500, forming a source region and a drain region in the stacked structure at two sides of each of the dummy gates.

Step S600, removing the dummy gate to form a first opening between the sidewalls, and removing the top semiconductor layer below the nanowire layer from the first opening to form a suspended nanowire channel in the first opening.

And S700, sequentially forming a gate oxide layer and a metal grid in the first opening, wherein the gate oxide layer completely surrounds the nanowire channel, and the metal grid covers the surface of the gate oxide layer and at least fills the first opening.

In other words, in the method for manufacturing a semiconductor device according to the present invention, a plurality of nanowire plates arranged in a lateral direction are formed in a top semiconductor layer of a silicon-on-insulator substrate, and then a gate structure of a gate all around is formed in a direction crossing the plurality of nanowire plates by using a conventional method for forming a gate structure of a fin field effect transistor. Because the invention forms the nanometer line board (channel) which is transversely arranged in the silicon substrate on the insulator containing the insulating buried layer, when the source electrode (source region) and the drain electrode (drain region) are formed in the subsequent steps, the inner isolating layer is not required to be formed firstly according to the existing forming mode of the all-around gate, and then the source electrode/the drain electrode are formed, thereby providing a novel method for forming the all-around gate, simplifying the forming steps of the all-around gate, and reducing the technical generation transition challenge from FinFET to GAA and the forming cost of the device.

The following describes a method for manufacturing a semiconductor device according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided for the purpose of facilitating and clearly illustrating embodiments of the present invention.

Fig. 2a to 2j are schematic structural diagrams of a semiconductor device in a manufacturing process according to an embodiment of the invention.

In step S100, referring to fig. 2a in particular, a substrate is provided, the substrate has a bottom semiconductor layer 100, an insulating buried layer 110 and a top semiconductor layer 120 stacked in sequence from bottom to top, and a plurality of first shallow trenches 101 with a depth smaller than the thickness of the top semiconductor layer 120 are formed in the top semiconductor layer 120. Wherein the substrate is used to provide a platform for operation of subsequent processes to produce the MOSFET device. Illustratively, the substrate may be a silicon-on-insulator substrate, the material of the bottom semiconductor layer 100 and the material of the top semiconductor layer 120 may include silicon, and the material of the buried insulating layer 110 may include silicon dioxide.

In this embodiment, a silicon-on-insulator substrate may be provided, and then a patterned photoresist layer (not shown) is formed on the surface of the silicon-on-insulator substrate, and the top semiconductor layer 120 in the silicon-on-insulator substrate is etched, so as to form a plurality of first shallow trenches 101 with a trench depth equal to the height of the nanowire layer 130' to be formed in the subsequent step in the top semiconductor layer 120. Since the height of the nanowire layer 130 'is the same as the depth of the first trench 101 formed with a constant depth in the embodiment of the present invention, the perimeter of the nanowire layer 130' can be adjusted by controlling the thickness of the thin film when the height of the nanowire layer is constant, thereby adjusting the performance of the MOSFET device. Wherein the perimeter of the nanowire layer is equal to the sum of the height of the nanowire layer and its width multiplied by 2.

In step S200, referring specifically to fig. 2c, a nanowire layer 130' is formed on the sidewall of the first shallow trench 101. Wherein the material of the nanowire layer 130' may include one or more of silicon, germanium, and group III-V materials. Illustratively, in the embodiment of the present invention, the material of the nanowire layer 130' is silicon.

In this embodiment, after the plurality of first shallow trenches 101 are formed in step S100, a nanowire layer 130 with a certain thickness is formed on the substrate by using a chemical vapor deposition epitaxy process LPCVD (as shown in fig. 2 b), and then etched, so as to form a nanowire layer 130' only remaining on the inner walls of the first shallow trenches 101. The higher the etching selectivity of the etching gas used for etching to the top semiconductor layer 120, the better, specifically, the range of the etching selectivity is at least greater than 10.

Specifically, referring to fig. 2b, in an embodiment of the present invention, a specific manner for forming the nanowire layer 130' is provided, which may include the following steps:

first, a nanowire layer is epitaxially grown on the surface of the top semiconductor layer 120 and the first trench 101;

next, the nanowire layer 130 covering the bottom and the top of the first shallow trench 101 is selectively removed by a dry etching process.

In step S300, referring to fig. 2d specifically and fig. 2c at the same time, the nanowire layer 130 'shown in fig. 2c is used as a mask, and the top semiconductor layers 120 on both sides of the nanowire layer 130' are etched to the top surface of the buried insulating layer 110, so as to form a plurality of discrete stacked structures 251 shown in fig. 2 d. The stacked structure 251 includes a nanowire layer 130 ″ and a top semiconductor layer 120', and the nanowire layer 130 ″ is obtained by partially removing the nanowire layer 130' in the process of using the nanowire layer 130 'as a mask and etching the top semiconductor layer 120 on both sides of the nanowire layer 130' to the top surface of the insulating buried layer 110.

It should be noted that, the proportional relationship of the pattern included in each drawing referred in the embodiment of the present invention does not have a strict one-to-one correspondence with the proportional relationship of the patterns included in other drawings, and each of the patterns is only used to assist in explaining the inventive step of the method for manufacturing the semiconductor device provided by the present invention, for example, in order to more clearly show the plurality of discrete stacked structures 251 obtained in step S300, the present invention enlarges the pattern size of the nanowire layer 130' included in fig. 2c, and obtains the stacked structure 251 included in fig. 2d correspondingly, that is, the pattern included in the drawing provided by the present invention is only used to define the positional relationship, not the dimensional relationship, of each film layer in the pattern.

In step S400, referring to fig. 2e specifically and fig. 2f at the same time, a dummy gate 261 and a sidewall 160 are formed, where the dummy gate 261 spans over the multiple stacked structures 251 and surrounds sidewalls and top surfaces of partial regions of the stacked structures 251, and the sidewall 160 is located on the sidewalls of the dummy gate 261.

In this embodiment, after forming the stacked structures 251, a polysilicon gate layer 140 and a hard mask layer 150 may be sequentially deposited on the surface of the substrate, and then, the polysilicon gate layer 140 and the hard mask layer 150 are etched along the direction AA' shown in fig. 2e to form a dummy gate 261 crossing the stacked structures 251, as shown in fig. 2 e. Then, the sidewall 160 for protecting the dummy gate 261 is further formed on the surface of the dummy gate 261 and the surface of the nanowire layer 130 ″ exposed at two sides thereof by using an atomic layer deposition process ALD, as shown in fig. 2 f. Fig. 2f is a schematic three-dimensional structure corresponding to the step shown in fig. 2e after the step of forming the dummy gate 261 and then forming the sidewall 160.

In step S500, referring specifically to fig. 2g and 2h, a source region S and a drain region D in the stacked structure 251 located at both sides of each of the dummy gates 261 are formed.

In this embodiment, at least a portion of the top semiconductor layer 120' under the nanowire layer 130 "and the nanowire layer 130" in the stacked structure 251 located in the partial regions on both sides of the dummy gate 261 (140 and 150) may be removed first to form second shallow trenches 102 in the stacked structure on both sides of the dummy gate, respectively; then, a stress material layer is deposited in the second shallow trench 102, so that the stress material layer at least fills the second shallow trench 102 to form the source region S and the drain region D. Wherein the stress material layer may include at least one of silicon, silicon phosphide, silicon carbon phosphide, and germanium silicide.

It should be noted that what kind of material of the stress material layer is filled in the second shallow trench 102 is determined according to the kind of the device formed on the substrate. For example, if the device formed on the substrate is an NMOS transistor, the material of the stress material layer epitaxially grown in the second shallow trench 102 may be silicon, and if the device formed on the substrate is a PMOS transistor, the material of the stress material layer epitaxially grown in the second shallow trench 102 may be germanium silicide. Of course, for different devices, the stress material layer filled in the source trench and the drain trench may also be other materials that can provide tensile stress (NMOS transistor) or compressive stress (PMOS transistor) to the device channel, which is not specifically limited in the present invention.

In step S600, referring to fig. 2i specifically, the dummy gate 261 is removed to form a first opening 103 between the sidewalls 160, and the top semiconductor layer 120' under the nanowire layer 130 ″ is removed from the first opening 103 to form a suspended nanowire channel S-D in the first opening 103.

In this embodiment, the top semiconductor layer 120' under the nanowire layer 130 ″ is also removed while the first opening 103 is formed after the dummy gate 261 is removed, thereby forming the void 104. Then, a metal gate is filled in the first opening 103 and the gap 104, so that a full gate loop of the GAA device can be formed.

Specifically, a specific implementation manner of removing the dummy gate 261 to form the first opening 103 between the sidewalls 160 is provided in the embodiment of the present invention, which may include the following steps:

firstly, depositing an insulating dielectric layer (not shown) until the insulating dielectric layer covers the source region S, the drain region D and the dummy gate 261;

then, the insulating dielectric layer is planarized, and the top surface of the dummy gate 261 is further exposed;

secondly, a combined process of dry etching and wet etching is adopted to remove the dummy gate 261.

In step S700, specifically referring to fig. 2j, a gate oxide layer 170 and a metal gate 180 are sequentially formed in the first opening 103, where the gate oxide layer 170 completely surrounds the nanowire channel S-D, and the metal gate 180 covers the surface of the gate oxide layer and at least fills the first opening 103.

In this embodiment, when the second shallow trench 102 is formed by etching in the above step, the top semiconductor layer 120' with a partial thickness is still remained at the bottom of the second shallow trench 102, so as to avoid the problem of leakage current between a metal gate and a source drain which are formed subsequently, and therefore, before forming the metal gate, one or more oxide layers may be formed in the first opening 103 and the gap 104 for isolating the metal gate from the source drain.

Optionally, a specific implementation manner of forming the gate oxide layer 170 in the first opening 103 is provided in the embodiment of the present invention, and may include the following steps:

first, a wet cleaning process or a thermal oxidation process is performed on the substrate to form a first oxide layer 171 on the bottom of the first opening 103 and the top and sidewalls of the void 104 located under the nanowire channel S-D;

next, a second oxide layer 172 is formed on the surface of the first oxide layer 171 in the first opening 103 and the void 104 by an atomic layer deposition process to form the gate oxide layer 170 composed of the first oxide layer 171 and the second oxide layer 172.

In this embodiment, the thickness of the first oxide layer 171 may be 0.6nm to 4nm, and specifically, the thickness of the first oxide layer 171 formed to constitute the gate oxide layer 170 is different for different devices on a chip according to different actual requirements. Illustratively, if the device formed on the semiconductor substrate 100 is a core device, the thickness of the first oxide layer 171 may range from 0.6nm to 1nm, and if the device formed on the semiconductor substrate 100 is an input-output device, the thickness of the first oxide layer 171 may range from 2nm to 4nm. The thickness of the second oxide layer 172 may be 1.5nm to 2nm. For example, in the embodiment of the present invention, the first oxide layer 171 may be silicon dioxide, and the second oxide layer 17 may be hafnium dioxide, or zirconium dioxide, or lanthanum oxide.

It should be noted that the gate oxide layer 170 may be only one oxide layer, or may be a stack of multiple oxide layers provided in the embodiment of the present invention, and the material of each layer may be the material of the oxide layer provided in the present invention, or may be any other material that can isolate the source, the drain, and the gate of the device, and the present invention is not limited in particular.

Further, the present invention provides a semiconductor device based on the manufacturing method of the semiconductor device as described above, including:

a substrate having a bottom semiconductor layer 100, a buried insulating layer 110, and a top semiconductor layer 120 'stacked in this order from bottom to top, and a plurality of laterally arranged discrete nanoplates 130 "formed within the top semiconductor layer 120' in a direction parallel to the surface of the substrate;

the gate oxide layer 170 completely surrounds the nanowire channel S-D, and the metal gate 180 covers the surface of the gate oxide layer 170 and at least fills the first opening.

In summary, in the method for manufacturing a semiconductor device according to the present invention, a plurality of nanowire plates arranged in a lateral direction are formed in a top semiconductor layer of a soi substrate, and then a gate structure of a gate all-around is formed along a direction crossing the plurality of nanowire plates by using a conventional method for forming a gate structure of a finfet. Because the invention forms the nanometer line board (channel) which is transversely arranged in the silicon substrate on the insulator containing the insulating buried layer, when the source electrode (source region) and the drain electrode (drain region) are formed in the subsequent steps, the inner isolating layer is not required to be formed firstly according to the existing forming mode of the all-around gate, and then the source electrode/the drain electrode are formed, thereby providing a novel method for forming the all-around gate, simplifying the forming steps of the all-around gate, and reducing the technical generation transition challenge from FinFET to GAA and the forming cost of the device.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the present invention.

Further, it will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of exemplary embodiments according to the present invention.

For ease of description, spatially relative terms such as "below … …", "above … …", "below", "above … …", "above", "upper" and "lower" and the like may be used herein to describe the spatial positional relationship of one element or feature to other elements or features as shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below … …" may include both orientations of "above … …" and "below … …". The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular is intended to include the plural unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. Any person skilled in the art can make any equivalent substitutions or modifications on the technical solutions and technical contents disclosed in the present invention without departing from the scope of the technical solutions of the present invention, and still fall within the protection scope of the present invention without departing from the technical solutions of the present invention.

Claims (9)

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate, wherein the substrate is provided with a bottom semiconductor layer, an insulating buried layer and a top semiconductor layer which are sequentially stacked from bottom to top, and a plurality of first shallow trenches with the depth smaller than the thickness of the top semiconductor layer are formed in the top semiconductor layer;

forming a nanowire layer on the side wall of the first shallow groove;

etching the top semiconductor layers on two sides of the nanowire layer to the top surface of the insulating buried layer by taking the nanowire layer as a mask so as to form a plurality of discrete stacked structures;

forming a virtual grid and a side wall, wherein the virtual grid spans the plurality of stacked structures and surrounds the side wall and the top surface of partial area of the stacked structures, and the side wall is positioned on the side wall of the virtual grid;

forming a source region and a drain region in the stacked structure at two sides of each virtual grid;

removing the virtual grid to form a first opening between the side walls, and removing the top semiconductor layer below the nanowire layer from the first opening to form a suspended nanowire channel in the first opening;

and sequentially forming a gate oxide layer and a metal gate in the first opening, wherein the gate oxide layer completely surrounds the nanowire channel, and the metal gate covers the surface of the gate oxide layer and at least fills the first opening.

2. The method for manufacturing the semiconductor device according to claim 1, wherein the substrate is a silicon-on-insulator substrate, the material of the bottom semiconductor layer and the top semiconductor layer includes silicon, and the material of the buried insulating layer includes silicon dioxide; the nanowire layer material comprises one or more of silicon, germanium, and a combination of group III-V materials.

3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a nanowire layer on the sidewall of the first shallow trench comprises:

epitaxially growing a nanowire layer on the top semiconductor layer and the surface of the first trench;

and selectively removing the nanowire layer covered on the bottom of the first shallow trench and the top surface of the top semiconductor layer by adopting a dry etching process.

4. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a source region and a drain region in the stacked structure on both sides of each of the dummy gates comprises:

removing the nanowire layer in the stacked structure in partial areas on two sides of the virtual grid electrode and at least part of the top semiconductor layer below the nanowire layer so as to form second shallow trenches in the stacked structure on two sides of the virtual grid electrode respectively;

and depositing a stress material layer in the second shallow trench, so that the stress material layer at least fills the second shallow trench to form the source region and the drain region.

5. The method according to claim 4, wherein when the semiconductor device is an NMOS transistor, the stress material layer comprises silicon; when the semiconductor device is a PMOS tube, the stress material layer comprises germanium silicide.

6. The method for manufacturing the semiconductor device according to claim 1, wherein the step of removing the dummy gate to form a first opening between the sidewalls comprises:

depositing an insulating medium layer until the insulating medium layer covers the source region, the drain region and the virtual grid;

flattening the insulating medium layer and further exposing the top surface of the virtual grid;

and removing the virtual grid by adopting a combined process of dry etching and wet etching.

7. The manufacturing method of a semiconductor device according to claim 1, wherein the step of forming the gate oxide layer in the first opening comprises:

performing a wet cleaning process or a thermal oxidation process on the substrate to form a first oxide layer on the bottom of the first opening and the top and sidewalls of the void under the nanowire channel;

forming a second oxide layer on the surface of the first oxide layer in the first opening and the void by an atomic layer deposition process to form the gate oxide layer composed of the first oxide layer and the second oxide layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein when the semiconductor device is a core device, the first oxide layer has a thickness of 0.6nm to 1nm, and the second oxide layer has a thickness of 1.5nm to 2nm; when the semiconductor device is an input/output device, the thickness of the first oxide layer is 2nm to 4nm, and the thickness of the second oxide layer is 1.5nm to 2nm.

9. A semiconductor device manufactured by the manufacturing method according to any one of claims 1 to 8, comprising:

the substrate is provided with a bottom semiconductor layer, an insulating buried layer and a top semiconductor layer which are sequentially stacked from bottom to top, and a plurality of transversely arranged discrete nano plates are formed in the top semiconductor layer along the direction parallel to the surface of the substrate;

the gate oxide layer completely surrounds the nanowire channel, and the metal grid covers the surface of the gate oxide layer.

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