CN1159849C

CN1159849C - Digital phase detecting method and its device

Info

Publication number: CN1159849C
Application number: CNB991270401A
Authority: CN
Inventors: 陈晗颖; 尹朝晖; 潘炳松; 张文
Original assignee: Alcatel Lucent Shanghai Bell Co Ltd
Current assignee: Nokia Shanghai Bell Co Ltd
Priority date: 1999-12-29
Filing date: 1999-12-29
Publication date: 2004-07-28
Anticipated expiration: 2019-12-29
Also published as: CN1302119A

Abstract

The present invention relates to a digital phase detecting method and a device thereof. The method comprises the following procedures: sample time is firstly determined, the rising edge time of two reference clock signals in need of phase detection is determined for many times within the sample time, multiple phase meter values which are determined by the two reference clock signals are obtained by calculation, and integral values are stored after the phase meter values are integrated; N integral values are then obtained after the whole process is repeated for N times; the accurate phase difference of the two reference clock signals is obtained after the N integral values are smoothened and filtered. The present invention has high phase detection accuracy, improves the property of dither filtering, and can filter ghost frequencies during sampling.

Description

A kind of digital phase detecting method and device thereof

The present invention relates to a kind of digital phase detecting method and device thereof.

Phase discriminator is a kind of phase comparison device, is mainly used in the phase-locked loop.Phase discriminator can be divided into simulation phase discriminator and digital phase discriminator two big classes, the integrated phase discriminator of present monolithic, as digital phase frequency detector MC4044, MC12040, CD4046 etc., with conspicuous characteristics, superior performance, but, be difficult in the higher phase-locked loop of required precision because output amplitude is little, discriminator sensitivity is low.For the phase-locked loop in the synchronous clock supply system, need a kind of high-precision digital phase discriminator, and can be neatly catching soon, follow the tracks of, changing between the maintenance, these four kinds of states of free-running operation, if directly use the integrated phase discriminator of above-mentioned monolithic, be difficult to reach above-mentioned requirements.

The object of the present invention is to provide a kind of digital phase detecting method and device thereof, it can accurately identify the phase difference of two reference clock signals, and has improved the shake filtering performance of signal.

In order to realize above-mentioned goal of the invention, a kind of digital phase detecting method that is provided, it is characterized in that it comprises the following steps: at first to determine a sampling time, need in this sampling time interval, repeatedly to determine phase demodulation two reference clock signals rising edge constantly, calculate a plurality of phasometer numerical value of in this sampling time interval, determining by two reference clock signals, directly determine simultaneously the leading or lagged relationship of two reference signals, a plurality of leading or lagging phase difference count values are carried out integration, and preserve integrated value; Said process N time repeatedly draws N integrated value then; To N integrated value carry out smoothly, Filtering Processing, draw the phase difference of accurate two reference clock signals.

In order to realize above-mentioned goal of the invention, a kind of digital phase demodulation apparatus that is provided, it comprises: two triggers receive the outside reference clock signal and the reset signal of reseting logic unit respectively, determine the initial moment of this reference clock signal rising edge, and output set pulse signal; The reseting logic unit receives the set pulse signal respectively from two triggers, carry out logical process, and returns reset signal to two triggers; Frequency unit receives the central clock signal from the outside, and through the prime number frequency division, output is than the counting clock signal of the high hundred times of frequency of described external reference clock signal; Leading counter receives the counting clock signal of frequency unit and the set pulse signal of a trigger, calculates the phase place leading time of two described reference clock signals, exports leading count value; Hysteresis counter receives the counting clock signal of frequency unit and the set pulse signal of another trigger, the phase lag time of calculating two described reference clock signals, lag output count value; CPU, receive leading, the hysteresimeter numerical value of outside central clock signal and leading counter, hysteresis counter, in the sampling time, carry out phase integral, just go to read through the count value behind the counting repeatedly every certain sampling time interval, then to a plurality of count values carry out smoothly, Filtering Processing, calculate the real phase difference of two reference clock signals, and output, reset signal also exported simultaneously to leading counter and hysteresis counter.

Owing to adopted above-mentioned technical solution, promptly in a set time, carry out phase integral, therefore greatly reduce the burden of CPU, and the precision of phase discrimination height, phase demodulation resolution can reach 10ns.This in addition digital phase demodulation apparatus also provides a low pass filter, has unlimited decay on the harmonic component of sampling rate, so it has also improved the shake filtering performance, and the parasitic frequency in the energy filtering sampling.

The present invention is further illustrated below in conjunction with drawings and Examples.

Fig. 1 is the circuit arrangement structured flowchart of a kind of digital phase demodulation apparatus of the present invention.

As shown in Figure 1, it comprises two triggers 1, reseting logic unit 2, leading counter 3, hysteresis counter 4, CPU 5 and frequency unit 6.

Two triggers 1,2 receive reset signal from the reseting logic unit, and respectively from outside reception reference clock signal S, R, when receiving reset signal, two triggers 1 are reset, when the rising edge of S signal arrives, trigger 1 set that links to each other with the S signal, and set pulse signal T1 outputed to leading counter 3 and reseting logic unit 2, when the rising edge of R signal arrives, the also set of trigger 1 that links to each other with the R signal, and set pulse signal T2 outputed to hysteresis counter 4 and reseting logic unit 2;

Reseting logic unit 2 receives set pulse signal T1, T2 from two triggers 1, and when all effective as if set pulse signal T1, the T2 of 1 output of two triggers, the reseting logic unit produces reset signal, and reset signal is turned back to two triggers 1;

Frequency unit 6 receives and two the incoherent central clock signal of reference clock signal CC from the outside, and through the prime number frequency division, output frequency is than the counting clock signal of reference clock signal S, the high hundred times of R;

Leading counter 3, from frequency unit 6 and a trigger 1 difference count pick up clock signal and set pulse signal T1, on behalf of reference clock signal S, the pulse duration of set pulse signal T1 be ahead of the leading time of R, during this period of time, leading counter 3 usefulness counting clock signals add counting;

Hysteresis counter 4, from frequency unit 6 and another trigger 1 difference count pick up clock signal and set pulse signal T2, on behalf of reference clock signal S, the pulse duration of set pulse signal T2 lag behind the lag time of R, during this period of time, hysteresis counter 4 usefulness counting clock signals add counting;

CPU 5, receive leading, hysteresimeter numerical value from leading counter 3, hysteresis counter 4 respectively, and simultaneously from outside reception central clock signal CC, in the sampling time, carry out phase integral, just go to read through the count value behind the counting repeatedly every certain sampling time interval, then to a plurality of count values carry out smoothly, Filtering Processing, the real phase difference of two reference signals of calculating, phase difference output, and simultaneously reset signal is exported to leading counter and hysteresis counter.

Claims

1. a digital phase detecting method is characterized in that it comprises the following steps:

At first determine a sampling time, need in this sampling time interval, repeatedly to determine phase demodulation two reference clock signals rising edge constantly, calculate a plurality of phasometer numerical value of in this sampling time interval, determining by two reference clock signals, directly determine simultaneously the leading or lagged relationship of two reference signals, a plurality of leading or lagging phase difference count values are carried out integration, and preserve integrated value;

Said process N time repeatedly draws N integrated value then;

To N integrated value carry out smoothly, Filtering Processing, draw the phase difference of accurate two reference clock signals.

2. digital phase demodulation apparatus is characterized in that it comprises:

Two triggers receive the outside reference clock signal and the reset signal of reseting logic unit respectively, determine the initial moment of this reference clock signal rising edge, and output set pulse signal;

The reseting logic unit receives the set pulse signal respectively from two triggers, carry out logical process, and returns reset signal to two triggers;

Frequency unit receives the central clock signal from the outside, and through the prime number frequency division, output is than the counting clock signal of the high hundred times of frequency of described external reference clock signal;

Leading counter receives the counting clock signal of frequency unit and the set pulse signal of a trigger, calculates the phase place leading time of two described reference clock signals, exports leading count value;

Hysteresis counter receives the counting clock signal of frequency unit and the set pulse signal of another trigger, the phase lag time of calculating two described reference clock signals, lag output count value;

CPU, receive leading, the hysteresimeter numerical value of outside central clock signal and leading counter, hysteresis counter, in the sampling time, carry out phase integral, just go to read through the count value behind the counting repeatedly every certain sampling time interval, then to a plurality of count values carry out smoothly, Filtering Processing, calculate the real phase difference of two reference clock signals, and output, reset signal also exported simultaneously to leading counter and hysteresis counter.