CN115983177A - Transistor model establishing method based on artificial neural network - Google Patents
Transistor model establishing method based on artificial neural network Download PDFInfo
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Abstract
The invention relates to a transistor model building method based on an artificial neural network, which comprises the steps of obtaining the process type of a transistor; establishing a transistor initial model based on the transistor process type, wherein the transistor initial model comprises a plurality of ports; applying a direct current voltage input signal to each port of the transistor initial model, and extracting a direct current output signal of each port of the transistor initial model; and fitting the direct-current voltage input signal and the direct-current output signal through a preset artificial neural network to obtain a transistor direct-current model. The present invention uses an artificial neural network to capture the relationship between the inputs and outputs (current and voltage) of a transistor model. Both dc and ac signals are considered in the model. The transistor can be modeled with high precision, and the simulation precision of the transistor can be remarkably improved under the condition of keeping higher simulation speed.
Description
Technical Field
The invention relates to the technical field of circuit layout, in particular to a transistor model establishing method based on an artificial neural network.
Background
Transistors are key components of analog integrated circuits, and their compact models play an important role in integrated circuit design. The precision of the compact model has a great influence on the design of the analog circuit. Several versions of the BSIM model have been developed in decades as a mainstream transistor model. Traditional compact transistor models, such as BSIM, PSP, and HiSim, are physically driven models and are widely used in the industry.
However, as moore's law develops, the mainstream compact model of BSIM faces challenges. As transistor dimensions continue to shrink, the impact of small-scale effects (e.g., short channel effects) increases, making the device physical characteristics of the transistors more complex, thereby making the BSIM model more difficult to fit. Also with the ever shrinking process, new transistor processes are being developed, which requires updating and even re-developing the corresponding transistor models. For example, the advent of new transistor device structures (e.g., tunneling field effect transistors and negative capacitance field effect transistors) has not been modeled using conventional BSIM models. In addition, the traditional physical driving model is made to depend on the experience of engineers to a great extent as the formula becomes more and more complex and the automated mold lifting process is lacked.
Look-up tables (LUTs) have been proposed as an alternative to the physical model, in comparison to the conventional compact transistor physical model. However, some problems still exist with the LUT model. First, LUT models require extensive simulation of the circuit to obtain large amounts of simulation data. Secondly, when a large-scale circuit is subjected to simulation verification, the simulation result is influenced by the possible convergence problem of the LUT model. In addition, since there are no input parameters and different sizes require corresponding simulation data, each device needs to build a corresponding LUT model. These problems make the LUT method difficult to be practically applied.
Therefore, most of the existing transistor model building methods have many limitations, and the transistor model cannot be built quickly and efficiently.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a transistor model building method based on an artificial neural network, so as to solve the technical problems that most of the transistor model building methods in the prior art have many limitations and cannot build a transistor model quickly and efficiently.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention discloses a transistor model building method based on an artificial neural network, which comprises the following steps:
acquiring a transistor process type;
establishing a transistor initial model based on the transistor process type, wherein the transistor initial model comprises a plurality of ports;
applying a direct current voltage input signal to each port of the transistor initial model, and extracting a direct current output signal of each port of the transistor initial model;
and fitting the direct current voltage input signal and the direct current output signal through a preset artificial neural network to obtain a transistor direct current model.
Further, when the transistor model includes a gate terminal and a drain terminal, the method for establishing the transistor model further includes:
applying a direct-current voltage signal to each port of the transistor initial model, and applying an alternating-current voltage signal to a drain terminal of the transistor initial model;
applying a direct-current voltage signal to each port of the transistor initial model, and extracting a current signal from a gate end of the transistor initial model after applying an alternating-current voltage signal to a drain end of the transistor initial model;
drawing a current-frequency baud chart according to the direct-current voltage signal and the current signal, wherein the abscissa of the current-frequency baud chart is frequency, and the ordinate of the current-frequency baud chart is current;
extracting a target point from the current-frequency bode diagram, and according to the current of the target point and the targetCalculating the gate-drain capacitance C of the transistor by the frequency of the point gd The gate leakage capacitance value C of the transistor gd The calculation formula of (2) is as follows:
V ac ＝I ac ×1/(2×π×f×C gd )
in the formula, V ac Is an alternating voltage signal, iac is a current signal of the target point, and f is the frequency of the target point;
based on the gate-drain capacitance value C of the transistor gd Establishing a transistor gate-drain capacitance model, wherein an input signal of the transistor gate-drain capacitance model is a direct-current voltage signal, and an output signal of the transistor gate-drain capacitance model is a transistor gate-drain capacitance value C gd 。
Further, when the transistor model includes a gate terminal and a source terminal, the transistor model establishing method further includes:
applying a direct-current voltage signal to each port of the transistor initial model, and applying an alternating-current voltage signal to a source end of the transistor initial model;
applying a direct-current voltage signal to each port of the transistor initial model, and extracting a current signal from a gate terminal of the transistor initial model after applying an alternating-current voltage signal to a source terminal of the transistor initial model;
drawing a current-frequency baud chart according to the direct-current voltage signal and the current signal, wherein the abscissa of the current-frequency baud chart is frequency, and the ordinate of the current-frequency baud chart is current;
extracting a target point from the current-frequency baud chart, and calculating a transistor gate-source capacitance value C according to the current of the target point and the frequency of the target point gs Gate-source capacitance value C of said transistor gs The calculation formula of (2) is as follows:
V ac ＝I ac ×1/(2×π×f×C gs )
in the formula, V ac Is an alternating voltage signal, iac is a current signal of the target point, and f is the frequency of the target point;
based on the gate-source capacitance value C of the transistor gd Build up crystalsA transistor gate-source capacitance model, wherein an input signal of the transistor gate-source capacitance model is a direct current voltage signal, and an output signal of the transistor gate-source capacitance model is a transistor gate-source capacitance value C gd 。
Further, when the transistor model includes a gate terminal and a body terminal, the transistor model establishing method further includes:
applying direct-current voltage signals to all ports of the transistor initial model, and applying alternating-current voltage signals to the body end of the transistor initial model;
applying a direct current voltage signal to each port of the transistor initial model, and extracting a current signal from a gate terminal of the transistor initial model after applying an alternating current voltage signal to a body terminal of the transistor initial model;
drawing a current-frequency baud graph according to the direct-current voltage signal and the current signal, wherein the abscissa of the current-frequency baud graph is frequency, and the ordinate of the current-frequency baud graph is current;
extracting a target point from the current-frequency baud chart, and calculating a capacitance value C of a gate body of the transistor according to the current of the target point and the frequency of the target point gs The transistor gate capacitance value C gs The calculation formula of (2) is as follows:
V ac ＝I ac ×1/(2×π×f×C gs )
in the formula, V ac Is an alternating voltage signal, iac is a current signal of the target point, and f is the frequency of the target point;
based on the transistor gate capacitance value C gd Establishing a transistor gate capacitance model, wherein an input signal of the transistor gate capacitance model is a direct-current voltage signal, and an output signal of the transistor gate capacitance model is a transistor gate capacitance value C gd 。
The beneficial effects of the invention are: the invention relates to a transistor model building method based on an artificial neural network, which comprises the steps of obtaining a transistor process type; establishing a transistor initial model based on the transistor process type, wherein the transistor initial model comprises a plurality of ports; applying a direct current voltage input signal to each port of the transistor initial model, and extracting a direct current output signal of each port of the transistor initial model; and fitting the direct-current voltage input signal and the direct-current output signal through a preset artificial neural network to obtain a transistor direct-current model. The present invention uses an artificial neural network to capture the relationship between the inputs and outputs (current and voltage) of a transistor model. Both dc and ac signals are considered in the model. The transistor can be modeled with high precision, and the simulation precision of the transistor can be remarkably improved under the condition of keeping higher simulation speed.
Drawings
The invention is further described below with reference to the following figures and examples:
FIG. 1 is a schematic flow chart of a transistor model building method based on an artificial neural network;
fig. 2 is a schematic structural diagram of a transistor model in the present application;
fig. 3 is a current-frequency bode plot in an embodiment of the present application.
Detailed Description
The following embodiments of the present application are described by specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure of the present application. The present application is capable of other and different embodiments and its several details are capable of modifications and/or changes in various respects, all without departing from the spirit of the present application. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present application, and the drawings only show the components related to the present application and are not drawn according to the number, shape and size of the components in actual implementation, and the type, number and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
In the following description, numerous details are set forth to provide a more thorough explanation of embodiments of the present application, however, it will be apparent to one skilled in the art that embodiments of the present application may be practiced without these specific details.
As shown in fig. 1-2, a transistor model building method based on an artificial neural network in this embodiment includes the steps of:
s110, acquiring a transistor process type;
s120, establishing a transistor initial model based on the transistor process type, wherein the transistor initial model comprises a plurality of ports;
s130, applying a dc voltage input signal to each port of the transistor initial model, and extracting a dc current output signal of each port of the transistor initial model;
and S140, fitting the direct-current voltage input signal and the direct-current output signal through a preset artificial neural network to obtain a transistor direct-current model.
In an embodiment of the present invention, when the transistor model includes a gate terminal and a drain terminal, the method for establishing the transistor model further includes the steps of:
s210, applying a direct current voltage signal to each port of the transistor initial model, and applying an alternating current voltage signal to a drain terminal of the transistor initial model;
s220, applying a direct current voltage signal to each port of the transistor initial model, and extracting a current signal from a gate end of the transistor initial model after applying an alternating current voltage signal to a drain end of the transistor initial model;
s230, drawing a current-frequency baud graph according to the direct-current voltage signal and the current signal, wherein the abscissa of the current-frequency baud graph is frequency, and the ordinate of the current-frequency baud graph is current;
s240, extracting a target point from the current-frequency baud chart, and calculating the grid leakage of the transistor according to the current of the target point and the frequency of the target pointCapacity value C gd The gate leakage capacitance value C of the transistor gd The calculation formula of (c) is:
V ac ＝I ac ×1/(2×π×f×C gd )
in the formula, V ac Is an alternating voltage signal, iac is a current signal of the target point, and f is the frequency of the target point;
s250, based on the transistor grid leakage capacitance value C gd Establishing a transistor gate-drain capacitance model, wherein an input signal of the transistor gate-drain capacitance model is a direct-current voltage signal, and an output signal of the transistor gate-drain capacitance model is a transistor gate-drain capacitance value C gd 。
In an embodiment of the present invention, when the transistor model includes a gate terminal and a source terminal, the method for establishing the transistor model further includes:
s310, applying direct current voltage signals to each port of the transistor initial model, and applying alternating current voltage signals to a source end of the transistor initial model;
s320, applying direct current voltage signals to all ports of the transistor initial model, and extracting current signals from a grid end of the transistor initial model after applying alternating current voltage signals to a source end of the transistor initial model;
s330, drawing a current-frequency baud graph according to the direct-current voltage signal and the current signal, wherein the abscissa of the current-frequency baud graph is frequency, and the ordinate of the current-frequency baud graph is current;
s340, extracting a target point from the current-frequency baud chart, and calculating a transistor gate-source capacitance value C according to the current of the target point and the frequency of the target point gs Gate-source capacitance value C of said transistor gs The calculation formula of (2) is as follows:
V ac ＝I ac ×1/(2×π×f×C gs )
in the formula, V ac The signal is an alternating voltage signal, the Iac is a current signal of the target point, and the f is the frequency of the target point;
s350, based on the transistor gate-source capacitance value C gd Establishing a transistor gate-source capacitance model, wherein an input signal of the transistor gate-source capacitance model is a direct-current voltage signal, and an output signal of the transistor gate-source capacitance model is a transistor gate-source capacitance value C gd 。
In an embodiment of the present invention, when the transistor model includes a gate terminal and a body terminal, the method for establishing the transistor model further includes:
s410, applying direct current voltage signals to each port of the transistor initial model, and applying alternating current voltage signals to a body end of the transistor initial model;
s420, applying a direct current voltage signal to each port of the transistor initial model, and extracting a current signal from a gate terminal of the transistor initial model after applying an alternating current voltage signal to a body terminal of the transistor initial model;
s430, drawing a current-frequency baud graph according to the direct-current voltage signal and the current signal, wherein the abscissa of the current-frequency baud graph is frequency, and the ordinate of the current-frequency baud graph is current;
s440, extracting a target point from the current-frequency baud graph, and calculating a transistor gate capacitance value C according to the current of the target point and the frequency of the target point gs A gate capacitance C of the transistor gs The calculation formula of (2) is as follows:
V ac ＝I ac ×1/(2×π×f×C gs )
in the formula, V ac Is an alternating voltage signal, iac is a current signal of the target point, and f is the frequency of the target point;
s450, based on the transistor grid capacitance value C gd Establishing a transistor grid capacitance model, wherein an input signal of the transistor grid capacitance model is a direct-current voltage signal, and an output signal of the transistor grid capacitance model is a capacitance value C of the transistor grid gd 。
In another embodiment of the present application, a method for establishing a transistor model based on an artificial neural network may include the steps of:
a1, determining a process structure type of a transistor and a modeling port of the transistor;
a2, extracting input direct current voltage and output direct current data of each port of the transistor (the direct current voltage is used as model input of the ANN, and the direct current is used as model output of the ANN);
a3, performing curve fitting on the direct-current voltage and the direct-current of the transistor port by using an Artificial Neural Network (ANN) to obtain a direct-current DC-ANN model of the circuit;
a4, applying direct-current voltage to each port (D, G, S, B) of the transistor, adding AC small-signal voltage to a drain terminal (D) of the transistor, then extracting current of a gate terminal (G) of the transistor, drawing a current-frequency baud graph (shown in figure 3), and calculating a corresponding transistor gate-drain capacitance value Cgd from a slope line in the graph according to a formula Vac = Iac × 1/(2 × π × f × C);
a5, applying direct-current voltage to each port (D, G, S, B) of the transistor, adding AC small-signal voltage to a source end (S) of the transistor, then extracting current of a gate end (G) of the transistor, drawing a current-frequency baud graph (shown in figure 3), and calculating a corresponding gate-source capacitance Cgs of the transistor according to a formula Vac = Iac × 1/(2 × π × f × C) from an oblique line in the graph;
applying direct-current voltage to each port (D, G, S, B) of the transistor, adding AC small-signal voltage to a body terminal (B) of the transistor, extracting current of a gate terminal (G) of the transistor, drawing a current-frequency baud graph (shown in figure 3), and calculating a corresponding gate capacitance value Cgb of the transistor according to a formula Vac = Iac × 1/(2 × π × f × C) from an oblique line in the graph;
and A7, constructing a Cgd ANN model by using the transistor port direct-current voltage in A4 and the calculated transistor gate-drain capacitance value data. The input variable of the ANN model is the direct current port voltage of the transistor, and the output value is a gate-drain capacitance value Cgd corresponding to the direct current port voltage;
and A8, constructing an ANN model of Cgs by using the direct-current voltage of the transistor port in the A5 and the calculated gate-source capacitance value data of the transistor. The input variable of the ANN model is the direct current port voltage of the transistor, and the output value is a gate-source capacitance Cgs corresponding to the direct current port voltage;
and A9, constructing an ANN model of Cgb by using the direct-current voltage of the transistor port in A6 and the calculated capacitance value data of the transistor gate. The input variable of the ANN model is the direct current port voltage of the transistor, and the output value is the gate capacitance value Cgb corresponding to the direct current port voltage;
a10, the model of the artificial neural network transistor from which DC and AC were obtained above was expressed by Verilog-A.
The beneficial effect of this application includes:
the modeling can be carried out aiming at any type of transistor (different process and manufacturing procedures and different physical principles), and the number and the type of the transistor ports are not limited;
applying direct current voltage to each port of the transistor, wherein each port can generate direct current, and the transistor can be in a normal working state or an abnormal working state;
the artificial neural network can be various types of neural network structures, or non-neural network structures (such as polynomial functions and the like), model input voltage is fitted to obtain model output current, and data preprocessing can be performed on input and output data through various preprocessing functions so as to improve fitting accuracy;
due to the capacitance Cgd at the gate-drain terminal, the output port current will vary due to the ac small signal voltage applied at the port. Here, a small ac signal can be applied to the gate terminal to draw current from the drain terminal. An alternating small signal can also be applied to the drain terminal to draw current from the gate terminal. Here all dc bias voltage conditions need to be covered;
due to the presence of the capacitance Cgs at the gate-source terminal, the output port current will vary due to the ac small signal voltage applied at the port. Here, an ac small signal can be applied at the gate terminal to draw current from the source terminal. An alternating small signal can also be applied to the source terminal to extract current from the gate terminal. Here all dc bias voltage conditions need to be covered;
due to the capacitance Cgb at the gate terminal, the output port current will vary due to the ac small signal voltage applied at the port. Here a small ac signal can be applied at the gate terminal to draw current from the body terminal. An ac small signal can also be applied to the bulk terminal to draw current from the gate terminal. Here all dc bias voltage conditions need to be covered;
in an ANN model of a gate-drain capacitor of a transistor, different direct-current bias voltages of each port of the transistor are input, and gate-drain capacitance values under different direct-current bias voltages are output;
in an ANN model of a gate-source capacitor of a transistor, different direct-current bias voltages of each port of the transistor are input, and gate-source capacitance values under different direct-current bias voltages are output;
in an ANN model of a gate capacitor of a transistor, inputting different direct current bias voltages of each port of the transistor, and outputting gate capacitance values under different direct current bias voltages;
the obtained transistor model function expression can be expressed and circuit simulated in any form, such as a netlist, verilog-a and the like.
The difference between the application and the current mainstream modeling method is as follows:
compared with the mainstream BSIM modeling method, the transistor model modeling method can be used for modeling transistors with different process procedures or different physical principles, so that the universality of the method is realized;
by using an artificial neural network structure and an automatic artificial neural network model parameter optimization process, the time for modeling a module circuit can be greatly shortened, and the modeling efficiency is improved;
by using the Verilog-A behavior level description language, more function descriptions can be flexibly realized.
In summary, in the transistor model establishing method based on the artificial neural network, the transistor process type is obtained; establishing a transistor initial model based on the transistor process type, wherein the transistor initial model comprises a plurality of ports; applying a direct current voltage input signal to each port of the transistor initial model, and extracting a direct current output signal of each port of the transistor initial model; and fitting the direct current voltage input signal and the direct current output signal through a preset artificial neural network to obtain a transistor direct current model. The present invention uses an artificial neural network to capture the relationship between the inputs and outputs (current and voltage) of a transistor model. Both dc and ac signals are considered in the model. The transistor can be modeled with high precision, and the simulation precision of the transistor can be remarkably improved under the condition of keeping higher simulation speed.
In the foregoing embodiments, although the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description. The embodiments of the present application are intended to embrace all such alternatives, modifications and variances that fall within the broad scope of the appended claims.
The above embodiments are merely illustrative of the principles and utilities of the present application and are not intended to limit the application. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical concepts disclosed in the present application shall be covered by the claims of the present application.
Claims (4)
1. A transistor model building method based on an artificial neural network is characterized in that: the method comprises the following steps:
acquiring a transistor process type;
establishing a transistor initial model based on the transistor process type, wherein the transistor initial model comprises a plurality of ports;
applying a direct current voltage input signal to each port of the transistor initial model, and extracting a direct current output signal of each port of the transistor initial model;
and fitting the direct current voltage input signal and the direct current output signal through a preset artificial neural network to obtain a transistor direct current model.
2. The method for building the transistor model based on the artificial neural network according to claim 1, wherein: when the transistor model comprises a gate end and a drain end, the transistor model establishing method further comprises the following steps:
applying a direct-current voltage signal to each port of the transistor initial model, and applying an alternating-current voltage signal to a drain terminal of the transistor initial model;
applying a direct-current voltage signal to each port of the transistor initial model, and extracting a current signal from a gate end of the transistor initial model after applying an alternating-current voltage signal to a drain end of the transistor initial model;
drawing a current-frequency baud graph according to the direct-current voltage signal and the current signal, wherein the abscissa of the current-frequency baud graph is frequency, and the ordinate of the current-frequency baud graph is current;
extracting a target point from the current-frequency baud chart, and calculating a transistor gate-drain capacitance value C according to the current of the target point and the frequency of the target point gd The gate-drain capacitance value C of the transistor gd The calculation formula of (2) is as follows:
V ac ＝I ac ×1/(2×π×f×C gd )
in the formula, V ac The signal is an alternating voltage signal, the Iac is a current signal of the target point, and the f is the frequency of the target point;
based on the gate-drain capacitance value C of the transistor gd Establishing a transistor gate-drain capacitance model, wherein an input signal of the transistor gate-drain capacitance model is a direct-current voltage signal, and an output signal of the transistor gate-drain capacitance model is a transistor gate-drain capacitance value C gd 。
3. The method for building the transistor model based on the artificial neural network according to claim 1, wherein: when the transistor model comprises a grid end and a source end, the transistor model establishing method further comprises the following steps:
applying a direct-current voltage signal to each port of the transistor initial model, and applying an alternating-current voltage signal to a source end of the transistor initial model;
applying a direct-current voltage signal to each port of the transistor initial model, and extracting a current signal from a gate terminal of the transistor initial model after applying an alternating-current voltage signal to a source terminal of the transistor initial model;
drawing a current-frequency baud chart according to the direct-current voltage signal and the current signal, wherein the abscissa of the current-frequency baud chart is frequency, and the ordinate of the current-frequency baud chart is current;
extracting a target point from the current-frequency baud chart, and calculating a transistor gate-source capacitance value C according to the current of the target point and the frequency of the target point gs The gate-source capacitance value C of the transistor gs The calculation formula of (2) is as follows:
V ac ＝I ac ×1/(2×π×f×C gs )
in the formula, V ac Is an alternating voltage signal, iac is a current signal of the target point, and f is the frequency of the target point;
based on the gate-source capacitance value C of the transistor gd Establishing a transistor gate-source capacitance model, wherein an input signal of the transistor gate-source capacitance model is a direct-current voltage signal, and an output signal of the transistor gate-source capacitance model is a transistor gate-source capacitance value C gd 。
4. The method for building the transistor model based on the artificial neural network according to claim 1, wherein: when the transistor model comprises a grid end and a body end, the transistor model establishing method further comprises the following steps:
applying direct-current voltage signals to all ports of the transistor initial model, and applying alternating-current voltage signals to the body end of the transistor initial model;
applying a direct current voltage signal to each port of the transistor initial model, and extracting a current signal from a gate terminal of the transistor initial model after applying an alternating current voltage signal to a body terminal of the transistor initial model;
drawing a current-frequency baud chart according to the direct-current voltage signal and the current signal, wherein the abscissa of the current-frequency baud chart is frequency, and the ordinate of the current-frequency baud chart is current;
extracting a target point from the current-frequency baud chart, and calculating a capacitance value C of a gate body of the transistor according to the current of the target point and the frequency of the target point gs The transistor gate capacitance value C gs The calculation formula of (2) is as follows:
V ac ＝I ac ×1/(2×π×f×C gs )
in the formula, V ac Is an alternating voltage signal, iac is a current signal of the target point, and f is the frequency of the target point;
based on the transistor gate capacitance value C gd Establishing a transistor gate capacitance model, wherein an input signal of the transistor gate capacitance model is a direct-current voltage signal, and an output signal of the transistor gate capacitance model is a transistor gate capacitance value C gd 。
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