CN115982083A

CN115982083A - Method, device and system for transmitting data between FPGA chips and storage medium

Info

Publication number: CN115982083A
Application number: CN202211595838.0A
Authority: CN
Inventors: 岳青
Original assignee: Sichuan Hengwan Technology Co Ltd
Current assignee: Sichuan Hengwan Technology Co Ltd
Priority date: 2022-12-13
Filing date: 2022-12-13
Publication date: 2023-04-18

Abstract

The embodiment of the invention discloses a method, a device and a system for transmitting data between FPGA chips and a storage medium, wherein the technical scheme provided by the invention is that a data link is established between a master FPGA chip and a slave FPGA chip, then the master FPGA chip and the slave FPGA chip transmit data based on the data link, and the data link only transmits data information but not control information, so that the data transmission efficiency is improved; in addition, the user data is crossed from the user clock domain to the transmission clock domain when the data is sent, and the received data is crossed from the transmission clock domain to the user clock domain when the data is received, so that the continuous data transmission is realized, and the data transmission rate is further improved; when multiple data links are in use, the synchronous buffer is set at the sending end or the receiving end, so that the data of each data link are aligned, the reliability of the data is improved, and the problem that the data transmission at high speed is not suitable due to high data overhead in the prior art is solved.

Description

Method, device and system for transmitting data between FPGA chips and storage medium

Technical Field

The present invention relates to the field of FPGA and communication technologies, and in particular, to a method, an apparatus, a system, and a storage medium for data transmission between FPGA chips.

Background

Massive antenna technology (Massive MIMO) is one of the key technologies of 5G NR (New Radio). In Massive MIMO systems, the number of antennas can typically reach 64 or more, for example: 128 or 256. As the number of antennas increases, the system capacity also doubles, and the complexity of system implementation also increases, so the amount of data to be processed is very large, and the requirements on the speed and stability of data transmission are also high. In order to implement a Massive MIMO system, multiple FPGAs (Field Programmable Gate arrays) are usually required to work together, so it is very critical how data is stably transmitted between the FPGAs.

In a system with multiple FPGAs working together, PCIE, serial RapidIO (SRIO) and Aurora64B/66B are three protocols commonly used for data transmission. Wherein PCIE defines a physical layer, a data link layer, a transaction layer and a software layer; SRIO defines a physical layer, a transport layer, and a logical layer; the Aurora64B/66B only defines a link layer and a physical layer, compared with PCIE and SRIO, the Aurora64B/66B protocol is simpler, the cost is lower, and the link number and the link rate are more flexible, so that the Aurora64B/66B is one of the common protocols for interconnection among multiple FPGAs.

Taking a system with a hardware design architecture based on Xilinx FPGA as an example, suppose that the whole system has 5 pieces of FPGA, wherein 1 piece of FPGA is taken as a master piece and mainly realizes the functions of ETH MAC and ORAN interfaces, and the other 4 pieces of FPGA are taken as slave pieces and mainly realizes the sending of downlink data and the receiving of uplink data, thus, data received by the ORAN interface from an upper layer and data which needs to be uploaded to the upper layer by the ORAN interface need to be transmitted between one master piece and a plurality of slave pieces.

Because the Aurora64B/66B needs to periodically perform clock compensation, the data is discontinuously transmitted, which means that the receiving and transmitting clocks of the Aurora64B/66B are not matched with the parallel clock rate of actual data transmission, so that the data needs to be buffered, and when the data line rate is high and the data link is more, a large amount of BRAM (Block RAM) resources are consumed for data buffering. Therefore, the existing transmission scheme between the master slice and the slave slice has large data overhead and is not suitable for high-rate data transmission.

In order to balance data overhead, rate and link, a simple and lightweight method for transmitting data between FPGA chips is urgently needed to be provided at present, and when multiple FPGAs are interconnected for data transmission, continuous data transmission can be realized, and the data transmission efficiency and reliability are improved, so as to solve the problem that the data transmission is not suitable for high-rate data transmission due to high data overhead in the prior art.

Disclosure of Invention

In view of this, embodiments of the present invention provide a method, an apparatus, a system, and a storage medium for data transmission between FPGA chips, in which a data link is established between a master FPGA chip and a slave FPGA chip, and then the master FPGA chip and the slave FPGA chip transmit data based on the data link, and since the data link only transmits data information but not control information, the transmission efficiency of data is improved; in addition, the user data is crossed from the user clock domain to the transmission clock domain when the data is sent, and the received data is crossed from the transmission clock domain to the user clock domain when the data is received, so that the data can be kept in the user clock domain before and after transmission, additional processing is not needed, the data overhead is low, the continuous data transmission is realized, and the data transmission rate is further improved; when multiple data links are in use, the synchronous buffer is set at sending end or receiving end to align data of each data link so as to raise reliability of data. The test shows that no error code exists in long-distance running at normal temperature, and the error code rate in long-distance running at high and low temperatures is very low.

In a first aspect, an embodiment of the present invention provides a data transmission method, where the method includes:

initializing the master FPGA chip and the slave FPGA chip; the master FPGA chip and the slave FPGA chip are interconnected through a high-speed serial interface;

the master FPGA chip judges whether the initialization operation is finished with the slave FPGA chip;

after the master FPGA chip and the slave FPGA chip complete initialization operation, according to a preset handshake signal, the master FPGA chip and the slave FPGA chip establish a data link based on at least one pair of high-speed serial interfaces defined by the preset handshake signal;

and after the data link is successfully established, the master FPGA chip and the slave FPGA chip transmit data based on the data link.

Preferably, the master FPGA chip and the slave FPGA chip include a high-speed serial transceiver module, and the initializing operation specifically includes:

resetting a clock module in the high-speed serial transceiver module;

and judging whether the clock module is locked or not, and resetting a data sending module and/or a data receiving module in the high-speed serial transceiver module after the clock module is locked.

Preferably, whether the master FPGA chip and the slave FPGA chip both complete initialization operation is determined as follows:

when the master FPGA chip carries out initialization operation, sending a master chip initialization start indication signal to the slave FPGA chip;

after receiving the master chip initialization start indication signal, the slave FPGA chip judges whether the initialization operation is completed locally, and if the initialization operation is completed, the slave chip initialization completion indication signal is replied to the master FPGA chip;

after receiving the slave chip initialization completion indication signal, the master FPGA chip judges whether the initialization operation is completed locally, and if the initialization operation is completed, the master chip initialization completion indication signal is sent to the slave FPGA chip;

after receiving the master initialization completion indication signal, the slave FPGA chip replies a confirmation to the master FPGA chip that the master initialization completion indication signal is received;

and when the main FPGA chip receives the indication signal for confirming that the main chip initialization is completed, judging that the main FPGA chip and the slave FPGA chip complete initialization operation.

Preferably, according to a preset handshake signal, the master FPGA chip and the slave FPGA chip establish a data link based on at least one pair of high-speed serial interfaces defined by the preset handshake signal, and the method specifically includes:

the master FPGA chip and the slave FPGA chip perform handshake according to preset handshake steps, when continuous successful handshake reaches preset times, the master FPGA chip and the slave FPGA chip successfully establish a data link between high-speed serial interfaces of preset handshake signal transmission, and when the data link is successfully established, the master FPGA chip sends a data link establishment success indication signal to the slave FPGA chip;

the preset handshake signals comprise preset first handshake signals and preset second handshake signals, and the handshake steps are as follows:

the master FPGA chip sends the preset first handshake signal to the slave FPGA chip;

when the slave FPGA chip receives the preset first handshake signal, replying the preset second handshake signal to the master FPGA chip;

and after the main FPGA chip receives the preset second handshake signal sent by the slave FPGA chip, the handshake is successful once.

Preferably, when the master FPGA chip and the slave FPGA chip establish a plurality of data links based on a plurality of pairs of high-speed serial interfaces defined by the preset handshake signals, the method further includes:

when the master FPGA chip or the slave FPGA chip receives a preset handshake signal sent by the other party, recording the moment when the preset handshake signal is received in each data link;

determining the link delay of each data link according to the moment when the preset handshake signal is received in each data link;

and configuring a receiving end synchronous buffer of each data link by using the link delay of each data link, or transmitting the link delay of each data link to the opposite side to enable the opposite side to configure a transmitting end synchronous buffer of the corresponding data link.

Preferably, the master FPGA chip and the slave FPGA chip include a high-speed serial transceiver IP core, and the master FPGA chip and the slave FPGA chip transmit data based on the data link, specifically including:

when the master FPGA chip or the slave FPGA chip sends user data to the other side based on the data link, the following operations are executed:

performing clock-crossing processing on user data to obtain first processing data;

adding a data synchronization head to the first processed data to obtain second processed data;

scrambling the data except the data synchronization head in the second processed data to obtain third processed data; the third processing data comprises the data synchronization head and data subjected to scrambling operation;

sending the third processed data to the high-speed serial transceiver IP core, and sending the third processed data to the opposite side after being processed by the high-speed serial transceiver IP core;

when the master FPGA chip or the slave FPGA chip receives data sent from the other side based on the data link, the following operations are executed:

obtaining received data through the high-speed serial transceiver IP core;

performing descrambling operation on the received data;

judging whether multiple data links exist or not, if so, caching the descrambled received data in a receiving end synchronous buffer of the current data link, and reading the descrambled received data from the receiving end synchronous buffer of the current data link so as to synchronize the data of each data link;

and performing cross-clock processing on the descrambled received data.

judging whether multiple data links exist or not, if so, caching the first processing data to a sending end synchronous buffer of the current data link, and reading the first processing data from the sending end synchronous buffer of the current data link so as to synchronize the data of each data link;

obtaining received data through the high-speed serial transceiver IP core;

performing descrambling operation on the received data;

and performing cross-clock processing on the descrambled received data.

Preferably, the first and second substrates are, among others,

the performing clock-crossing processing on the user data specifically includes:

crossing the user data from a user clock to a transmit clock;

the performing clock-crossing processing on the descrambled received data specifically includes:

and crossing the descrambled received data from a transmission clock to a user clock.

In a second aspect, an embodiment of the present invention provides an apparatus for transmitting data between FPGA chips, where the apparatus includes:

the initialization module is set to perform initialization operation on the master FPGA chip and the slave FPGA chip; the master FPGA chip and the slave FPGA chip are interconnected through a high-speed serial interface;

the initialization completion judging module is set for judging whether the master FPGA chip and the slave FPGA chip complete initialization operation or not;

the link establishing module is used for establishing a data link between the master FPGA chip and the slave FPGA chip based on at least one pair of high-speed serial interfaces defined by the preset handshake signals according to the preset handshake signals after the master FPGA chip and the slave FPGA chip complete initialization operation;

and the data transmission module is used for transmitting data based on the data link between the master FPGA chip and the slave FPGA chip after the data link is successfully established.

In a third aspect, an embodiment of the present invention provides a data transmission system, including: the FPGA chip comprises a main FPGA chip and one or more slave FPGA chips, wherein the main FPGA chip and the slave FPGA chips are interconnected through a high-speed serial interface;

the master FPGA chip is set to perform initialization operation and judge whether the initialization operation is completed with the slave FPGA chip, after the initialization operation is completed with the slave FPGA chip, a data link is established with at least one pair of high-speed serial interfaces defined by the slave FPGA chip based on a preset handshake signal according to the preset handshake signal, and after the data link is successfully established, data is transmitted with the slave FPGA chip based on the data link;

the slave FPGA chip is set to perform initialization operation, establishes a data link with at least one pair of high-speed serial interfaces defined by the master FPGA chip based on preset handshake signals according to the preset handshake signals after finishing the initialization operation with the master FPGA chip, and transmits data with the master FPGA chip based on the data link after the data link is successfully established.

In a fourth aspect, an embodiment of the present invention provides a storage medium, where the storage medium is used to store a computer program, and the computer program is used to implement the method in the first aspect.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 is a flow chart of a method for transmitting data between FPGA chips according to an embodiment of the present invention;

fig. 2 is a flowchart of the main FPGA chip determining and the slave FPGA chip performing initialization operations according to the embodiment of the present invention;

fig. 3 is a handshake flowchart when the master FPGA chip and the slave FPGA chip establish a data link based on a high-speed serial interface according to an embodiment of the present invention;

fig. 4 is a flowchart of a data transmission process of a user data transmitting end when a multiple data link data synchronization process is performed at a data receiving end according to an embodiment of the present invention;

fig. 5 is a flowchart of a transmission process of received data by a data receiving end when a multiple data link data synchronization process is performed at a data receiving end according to an embodiment of the present invention;

fig. 6 is a flowchart of a data transmission process of a user data transmitting end when a multiple data link data synchronization process is performed at a data transmitting end according to an embodiment of the present invention;

fig. 7 is a flowchart of a transmission process of received data by a data receiving end when a multiple data link data synchronization process is performed at a data transmitting end according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a data transmission device according to an embodiment of the present invention;

FIG. 9 is a schematic structural diagram of a data transmission module when a single data link is provided between a master FPGA chip and a slave FPGA chip according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a data transmission module according to an embodiment of the present invention when multiple data links are provided between a master FPGA chip and a slave FPGA chip and when data synchronization processing is performed at a data sender;

FIG. 11 is a schematic structural diagram of a data transmission module when multiple data links are provided between a master FPGA chip and a slave FPGA chip and when data synchronization processing of the multiple data links is performed at a data receiver according to an embodiment of the present invention;

fig. 12 is a diagram illustrating an O-RU architecture of a data transmission system according to an exemplary embodiment of the present invention.

Detailed Description

The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.

Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

Meanwhile, it should be understood that, in the following description, a "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.

Unless the context clearly requires otherwise, throughout the description, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".

In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.

The hardware design architecture of the technical scheme of the invention is based on a Xilinx FPGA system, and the system comprises a plurality of FPGAs, wherein one FPGA is used as a master chip, and the other one or more FPGAs are used as slave chips. Taking the Xilinx FPGA system used for O-RU as an example, the master slice mainly realizes the functions of ETH MAC and ORAN interfaces, and is responsible for distributing downlink data to the slave slices and sending the downlink data out through the slave slices, and receiving uplink data from the slave slices, summarizing the uplink data and uploading the uplink data to an upper layer. Each FPGA employs a high-speed serial transceiver IP core to enable high-speed serial communication between the master and slave chips.

It should be noted that: the technical scheme of the invention is that the same program code runs no matter in the master slice or the slave slice, namely: one FPGA includes both the functions performed by the master and the slave. The master chip and the slave chip are only one functional mode for each FPGA, each FPGA can be configured into a master chip mode or a slave chip mode, and when the FPGA is configured into the master chip mode, the FPGA operates in the master chip mode to execute the functions of the master chip; when the FPGA is configured to the slave mode, the FPGA operates in the slave mode to perform the functions of the slave.

Fig. 1 is a flowchart of a method for transmitting data between FPGA chips according to an embodiment of the present invention. As shown in fig. 1 in detail, the method includes the following steps:

step S110: the master FPGA chip and the slave FPGA chip carry out initialization operation; the master FPGA chip and the slave FPGA chip are interconnected through a high-speed serial interface.

Xilinx corporation integrates one or more high-speed serial transceiver modules in many FPGAs, its artix7, kintex7, and virtex7, called: and the SERDES (Multi-Gigabit Serializer/Deserializer) is used for realizing high-speed serial communication between the FPGA and the outside. The initialization operation referred to in this step is mainly a reset operation performed for the high-speed serial transceiver module in the FPGA chip. The high-speed serial transceiver module comprises a clock module, a data transmitting module and a data receiving module. The initialization operation specifically includes: resetting a clock module in the high-speed serial transceiver module; and judging whether the clock module is locked or not, and resetting the data sending module and/or the data receiving module in the high-speed serial transceiver module after the clock module is locked.

In practical applications, the specific reset of which part of these modules depends on the system requirements. In a specific example, according to a reset requirement of the SERDES, first, a QPLL (Quadrature Phase Locked Loop) of the SERDES is reset, then, whether the QPLL is Locked is determined, and after the QPLL is Locked, a TX DATAPATH (transmit data link) in a data transmission module and/or an RX DATAPATH (receive data link) in a data reception module of the SERDES are reset.

In addition, by providing reset interactive data to a PS (Processing System) of the FPGA, the PS can reset the corresponding part of the high-speed serial interface in time when needed (such as when a data link is abnormal). The provided reset interaction data comprises the following four data:

1. a QPLL reset for resetting the QPLL of the SERDES;

2. GTRESET for resetting TX DATAPATH (transmit data link) and RX DATAPATH (receive data link) of the SERDES;

3. GTTXRESET for resetting TX DATAPATH (transmit data link) of SERDES;

4. GTRXREST to reset RX DATAPATH (receive data link) of SERDES.

In addition, the initialization may be performed during the power-on or reset process of the FPGA, or during the abnormal data link, or may be performed by instructing the FPGA to perform initialization by a user through an upper computer, or in other scenes requiring initialization.

It should be noted that: in addition to the initialization for SERDES described above, the initialization operations involved in this step also include other conventional initializations performed by the FPGA upon power-up.

Step S120: and the master FPGA chip judges whether the slave FPGA chip and the master FPGA chip complete initialization operation or not.

When the data link is established between the master FPGA chip and the slave FPGA chip, the master FPGA chip is used for leading the establishment. Both parties are required to complete initialization operations before establishing a data link. As shown in fig. 2, the master FPGA chip determines whether the slave FPGA chip and the master FPGA chip complete initialization operations by the following steps:

step S121: and when the master FPGA chip carries out initialization operation, sending a master chip initialization start indication signal to the slave FPGA chip.

Step S122: and after receiving the master chip initialization start indication signal, the slave FPGA chip judges whether the initialization operation is finished locally, and if the initialization operation is finished, the slave chip initialization completion indication signal is replied to the master FPGA chip.

Step S123: and after receiving the slave chip initialization completion indication signal, the master FPGA chip judges whether the initialization operation is completed locally, and if the initialization operation is completed, the master chip initialization completion indication signal is sent to the slave FPGA chip.

Step S124: and after receiving the master chip initialization completion indication signal, the slave FPGA chip replies a confirmation to the master FPGA chip to receive the master chip initialization completion indication signal.

Step S125: and when the main FPGA chip receives the indication signal for confirming that the main chip initialization is completed, judging that the main FPGA chip and the slave FPGA chip complete initialization operation.

The signals sent between the master FPGA chip and the slave FPGA chip involved in the steps S121 to S125 include two parts, namely a synchronization header and information content, where the information content is fixed to 8 bytes, and if less than 8 bytes need to be supplemented with 0, specific information content may be customized according to system requirements, and may be different from each other, and it may also be defined that the signals sent by the master FPGA are the same and/or the signals sent by the slave FPGA are the same; the sync header is fixed to "10" to identify the following information content as control information. The master FPGA chip and the slave FPGA chip can definitely know that the initialization of the master FPGA chip and the initialization of the slave FPGA chip are finished through the signals sent between the high-speed serial interfaces, so that the opportunity of building a link is determined.

In a specific example, the main slice initialization start indication signal and the main slice initialization completion indication signal respectively sent by the main FPGA chip in steps S121 and S123 are both "1000bcbc78", where the first two bits "10" are synchronization heads and "00bcbc78" are information contents; the slave chip initialization completion indication signal and the confirmation of receiving the master chip initialization completion indication signal respectively sent by the slave FPGA chip in steps S122 and S124 are both "1000000078", where the first two bits "10" are synchronization header and "00000078" is information content.

Through the step S120, if it is determined that the master FPGA chip and the slave FPGA chip both complete the initialization operation, the step S130 is executed, and if neither or one of the master FPGA chip and the slave FPGA chip does not complete, the step S110 is continuously executed.

Step S130: after the master FPGA chip and the slave FPGA chip complete initialization operation, according to a preset handshake signal, the master FPGA chip and the slave FPGA chip establish a data link based on at least one pair of high-speed serial interfaces defined by the preset handshake signal.

Xilinx's FPGA for Gigabit applications will basically integrate some high-speed serial interfaces, collectively known as Gigabit drivers (GTx), in the order of increasing transmission rates, including: GTP, GTR, GTX, GTH, GTZ, GTY and the like. The GTx integrated by different series of FPGAs is different. In a specific example, the invention selects an FPGA with a GTY or GTH integrated with a higher transmission rate, and the master FPGA chip and the slave FPGA chip are connected through the GTY or GTH to realize the higher transmission rate.

The step of establishing the data link refers to establishing a data link between each pair of receiving and sending interfaces in the master FPGA chip and the slave FPGA chip, and the data link is specially used for transmitting data information between the master FPGA chip and the slave FPGA chip. Taking Xilinx kintex7/virtex7 as an example, each GTX/GTH includes 1 clock module, 4 data sending modules and 4 data receiving modules, that is, includes 4 pairs of transceiving interfaces, and if the master FPGA chip and the slave FPGA chip all select Xilinx kintex7/virtex7, at most 4 data links can be established therebetween, that is: each data link corresponds to a high-speed transceiver GT.

Specifically, according to a preset handshake signal, the master FPGA chip and the slave FPGA chip establish a data link based on at least one pair of high-speed serial interfaces defined by the preset handshake signal, which specifically includes:

the master FPGA chip and the slave FPGA chip are used for handshaking according to preset handshaking steps, when the continuous handshaking reaches preset times, the master FPGA chip and the slave FPGA chip successfully establish a data link between the preset high-speed serial interfaces for handshaking signal transmission, and when the data link is successfully established, the master FPGA chip sends a data link establishment success indicating signal to the slave FPGA chip.

and after the master FPGA chip receives the preset second handshake signal sent by the slave FPGA chip, the handshake is successful once.

The preset times of continuous successful handshake and the preset handshake signals sent by each handshake can be set according to system requirements, and the preset first handshake signals can be the same as or different from the preset second handshake signals. The signals involved in the synchronization step S120 are similar, and the handshake signal in this step S130 also includes a synchronization header and information content, where the synchronization header is also "10", and the information content can also be customized. In a specific example, as shown in fig. 3, the step S130 is described in detail by taking as an example that consecutive successful handshakes reach three times, preset handshake signals sent by the main FPGA chip for each handshake are different from each other, and a preset first handshake signal is the same as a preset second handshake signal:

step S131: and the master FPGA chip sends a first handshake signal to the slave FPGA chip.

In a specific example, if the master FPGA chip and the slave FPGA chip employ Aurora64B/66B codec, the first handshake signal may be defined as "1000bcbc78", where the first two bits "10" are synchronization headers.

Step S132: and after the slave FPGA chip receives the first handshake signal, replying the first handshake signal to the master FPGA chip.

Step S133: and the master FPGA chip judges whether the first handshake signal sent by the slave FPGA chip is received, if so, the master FPGA chip successfully handshakes once and continues to execute the step S134.

In addition, when under predetermined conditions, such as: within a predetermined time, if the master FPGA chip does not receive the first handshake signal sent by the slave FPGA chip (the reason may be that the slave FPGA chip does not receive the first handshake signal sent by the master FPGA chip, or the slave FPGA chip replies the first handshake signal but the master FPGA chip does not receive the first handshake signal), step S131 is executed again.

Step S134: and the master FPGA chip sends a second handshake signal to the slave FPGA chip.

In a specific example, if the master FPGA chip and the slave FPGA chip employ Aurora64B/66B codec, the second handshake signal may be defined as "100055bc78", where the first two bits "10" are synchronization headers.

Step S135: and when the slave FPGA chip receives the second handshake signal, replying the second handshake signal to the master FPGA chip.

Step S136: and the master FPGA chip judges whether the second handshake signal sent by the slave FPGA chip is received, if so, the handshake is successful twice, and the step S137 is continuously executed.

And if the master FPGA chip does not receive the second handshake signal sent by the slave FPGA chip, re-executing the step S131.

Step S137: and the master FPGA chip sends a third handshake signal to the slave FPGA chip.

In a specific example, if the master FPGA chip and the slave FPGA chip employ Aurora64B/66B codec, the third handshake signal may be defined as "1000aabc78", where the first two bits "10" are synchronization headers.

Step S138: and when the slave FPGA chip receives the third handshake signal, replying the third handshake signal to the master FPGA chip.

Step S139: and the master FPGA chip judges whether the third handshake signal sent by the slave FPGA chip is received, if so, the master FPGA chip successfully handshakes for three times, and the data link is successfully established.

And if the master FPGA chip does not receive the third handshake signal sent by the slave FPGA chip, re-executing step S131.

Step S13A: and when the data link is successfully established, the master FPGA chip sends a data link establishment success indicating signal to the slave FPGA chip.

In addition, the inventors of the present invention found, at the time of actual project development: when the master FPGA chip and the slave FPGA chips transmit data between the multiple pairs of transceiving interfaces, the receiver does not receive the transmitted data at the same time when the sender (such as the master FPGA chip) transmits the data to the receiver (such as the slave FPGA chips) through different transceiving interface pairs at the same time. In order to solve the problem, the invention provides a data synchronization scheme of multiple data links, and particularly, when data links are established between multiple pairs of transceiving interfaces, the time delay of each data link at a receiving end is calculated by using the time delay of the receiving end for receiving the handshake signals while sending the handshake signals, and the time delay is configured to a synchronous buffer reading data end of the data link, namely, the configured time reading data is delayed, so that the data of the multiple data links are synchronized. Specifically, when the master FPGA chip or the slave FPGA chip receives a preset handshake signal sent by the other party, the time when the preset handshake signal is received in each data link is recorded; determining the link delay of each data link according to the moment when the preset handshake signal is received in each data link; and configuring the receiving end synchronous buffer of each data link by using the link delay of each data link, or transmitting the link delay of each data link to the opposite side so that the opposite side configures the transmitting end synchronous buffer of the corresponding data link.

In a specific example, the receiver-side synchronization buffer or the sender-side synchronization buffer may be implemented using a RAM that occupies few resources.

It should be noted that: different from the prior art that both data information and control information and mixed information of the data information and the control information are transmitted between each pair of transceivers, the data link established between the master FPGA chip and the slave FPGA chip is a link specially used for data information transmission, so that on one hand, the link is established in advance before data transmission, and is not easy to disconnect, thereby improving the stability of data transmission; on the other hand, only data information is transmitted, so that the data transmission efficiency is improved.

Step S140: and after the data link is successfully established, the master FPGA chip and the slave FPGA chip transmit data based on the data link.

Xilinx provides two Aurora IP cores, respectively: aurora 8B/10B and Aurora64B/66B. Wherein, aurora 8B/10B coding can balance DC, has enough jump to recover clock, but has 20% bandwidth overhead; the first two bits of the Aurora64B/66B code represent a synchronous head, the overhead is about 3%, and compared with the Aurora 8B/10B code, the Aurora64B/66B code data has smaller overhead, and the data transmission efficiency is higher.

In a specific example, the high-speed serial transceiver IP core is used in the "FPGA chip" (including the master FPGA chip and the slave FPGA chip), and specifically, aurora64B/66B coding and decoding are adopted, so that in combination with a high-speed serial interface GTY or GTH, the data line rate can reach more than 16Gbps, thereby realizing a higher transmission rate. One or more high-speed serial transceiver IP cores may be included in the FPGA chip. The high-speed serial transceiver module is contained in the high-speed serial transceiver IP core.

In the invention, when multiple data links exist, the data synchronization processing of the multiple data links can be executed at a data sending party or a data receiving party, and in the concrete implementation, one of the data synchronization processing can be selected.

Specifically, when the data synchronization processing of multiple data links is executed at the data receiving side, the master FPGA chip and the slave FPGA chip transmit data based on the data links, which is specifically described as follows:

before transmitting the received user data to the high-speed serial transceiver IP core at the other end through the high-speed serial transceiver IP core, the master FPGA chip or the slave FPGA chip needs to process the user data, which is specifically shown in fig. 4 and includes the following steps:

step S1410: and performing clock crossing processing on the user data to obtain first processing data.

Step S1411: and adding a data synchronization head to the first processed data to obtain second processed data.

Specifically, the "data sync header" is fixed to "01" here, which indicates that the subsequent information content is data information.

Step S1412: scrambling the data except the data synchronization head in the second processed data to obtain third processed data; wherein the third processed data comprises the data synchronization header and the data after scrambling operation.

In a specific example, the polynomial used when scrambling is G (x) =1+ x39+ x58.

When the step is realized, the following steps can be realized:

and judging whether scrambling is needed according to a preset scrambling and descrambling configuration value. The 'scrambling/descrambling configuration value' is a configuration item which is set by a user according to system requirements and determines whether scrambling operation is completed before entering the high-speed serial transceiver IP core or inside the high-speed serial transceiver IP core, and whether descrambling is completed after passing through the high-speed serial transceiver IP core or inside the high-speed serial transceiver IP core. If the scrambling operation is completed before entering the high speed serial transceiver IP core and the descrambling operation is completed after passing through the high speed serial transceiver IP core, the scrambling operation and the descrambling operation within the high speed serial transceiver IP core need to be masked out.

It should be noted that: the data synchronization head does not need to carry out scrambling operation, only scrambles the data part behind the data synchronization head, and adds the data synchronization head to the scrambled data after the scrambling is finished to form third processed data.

Step S1413: and sending the third processed data to the high-speed serial transceiver IP core, and sending the processed third processed data to the opposite side.

Specifically, in the high-speed serial transceiver IP core, received data is subjected to encoding, parallel-to-serial conversion, equalization, and other processing, and is transmitted to the other party through the high-speed serial interface.

It should be noted that: here, "user data" is processed in steps S141 to S144 in units of 64 bits.

Similarly, when the master FPGA chip or the slave FPGA chip receives data sent from the other, after receiving the data through the IP core of the high-speed serial transceiver, the master FPGA chip or the slave FPGA chip also needs to process the received data, specifically as shown in fig. 5, the method includes the following steps:

step S1420: and obtaining received data through the high-speed serial transceiver IP core.

Specifically, in the high-speed serial transceiver IP core, received data is received through the high-speed serial interface and is subjected to equalization, serial-to-parallel conversion, decoding, and the like.

Step S1421: and performing descrambling operation on the received data.

Similarly, in step S1420, it may be determined whether descrambling is necessary according to a preset descrambling configuration value, as in step S1412. This step S1420 is executed if descrambling is required, otherwise step S1421 is executed directly.

Step S1422: and judging whether a plurality of data links exist, if so, executing a step S1423, and otherwise, executing a step S1424.

Step S1423: and caching the descrambled received data in a receiving end synchronous buffer of the current data link, and reading the descrambled received data from the receiving end synchronous buffer of the current data link so as to synchronize the data of each data link.

Step S1424: and performing cross-clock processing on the descrambled received data.

For the "cross-clock processing" in step S1424 and step S1410, in a specific example, it is assumed that the master FPGA chip sends data to and receives data from the slave FPGA chip, and because clock sources used by the sender and the receiver are different, there is a clock difference that causes clock mismatch, so there may be a data packet loss phenomenon, and for stable reliability of data, the master FPGA chip or the slave FPGA chip in the present invention needs to send data to the other party after performing cross-clock processing on the data to the other party before sending the data to the other party, and then sends the data to the other party; correspondingly, after the slave FPGA chip or the master FPGA chip receives the data sent by the other side, the data received from the other side also needs to be processed in a clock crossing manner.

In step S1410, performing clock crossing processing on the user data specifically includes: crossing the user data from a user clock to a transmit clock;

for the step S1424, performing clock crossing processing on the received data or the descrambled received data, specifically including: and crossing the receiving data or the descrambled receiving data from a transmission clock to a user clock.

In a specific example, a RAM that occupies few resources is used to span data from the user clock domain to the transmit clock domain, or vice versa. When the user data is crossed from the user clock domain to the transmission clock domain, the specific operation is as follows: one end uses the user clock to store the user data, and the other end uses the transmission clock to read the user data; when the received data or the descrambled received data is crossed from a transmission clock domain to a user clock domain, the specific operation is as follows: one end uses the transmission clock to store the received data or the descrambled received data, and the other end uses the user clock to read the received data or the descrambled received data. The transmission clock refers to a clock used when the high-speed serial interface sends or receives data, and if the high-speed serial interface is a GTY, the transmission clock is a GTY transmission clock.

For the synchronization operation involved in step S1423, in a specific example, it is assumed that three data links need to be established between the master FPGA chip and the slave FPGA chip (i.e., each of the two sides has three pairs of transceiving interfaces), the master FPGA chip sends a handshake signal to the slave FPGA chip through three sending interfaces at the same time, the slave FPGA chip records the receiving time after receiving the handshake signal at the corresponding receiving interface, and it is assumed that the first data link is received at 2 hours, 2 minutes, 2 seconds, the second data link is received at 2 hours, 2 minutes, 4 seconds, and the third data link is received at 2 hours, 2 minutes, 1 second, the delay determined according to the recorded receiving time is finally: the first data link is delayed for 2 seconds, the second data link is delayed for 0 second (no delay is needed), the third data link is delayed for 3 seconds, and the calculated delay is configured to the receiving end synchronous buffer of the corresponding data link. When receiving data from the main FPGA chip on the first data link from the FPGA chip, the data needs to be buffered in a receiving end synchronous buffer of the first data link for 2 seconds, and then the data is read from the receiving end synchronous buffer of the first data link, and the same is true for the third data link, so that the data of each data link is read at the same time, and the technical purpose of synchronous receiving of the data of multiple data links is achieved.

Similarly, the main FPGA chip calculates the time delay on each data link by receiving handshake signals sent by the slave FPGA chip, and configures a receiving end synchronous buffer of each data link at the side of the main FPGA chip by using the time delay of each data link, so that when receiving data sent by the slave FPGA chip, the data is buffered and then read, and the data of multiple data links is synchronously received.

When the synchronous processing of the data of multiple data links is executed at the data sending party, the master FPGA chip and the slave FPGA chip transmit data based on the data links, which is specifically described as follows:

before the master FPGA chip or the slave FPGA chip sends the received user data to the high-speed serial transceiver IP core at the other end through the high-speed serial transceiver IP core, the user data needs to be processed, specifically as shown in fig. 6, the method includes the following steps:

step S1430: and performing clock crossing processing on the user data to obtain first processing data.

Step S1431: and judging whether a plurality of data links exist, if so, executing the step S1432, and otherwise, executing the step S1433.

Step S1432: and caching the first processing data to a sending end synchronous buffer of the current data link, and reading the first processing data from the sending end synchronous buffer of the current data link so as to synchronize the data of each data link.

Step S1433: and adding a data synchronization head to the first processed data to obtain second processed data.

Step S1434: scrambling the data except the data synchronization head in the second processed data to obtain third processed data; the third processing data comprises the data synchronization head and data subjected to scrambling operation; .

Step S1435: and sending the third processed data to the high-speed serial transceiver IP core, and sending the processed third processed data to the opposite side.

Similarly, when the master FPGA chip or the slave FPGA chip receives data sent from the other side, after the data is received by the high-speed serial transceiver IP core, the received data also needs to be processed, which is specifically shown in fig. 7, and includes the following steps:

step S1440: and obtaining received data through the high-speed serial transceiver IP core.

Step S1441: and performing descrambling operation on the received data.

Step S1442: and performing cross-clock processing on the descrambled received data.

As can be seen from the above steps, in the embodiment of the present invention, the data link is established between the master FPGA chip and the slave FPGA chip, and then the master FPGA chip and the slave FPGA chip transmit data based on the data link, and since the data link only transmits data information but not control information, the data transmission efficiency is improved; in addition, the user data is crossed from the user clock domain to the transmission clock domain when the data is sent, and the received data is crossed from the transmission clock domain to the user clock domain when the data is received, so that the data can be kept in the user clock domain before and after transmission without additional processing, the continuous transmission of the data is realized, and the data transmission rate is further improved; when multiple data links are in use, the synchronous buffer is set at sending end or receiving end to align data of each data link so as to raise reliability of data.

Fig. 8 is a schematic structural diagram of an inter-FPGA-chip data transmission device according to an embodiment of the present invention, which is disposed on an FPGA chip, and as shown in fig. 8, the inter-FPGA-chip data transmission device 8 according to the embodiment of the present invention includes: an initialization module 810 configured to perform initialization operations on the master FPGA chip and the slave FPGA chip; the master FPGA chip and the slave FPGA chip are interconnected through a high-speed serial interface; an initialization completion judging module 820 configured to judge whether the master FPGA chip and the slave FPGA chip have completed initialization operations; the link establishing module 830 is configured to establish a data link between the master FPGA chip and the slave FPGA chip based on at least one pair of high-speed serial interfaces defined by the preset handshake signals according to the preset handshake signals after the master FPGA chip and the slave FPGA chip both complete initialization operations; the master FPGA chip and the slave FPGA chip are interconnected through a high-speed serial interface; and the data transmission module 840 is configured to transmit data based on the data link between the master FPGA chip and the slave FPGA chip after the data link is successfully established.

When a single data link is formed between the master FPGA chip and the slave FPGA chip, the data transmission module 840 specifically includes the following modules as shown in fig. 9:

the transmitting end clock crossing processing module 8410 is configured to perform clock crossing processing on the user data to obtain first processed data, and send the first processed data to the data synchronization header adding module 911.

A data synchronization header adding module 8411, configured to add a data synchronization header to the first processed data to obtain second processed data, and send the second processed data to the scrambling module 912.

The scrambling module 8412 is configured to perform scrambling operation on data in the second processed data except for the data synchronization header to obtain third processed data, and send the third processed data to the high-speed serial transceiver IP core 913, where the third processed data includes the data synchronization header and the data subjected to scrambling operation.

And a high-speed serial transceiver IP core 8413 configured to transmit the third processed data to the other side after processing thereof and obtain received data from the other side.

The descrambling module 8414 is configured to perform descrambling operation on the received data, and send the descrambled received data to the receiving end cross-clock processing module 915.

And the receiving end cross-clock processing module 8415 is configured to perform cross-clock processing on the descrambled received data.

When multiple data links are formed between the master FPGA chip and the slave FPGA chip, and when data synchronization processing of the multiple data links is performed at a data transmitting side, as for the data transmission module 840, as shown in fig. 10 specifically, compared with that shown in fig. 9, one more transmitting synchronization processing module 8420 is added between the transmitting-side cross-clock processing module 8410 and the data synchronization header adding module 8411, and is configured to cache the first processing data transmitted to the transmitting-side cross-clock processing module 8410 to a transmitting-side synchronization buffer of the current data link, and read the first processing data from the transmitting-side synchronization buffer of the current data link, so as to synchronize data of each data link.

When the data synchronization processing of multiple data links is performed at the data receiving side, as shown in fig. 11, in particular, for the data transmission module 840, as compared with that shown in fig. 9, one more receiving synchronization processing module 8430 is added between the descrambling module 8414 and the receiving-end clock-crossing processing module 8415, and is configured to cache the descrambled received data sent to the receiving-end synchronization processing module 8414 by the descrambling module 8414 in the receiving-end synchronization buffer of the current data link, and then read the descrambled received data from the receiving-end synchronization buffer of the current data link, so as to synchronize the data of each data link.

The embodiment of the invention also provides a data transmission system between the FPGA chips, which at least comprises: the FPGA chip comprises a main FPGA chip and one or more slave FPGA chips, wherein the main FPGA chip and the slave FPGA chips are interconnected through a high-speed serial interface;

In a specific embodiment, the data transmission system is an ORAN network radio frequency unit O-RU, taking the example that the base station radio frequency unit O-RU12 includes a master FPGA chip 1210, a slave FPGA chip 1220, and a slave FPGA chip 1230, and a specific structural schematic diagram is shown in fig. 12, where the master FPGA chip 1210 is connected to an O-DU (ORAN network distributed unit), mainly implementing functions of ETH MAC and ORAN interfaces, and is responsible for uploading uplink data received from an antenna by the slave FPGA chip 1220 and the slave FPGA chip 1230 to the O-DU, and distributing downlink data downloaded by the O-DU to the slave FPGA chip 1220 and the slave FPGA chip 1230; the slave FPGA chip 1220 and the slave FPGA chip 1230 are connected to an antenna, and mainly transmit downlink data distributed from the master FPGA chip 1210 through the antenna, and receive uplink data and upload the uplink data to the master FPGA chip 1210.

An embodiment of the present invention provides a storage medium, where the storage medium is configured to store a computer program, and the computer program is configured to implement the method for transmitting data between FPGA chips according to any of the above method embodiments.

The embodiment of the present invention provides a chip, where the chip is used to support a receiving device (e.g., a terminal device, a network device, etc.) to implement the functions shown in the embodiment of the present invention, and the chip is specifically used in a chip system, where the chip system may be formed by a chip, and may also include a chip and other discrete devices. When the chip in the receiving device implementing the method includes a processing unit, the chip may further include a communication unit, and the processing unit may be, for example, a processor, and when the chip includes the communication unit, the communication unit may be, for example, an input/output interface, a pin, a circuit, or the like. The processing unit executes all or part of the actions executed by the processing modules in the embodiment of the invention, and the communication unit executes corresponding receiving or sending actions. In another specific embodiment, the processing module of the receiving device in the embodiment of the present invention may be a processing unit of a chip, and the receiving module or the transmitting module of the control device is a communication unit of the chip.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, apparatus (device) or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may employ a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations of methods, apparatus (devices) and computer program products according to embodiments of the application. It will be understood that each flow in the flow diagrams can be implemented by computer program instructions.

These computer program instructions may be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows.

These computer program instructions may also be provided to a processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows.

Another embodiment of the invention is directed to a non-volatile storage medium storing a computer-readable program for causing a computer to perform some or all of the above-described method embodiments.

That is, as can be understood by those skilled in the art, all or part of the steps in the method for implementing the embodiments described above may be accomplished by specifying, by a program, relevant hardware, where the program is stored in a storage medium and includes several instructions to enable a device (which may be a single chip, a chip, or the like) or a processor (processor) to execute all or part of the steps of the method described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for transmitting data between FPGA chips is characterized by comprising the following steps:

the master FPGA chip judges whether the slave FPGA chip and the master FPGA chip complete initialization operation or not;

2. The method according to claim 1, wherein the master FPGA chip and the slave FPGA chip comprise high-speed serial transceiver modules, and the performing initialization operation specifically comprises:

resetting a clock module in the high-speed serial transceiver module;

3. The method of claim 1, wherein determining whether the master FPGA chip and the slave FPGA chip both complete initialization operations is performed by:

after receiving the master chip initialization start indication signal, the slave FPGA chip judges whether the initialization operation is finished locally, and if the initialization operation is finished, the slave chip initialization completion indication signal is replied to the master FPGA chip;

4. The method according to claim 1, wherein the establishing of the data link between the master FPGA chip and the slave FPGA chip based on at least one pair of high-speed serial interfaces defined by the preset handshake signals according to the preset handshake signals specifically includes:

5. The method according to claim 4, wherein when the master FPGA chip and the slave FPGA chip establish a plurality of data links based on a plurality of pairs of high-speed serial interfaces defined by the preset handshake signals, the method further comprises:

and configuring the receiving end synchronous buffer of each data link by using the link delay of each data link, or transmitting the link delay of each data link to the opposite side so that the opposite side configures the transmitting end synchronous buffer of the corresponding data link.

6. The method according to claim 5, wherein the master FPGA chip and the slave FPGA chip comprise high-speed serial transceiver IP cores, and the master FPGA chip and the slave FPGA chip transmit data based on the data link, specifically comprising:

obtaining received data through the high-speed serial transceiver IP core;

performing descrambling operation on the received data;

judging whether a plurality of data links exist, if so, caching the descrambled received data into a receiving end synchronization buffer of the current data link, and reading the descrambled received data from the receiving end synchronization buffer of the current data link so as to synchronize the data of each data link;

and performing cross-clock processing on the descrambled received data.

7. The method according to claim 5, wherein the master FPGA chip and the slave FPGA chip comprise high-speed serial transceiver IP cores, and the master FPGA chip and the slave FPGA chip transmit data based on the data link, specifically comprising:

judging whether multiple data links exist or not, if so, caching the first processing data to a sending end synchronous cache of the current data link, and reading the first processing data from the sending end synchronous cache of the current data link so as to synchronize the data of each data link;

obtaining received data through the high-speed serial transceiver IP core;

performing descrambling operation on the received data;

and performing cross-clock processing on the descrambled received data.

8. The method of claim 6 or 7, wherein,

crossing the user data from a user clock to a transmit clock;

9. The utility model provides a data transmission device between FPGA chip which characterized in that, the device includes:

the initialization completion judging module is used for setting the master FPGA chip to judge whether the initialization operation is completed with the slave FPGA chip;

10. A data transmission system, comprising: the FPGA chip comprises a main FPGA chip and one or more slave FPGA chips, wherein the main FPGA chip and the slave FPGA chips are interconnected through a high-speed serial interface;

the master FPGA chip is set to perform initialization operation and judge whether the initialization operation is completed with the slave FPGA chip or not, after the initialization operation is completed with the slave FPGA chip, a data link is established with at least one pair of high-speed serial interfaces defined by the slave FPGA chip based on a preset handshake signal according to a preset handshake signal, and after the data link is successfully established, data are transmitted with the slave FPGA chip based on the data link;

11. A storage medium for storing a computer program for implementing the method of any one of claims 1 to 8.