CN115981880A - Method, device, system and chip for avoiding deadlock of host access slave - Google Patents
Method, device, system and chip for avoiding deadlock of host access slave Download PDFInfo
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Abstract
The invention discloses a method, a device, a system and a chip for avoiding deadlock of a host access slave, wherein the method comprises the following steps: in the communication process of the host module and the slave module, the connecting pipe module arranged between the host module and the slave module is in a monitoring transparent transmission mode, and monitors command/response information between the host module and the slave module in real time and carries out transparent transmission processing; after receiving the takeover command, the takeover module is switched to enter a takeover mode, and takes over the operation of the slave module connected with the takeover module, and then carries out subsequent communication with the host module; after receiving the command of quitting takeover, the takeover module completes the current command operation with the host module, quits the current takeover mode and enters the monitoring transparent transmission mode. The invention can improve the stability, robustness and software friendliness of the system.
Description
Technical Field
The invention relates to the technical field of data communication in a chip, in particular to a method, a device, a system and a chip for avoiding deadlock of a host access slave.
Background
In large-scale digital chip designs, a host module (Master) for access is typically provided, which may be implemented, for example, using a CPU; meanwhile, various storage space types such as a system configuration space, an on-chip cache space, an off-chip cache space and the like exist, and the storage spaces are used as Slave modules (Slave) for access and managed by corresponding storage logic circuits. There may be situations where one master module accesses multiple slave modules, typically via a standard bus protocol (e.g., AMBA AXI bus) and a bus interconnect module (interconnect) that is responsible for command arbitration and access routing for the different functional modules.
Fig. 1 is a schematic diagram illustrating an application architecture having a master module and a slave module in the prior art; in this bus structure, the master module is connected to at least one slave module via a bus interconnect module. Generally, after a host module sends an access command, a bus interconnection module routes access to a corresponding slave module according to address mapping; the slave modules execute the commands and return responses (such as write execution results, read data and the like) after receiving the commands, and the bus interconnection module is responsible for arbitrating the responses of the plurality of slave modules and selecting one slave module to send to the host module according to the arbitration results. In addition, a Clock and Reset Generator (CRG) is usually responsible for generating clocks and Reset signals of all modules, and for low power consumption and exception management, the clocks and Reset signals of different modules can be independently controlled by the CPU through issuing software commands.
However, after the master module sends a command to a slave module, the command is executed only after the master module receives a corresponding response; if the slave module fails to return a response, the master module will remain in a wait state and cause a deadlock. Commonly, such a deadlock situation may occur under the following scenario:
scene 1: under the low power consumption scene, the clock of the slave module is closed and reset effectively through the CRG module, and then the slave is in a shutdown mode and cannot execute the command.
Scene 2: an exception occurs inside the slave module, so that the command cannot be correctly executed and a response is returned.
In the prior art, the above mentioned deadlock problem is generally solved by the following methods:
for scenario 1, in a low power consumption scenario, the master module is restricted from accessing the slave module that is turned off.
For scenario 2, resetting all the master module, the bus interconnect module and the slave module is equivalent to restarting the whole system.
However, the existing solutions have some disadvantages when used in practical projects:
when the solution of scenario 1 is applied to a platform debugging stage, if software testing is not complete, or in a normal system operation stage, because software execution is abnormal, the slave module that is shut down may be accessed by mistake, thereby causing a deadlock, and in this case, it usually takes a lot of time to debug and solve such a deadlock problem.
For the solution of scenario 2, if an abnormality occurs in a single slave module, all the host module, the bus interconnect module and the slave module are reset, which affects other functions still in normal operation, resulting in a large cost and poor system robustness.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a method, an apparatus, a system and a chip for avoiding deadlock of a host accessing a slave, which can avoid deadlock of a host module without affecting normal operation of other modules, and improve stability of the system.
To solve the above technical problem, an aspect of the present invention provides a method for avoiding deadlock of a master accessing a slave, which at least includes the following steps:
in the communication process of the host module and the slave module, a connecting pipe module arranged between the host module and the slave module is in a monitoring transparent transmission mode, and command/response information between the host module and the slave module is monitored in real time and is subjected to transparent transmission processing;
after receiving the takeover command, the takeover module is switched to enter a takeover mode, and takes over the operation of the slave module connected with the takeover module, and then carries out subsequent communication with the host module;
after receiving the command of quitting takeover, the takeover module completes the current command operation with the host module, quits the current takeover mode and enters the monitoring transparent transmission mode.
Wherein, the step of monitoring the information between the host module and the slave module in real time and carrying out transparent transmission processing further comprises:
the taking-over module transmits the command message from the host module forwarded by the bus interconnection module to the slave module; transmitting a response message from the slave module to the host module through the bus interconnection module;
the takeover module monitors and counts the command and the response message, and records the command type and the access data length when receiving a read command of the host module; when a write command of the host module is received, recording the sending number of write data; and when the received read data is the read command returned by the slave module, recording the number of the received read data.
Wherein, after receiving the takeover command from the clock reset module, the takeover module switches to enter a takeover mode, and the step of taking over the operation of the slave module connected to the takeover mode further includes:
and shielding all operations of the host module on the slave module, replacing the slave module and the host module by a take-over module to finish all command messages which are sent but not finished, and responding to new command messages sent by the host module subsequently.
Correspondingly, the present invention also provides a device for avoiding deadlock of a host accessing a slave, which is arranged between a host module and a slave module, and at least comprises:
the monitoring and transparent transmission processing unit is used for monitoring command/response information between the host module and the slave module in real time and performing transparent transmission processing in a monitoring and transparent transmission mode in the communication process of the host module and the slave module;
the takeover processing unit is used for switching to enter a takeover mode after receiving the takeover command, carrying out takeover processing on the operation of the slave module connected with the takeover mode and carrying out subsequent communication with the host module;
and the takeover exit unit is used for completing the current command operation between the takeover exit unit and the host module after receiving the takeover exit command, exiting the current takeover mode and entering the monitoring transparent transmission mode.
Wherein, the monitoring transparent transmission processing unit further comprises:
the transparent transmission processing unit is used for transmitting the command message from the host module forwarded by the bus interconnection module to the slave module; transmitting a response message from the slave module to the host module through the bus interconnection module;
the monitoring processing unit is used for monitoring and counting the command and the response message, and recording the command type and the access data length when the received command is a read command of the host module; when a write command of the host module is received, recording the sending number of write data; and when the received read data is the read command returned by the slave module, recording the number of the received read data.
Wherein the takeover processing unit further comprises:
and the shielding processing unit is used for shielding all operations of the host module on the slave module, replacing the slave module and the host module by the take-over module to finish all command messages which are sent but not finished, and responding to new command messages sent by the host module subsequently.
Correspondingly, the invention also provides a method for avoiding deadlock of a host access slave, which at least comprises the following steps:
in the communication process of the host module and the slave module, a connecting pipe module arranged between the host module and the slave module is in a monitoring transparent transmission mode, and command/response information between the host module and the slave module is monitored in real time and is subjected to transparent transmission processing;
when a slave module is detected to need to enter a low-power-consumption working mode or abnormal working occurs, controlling to send a command for turning off the slave module to a clock reset module, and sending a take-over command to a take-over module connected with the slave module by the clock reset module;
after receiving the takeover command, the takeover module switches to enter a takeover mode, takes over the operation of the slave module connected with the takeover mode, performs subsequent communication with the host module, and returns a takeover response to the clock reset module;
and after receiving the take-over response, the clock reset module controls to turn off the slave module.
Wherein, the step of monitoring the information between the host module and the slave module in real time and carrying out transparent transmission processing further comprises:
the taking-over module transmits the command message from the host module forwarded by the bus interconnection module to the slave module; transmitting a response message from the slave module to the host module through the bus interconnection module;
the takeover module monitors and counts the command and the response message, and records the command type and the access data length when receiving a read command of the host module; when a write command of the host module is received, recording the sending number of write data; and when the received read data is the read command returned by the slave module, recording the number of the received read data.
Wherein, after receiving the takeover command from the clock reset module, the takeover module switches to enter a takeover mode, and the step of taking over the operation of the slave module connected with the takeover module further comprises:
and shielding all operations of the host module on the slave module, replacing the slave module and the host module by a take-over module to finish all command messages which are sent but not finished, and responding to new command messages sent by the host module subsequently.
Wherein the method further comprises:
when the switched-off slave module needs to be switched on, controlling to send a starting instruction to the clock reset module;
when the clock reset module receives the starting instruction, a takeover quitting command is sent to the takeover module; and controlling to open the slave module;
and after receiving the takeover quitting command, the takeover module finishes the current command operation with the host module, quits the current takeover mode, enters a monitoring transparent transmission mode and sends a takeover quitting response to the clock resetting module.
The invention also provides a system for avoiding deadlock of the host accessing the slave, which comprises a host module and at least one slave module connected through a bus interconnection module, wherein a pipe connection module and a clock reset module connected with each pipe connection module and each slave module are arranged between each slave module and the interconnection module; wherein:
the clock resetting module is used for sending a take-over command to the connected take-over module after receiving an instruction for turning off the slave module and controlling to turn off the slave module after receiving a take-over response of the take-over module; when receiving an instruction for starting the slave module, controlling to restart the slave module and sending a takeover exit command to a takeover module connected to the slave module;
the take-over module is a device for avoiding deadlock of the host accessing the slave as described above.
The present invention also provides a computer readable storage medium storing executable instructions that, when executed, implement a method as described above.
The invention also provides a chip, wherein the system for avoiding the deadlock of the host access slave is deployed in the chip.
The embodiment of the invention has the following beneficial effects:
the invention provides a method, a device, a system and a chip for avoiding deadlock of a host access slave. A takeover module operated by a bus is connected between each slave module and the bus interconnection module, and the clock reset module interacts with the takeover module to control the working mode of the takeover module; the receiving module can monitor the execution and response conditions of commands between the host module and the slave module in real time, and when a certain slave module fails or is temporarily closed, the receiving module can be controlled to enter a receiving mode in time through the clock resetting module, so that the receiving module can automatically replace the slave module to complete the receiving and response of all commands. Thereby avoiding the deadlock situation of the host module; the stability of the system is improved;
by implementing the invention, after a certain slave module is turned off (or abnormal), the deadlock of the host module can be avoided without limiting the access of software and resetting all modules in the system, and the robustness and the software friendliness of the system can be greatly improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is within the scope of the present invention for those skilled in the art to obtain other drawings based on the drawings without inventive exercise.
FIG. 1 is a diagram illustrating an application architecture having a master module and a slave module according to the prior art;
FIG. 2 is a schematic flow chart illustrating an embodiment of a method for avoiding deadlock of a master access slave according to the present invention;
FIG. 3 is a diagram illustrating an application architecture involved in the method of the present invention;
fig. 4 is a more detailed flowchart illustrating a takeover process implemented by a takeover module in the method according to the present invention;
FIG. 5 is a more detailed flowchart illustrating the takeover module exiting the takeover process in the method of the present invention;
FIG. 6 is a schematic structural diagram illustrating an embodiment of an apparatus for avoiding deadlock of a master access slave according to the present invention;
fig. 7 is a schematic structural diagram of the snoop transparent transmission processing unit in fig. 6.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.
Fig. 2 is a main flow diagram illustrating an embodiment of a method for avoiding deadlock of a master access slave according to the present invention; in the embodiment, with reference to fig. 3 to 5, the method is applied to an application architecture as shown in fig. 3, where the application architecture includes a master module and at least one slave module connected through a bus interconnection module, a connection module is disposed between each slave module and the interconnection module, and a clock reset module connected to each connection module and the slave module, and the clock reset module receives a software command of a CPU module.
More specifically, the method for avoiding deadlock of the master access slave at least comprises the following steps:
step S10, in the process of communication between the host module and the slave module, the connecting pipe module arranged between the host module and the slave module is in a monitoring transparent transmission mode, and command/response information between the host module and the slave module is monitored in real time and transparent transmission processing is carried out;
in a specific example, the step S10 further includes: the taking-over module transmits the command message from the host module forwarded by the bus interconnection module to the slave module; transmitting a response message from the slave module to the host module through the bus interconnection module;
the takeover module monitors and counts the command and the response message, and records the command type and the access data length when receiving a read command of the host module; when a write command of the host module is received, recording the sending number of write data; and when the received read data is the read command returned by the slave module, recording the number of the received read data.
Step S11, after receiving the takeover command, the takeover module switches to enter a takeover mode, and takes over the operation of the slave module connected with the takeover module, and performs subsequent communication with the host module; it can be understood that, in a specific example, when a certain slave module needs to enter a low power consumption operating mode, or a system detects that the slave module has an abnormal operation, the clock reset module sends a takeover command to a takeover module connected to the slave module;
in a specific example, the step S11 further includes:
the take-over module shields all operations of the host module on the slave module, replaces the slave module and the host module by the take-over module to finish all command messages which are sent but not finished, and responds to new command messages sent by the host module subsequently.
In a specific application, for the operation that the master module has sent to the slave module before, but the slave module has not completed response due to the exception, the operation is all completed by the takeover module, so that the deadlock situation in the prior art is avoided. Specifically, for a write command that has been sent by the host module, according to the monitored command execution condition, if write data has already been sent for a part or has not yet started to be sent, the takeover module is responsible for sending write data corresponding to all unfinished write commands; if the slave module returns a write response, the take-over module is responsible for receiving the response; if the slave module returns the read data, the takeover module is responsible for receiving the write data.
When the slave unit is in the off mode, the master module can still access the slave module, and at this time, the takeover module is responsible for receiving all commands and completing all response operations.
Step S12, after receiving the takeover quitting command, the takeover module completes the current command operation with the host module (i.e. all the commands in execution return responses), and quits the current takeover mode, and enters the monitoring transparent transmission mode.
Referring to fig. 4 and 5, in a more detailed example, the method for avoiding deadlock of master access slave includes at least the following steps:
step S20, in the process of communication between the host module and the slave module, the connecting pipe module arranged between the host module and the slave module is in a monitoring transparent transmission mode, and command/response information between the host module and the slave module is monitored in real time and transparent transmission processing is carried out;
specifically, in this step, the takeover module transparently transmits the command message from the master module, which is forwarded by the bus interconnection module, to the slave module; transmitting a response message from the slave module to the host module through the bus interconnection module;
the takeover module monitors and counts the command and the response message, and records the command type and the access data length when receiving a read command of the host module; when a write command of the host module is received, recording the sending number of write data; and when the received read data is the read command returned by the slave module, recording the number of the received read data.
Step S21, when detecting that a slave module needs to enter a low-power-consumption working mode or abnormal working occurs, controlling to send an instruction for turning off the slave module to a clock reset module, and sending a take-over command to a take-over module connected with the slave module by the clock reset module;
step S22, after receiving the takeover command, the takeover module switches to enter a takeover mode, takes over the operation of the slave module connected with the takeover mode, performs subsequent communication with the host module, and returns a takeover response to the clock reset module;
more specifically, in this step, all operations of the master module on the slave module are shielded, all issued command messages which are not yet completed are completed by the takeover module instead of the slave module and the master module, and new command messages subsequently issued by the master module are responded.
And S23, after the clock reset module receives the take-over response, the clock reset module controls to switch off the slave module, the clock reset module switches off the slave module by switching off the clock of the slave module and effectively resetting, and the slave module enters a switch-off mode.
Step S30, when the turned-off slave module needs to be turned on, controlling to send a starting instruction to the clock reset module;
step S31, when the clock reset module receives the starting instruction, the clock reset module sends a takeover quitting command to the takeover module; and controlling to open the slave module; specifically, the clock reset module enables the slave module to enter a normal working mode by turning on and resetting the clock corresponding to the slave module;
and step S32, after receiving the takeover quitting command, the takeover module completes the current command operation with the host module, quits the current takeover mode, enters the monitoring transparent transmission mode, and sends a takeover quitting response to the clock reset module.
It will be appreciated that in embodiments of the present invention, by providing a takeover module that integrates the functions of the slave modules, when the takeover module is in a takeover mode, it is able to implement all the functions of the corresponding slave modules. By arranging the take-over module, when the slave module fails or is shut down, the take-over module can work instead of the slave module, so that a deadlock condition caused by the failure or the turn-off of the slave when the host accesses the slave can be avoided; and the situation that the slave is shut down sometimes happens, the invention is implemented, even if the situation that the takeover module has a fault is considered, the overall probability of deadlock of the host is greatly reduced.
Fig. 6 is a schematic structural diagram illustrating an embodiment of an apparatus for avoiding deadlock of a master access slave according to the present invention. In this embodiment, the apparatus 1 for avoiding deadlock of a master access slave is disposed in a takeover module shown in fig. 3, the takeover module is disposed between the master module and the slave module, and the apparatus 1 at least includes:
the monitoring and transparent transmission processing unit 10 is used for being in a monitoring and transparent transmission mode in the communication process of the host module and the slave module, monitoring command/response information between the host module and the slave module in real time and performing transparent transmission processing;
the takeover processing unit 11 is configured to switch to enter a takeover mode after receiving a takeover command, perform takeover processing on operations of the slave module connected to the takeover mode, and perform subsequent communication with the master module;
more specifically, the takeover processing unit 11 further includes:
and the shielding processing unit is used for shielding all operations of the host module on the slave module, replacing the slave module and the slave module by a take-over module to finish all command messages which are sent but not finished, and responding to new command messages sent by the host module subsequently.
And the takeover exit unit 12 is configured to complete a current command operation with the host module after receiving the takeover exit command, exit the current takeover mode, and enter the monitoring transparent transmission mode.
More specifically, the snoop transparent transmission processing unit 10 further includes:
a transparent transmission processing unit 100, configured to transmit the command message from the host module forwarded by the bus interconnection module to the slave module; transmitting a response message from the slave module to the host module through the bus interconnection module;
the monitoring processing unit 101 is used for monitoring and counting the command and the response message, and recording the command type and the access data length when the received command is a read command of the host module; when a write command of the host module is received, recording the sending number of write data; and when the received read data is the read command returned by the slave module, recording the number of the received read data.
For more details, reference may be made to and combined with the foregoing description of fig. 2 to 5, which is not repeated herein.
In another aspect of the present invention, a system for avoiding deadlock of a master access slave is further provided, and a general architecture of the system can be shown in fig. 3, where the system at least includes a master module and at least one slave module connected through a bus interconnection module, a connection pipe module is disposed between each slave module and the interconnection module, and a clock reset module connected to each connection pipe module and each slave module; wherein:
the clock resetting module is used for sending a take-over command to the connected take-over module after receiving an instruction for turning off the slave module and controlling to turn off the slave module after receiving a take-over response of the take-over module; when receiving an instruction for starting the slave module, controlling to restart the slave module and sending a takeover exit command to a takeover module connected to the slave module;
the take-over module is provided with the device for avoiding the deadlock of the master access slave, which is described in the foregoing fig. 6 and fig. 7.
For more details, reference may be made to and combined with the foregoing description of fig. 6 and 7, which are not repeated herein.
The present invention also provides a computer readable storage medium storing executable instructions that, when executed, implement the method as described in the foregoing fig. 2 to 5. For more details, reference may be made to and the above description of fig. 2 to 5, which are not repeated herein.
The invention also provides a chip, wherein the system for avoiding deadlock of the host access slave is deployed in the chip. For more details, reference may be made to the foregoing description of fig. 2 to 7, which is not repeated herein.
The embodiment of the invention has the following beneficial effects:
the invention provides a method, a device, a system and a chip for avoiding deadlock of a host access slave. A takeover module operated by a bus is connected between each slave module and the bus interconnection module, and the clock reset module interacts with the takeover module to control the working mode of the takeover module; the receiving module can monitor the execution and response conditions of commands between the host module and the slave module in real time, and when a certain slave module breaks down or is temporarily closed, the receiving module can be controlled to enter a receiving mode in time through the clock resetting module, so that the receiving module can automatically replace the slave module to complete the receiving and response of all commands. Thereby avoiding the deadlock situation of the host module; the stability of the system is improved;
by implementing the invention, after a certain slave module is turned off (or abnormal), the access of software is not required to be limited, and all modules in the system are not required to be reset, so that the condition of deadlock of the host module can be avoided, and the robustness and software friendliness of the system can be greatly improved.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (13)
1. A method for avoiding deadlock of a master access slave, comprising at least the following steps:
in the communication process of the host module and the slave module, a connecting pipe module arranged between the host module and the slave module is in a monitoring transparent transmission mode, and command/response information between the host module and the slave module is monitored in real time and is subjected to transparent transmission processing;
after receiving the take-over command, the take-over module is switched to enter a take-over mode, and takes over the operation of the slave module connected with the take-over module, and performs subsequent communication with the host module;
after receiving the command of quitting takeover, the takeover module completes the current command operation with the host module, quits the current takeover mode and enters the monitoring transparent transmission mode.
2. The method of claim 1, wherein the step of monitoring and transparently transmitting information between the master module and the slave module in real time further comprises:
the take-over module transmits the command message from the host module forwarded by the bus interconnection module to the slave module; the response message from the slave module is transmitted to the host module through the bus interconnection module;
the take-over module monitors and counts the command message and the response message, and records the command type and the access data length when receiving a read command of the host module; when a write command of the host module is received, recording the sending number of write data; and when the received read data is the read command returned by the slave module, recording the number of the received read data.
3. The method of claim 2, wherein after receiving the takeover command, the takeover module switches to a takeover mode, and the step of performing takeover processing on the operation of the slave module connected thereto further comprises:
and shielding all response operations of the host module to the slave module, replacing the slave module and the host module by a take-over module to finish all command messages which are sent but not finished, and responding to new command messages sent by the host module subsequently.
4. A device for avoiding deadlock of a master access slave is characterized in that the device is arranged between a master module and a slave module and at least comprises:
the monitoring and transparent transmission processing unit is used for being in a monitoring and transparent transmission mode in the communication process of the host module and the slave module, monitoring command/response information between the host module and the slave module in real time and performing transparent transmission processing;
the take-over processing unit is used for switching into a take-over mode after receiving the take-over command, taking over the operation of the slave module connected with the take-over processing unit and carrying out subsequent communication with the host module;
and the takeover exit unit is used for completing the current command operation between the takeover exit unit and the host module after receiving the takeover exit command, exiting the current takeover mode and entering the monitoring transparent transmission mode.
5. The apparatus of claim 4, wherein the snoop pass-through processing unit further comprises:
the transparent transmission processing unit is used for transmitting the command message from the host module forwarded by the bus interconnection module to the slave module; transmitting a response message from the slave module to the host module through the bus interconnection module;
the monitoring processing unit is used for monitoring and counting the command and the response message, and recording the command type and the access data length when the received command is a read command of the host module; when a write command of the host module is received, recording the sending number of write data; and when the received read data is the read command returned by the slave module, recording the number of the received read data.
6. The apparatus of claim 5, wherein the takeover processing unit further comprises:
and the shielding processing unit is used for shielding all operations of the host module on the slave module, replacing the slave module and the host module by the take-over module to finish all command messages which are sent but not finished, and responding to new command messages sent by the host module subsequently.
7. A method for avoiding deadlock of a master access slave, comprising at least the following steps:
in the communication process of the host module and the slave module, the connecting pipe module arranged between the host module and the slave module is in a monitoring transparent transmission mode, and monitors command/response information between the host module and the slave module in real time and carries out transparent transmission processing;
when a slave module is detected to need to enter a low-power-consumption working mode or abnormal working occurs, controlling to send a command for turning off the slave module to a clock reset module, and sending a take-over command to a take-over module connected with the slave module by the clock reset module;
after receiving the takeover command, the takeover module switches to enter a takeover mode, takes over the operation of the slave module connected with the takeover mode, performs subsequent communication with the host module, and returns a takeover response to the clock reset module;
and after receiving the take-over response, the clock reset module controls to turn off the slave module.
8. The method of claim 7, wherein the step of monitoring and transparently transmitting information between the master module and the slave module in real time further comprises:
the taking-over module transmits the command message from the host module forwarded by the bus interconnection module to the slave module; transmitting a response message from the slave module to the host module through the bus interconnection module;
the takeover module monitors and counts the command and the response message, and records the command type and the access data length when receiving a read command of the host module; when a write command of the host module is received, recording the sending number of write data; and when the received read data is the read command returned by the slave module, recording the number of the received read data.
9. The method as claimed in claim 8, wherein the step of switching the takeover module into the takeover mode after receiving the takeover command from the clock reset module, and the step of taking over the operation of the slave module connected thereto further comprises:
and shielding all operations of the host module on the slave module, replacing the slave module and the host module by a take-over module to finish all command messages which are sent but not finished, and responding to new command messages sent by the host module subsequently.
10. The method of claim 9, wherein the method further comprises:
when the switched-off slave module needs to be switched on, controlling to send a starting instruction to the clock reset module;
when the clock reset module receives the starting instruction, a takeover quitting command is sent to the takeover module; and controlling to open the slave module;
and after receiving the takeover quitting command, the takeover module finishes the current command operation with the host module, quits the current takeover mode, enters the monitoring transparent transmission mode and sends a takeover quitting response to the clock reset module.
11. A system for avoiding deadlock of a host access slave is characterized by comprising a host module and at least one slave module connected through a bus interconnection module, wherein a pipe connection module and a clock reset module connected with each pipe connection module and each slave module are arranged between each slave module and the interconnection module; wherein:
the clock resetting module is used for sending a take-over command to the connected take-over module after receiving an instruction for turning off the slave module and controlling to turn off the slave module after receiving a take-over response of the take-over module; when receiving an instruction for starting the slave module, controlling to restart the slave module and sending a takeover exit command to a takeover module connected to the slave module;
the take-over module is provided with the device for avoiding the deadlock of the master access slave according to any one of claims 4 to 6.
12. A computer readable storage medium storing executable instructions, wherein the executable instructions, when executed, implement the method of any one of claims 1 to 3.
13. A chip having the system for avoiding deadlock for a master access slave as claimed in claim 11 deployed therein.
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