CN114546912A

CN114546912A - Interrupt expansion method for server system

Info

Publication number: CN114546912A
Application number: CN202210049204.9A
Authority: CN
Inventors: 范里政; 杨有桂; 刘付东
Original assignee: Phytium Technology Co Ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2022-01-17
Filing date: 2022-01-17
Publication date: 2022-05-27

Abstract

The invention discloses an interrupt expansion method for a server system, which comprises the following steps: storing an interrupt ID through an interrupt status register, wherein the interrupt ID is mapped with the slave machines in a one-to-one correspondence manner; the CPU reads the value of the interrupt state register, executes different interrupt service programs according to different IDs, simultaneously clears the interrupt, and executes the interrupt request task on the other thread. The invention has the advantages of simple principle, simple and convenient operation, wide application range and the like.

Description

Interrupt expansion method for server system

Technical Field

The invention mainly relates to the technical field of server management and control, in particular to an interrupt expansion method for a server system.

Background

In order to manage the servers, a server management and control unit (BMC) is added to the current server system. The master-slave relationship between the CPU and the BMC is as follows: the CPU is a master device, and the BMC is a slave device. The CPU (master) may initiate access to the BMC, but the BMC (slave) does not have such permission. Such a limitation may cause the BMC to be unable to initiate a command to the CPU, and cause the BMC to be unable to perform such actions as shutdown. In order to avoid the problems, most processors receive the interrupt signal corresponding to the BMC by using the GPIO with the interrupt function, and then execute the corresponding functional operation, so that the problems are avoided. But this also greatly wastes the GPIO port that the CPU would otherwise not have been.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides the interrupt expansion method for the server system, which has the advantages of simple principle, simple and convenient operation and wide application range.

In order to solve the technical problems, the invention adopts the following technical scheme:

an outage augmentation method for a server system, comprising:

storing an interrupt ID in an interrupt status register, wherein the interrupt ID is mapped with slave machines of a server system in a one-to-one correspondence manner;

a CPU of a host in the server system reads an interrupt ID value in an interrupt status register;

the CPU of the host in the server system executes a corresponding interrupt service program according to the read interrupt ID value;

the CPU of the host in the server system clears the interrupt and executes the interrupt requesting task in another thread.

As a further improvement of the invention: the master and the slaves in the server system use the same clock source, and one master and a plurality of slaves are connected together through an interrupt line.

As a further improvement of the invention: the slave machine comprises a BMC which initiates an interrupt command to the CPU.

As a further improvement of the invention: and setting level conversion when the BMC is connected with the CPU.

As a further improvement of the invention: and determining interrupt IDs used by a plurality of slaves in the server system and the interrupt ID of the master, and storing the interrupt IDs in an interrupt status register.

As a further improvement of the invention: the interrupt state register adopts uart virtual serial port interrupt; and after the interrupt is sent out, the CPU of the host carries out interrupt operation through a uart virtual serial port according to the set interrupt ID.

As a further improvement of the invention: the interrupt status register is provided with interrupt IDs used by a plurality of slaves and an interrupt ID of a master.

As a further improvement of the invention: the definition of the interrupt ID in the interrupt status register adopts a user-defined mode, so that the slave can judge that the interrupt ID corresponds to the virtual serial port function.

As a further improvement of the invention: when the interrupt ID needs to be modified, the corresponding value needing to be determined is directly written.

As a further improvement of the invention: the host's CPU chooses to walk different branch threads based on different interrupt IDs.

Compared with the prior art, the invention has the advantages that:

1. the interrupt expansion method for the server system has the advantages of simple principle, simple and convenient operation and wide application range, does not occupy the limited GPIO pin with the interrupt function in the CPU, can maximally improve the device occupancy of the SerIRQ, and reduces the complexity of hardware design. The invention adopts the interruption that other fixed modules do not occupy to realize a plurality of expansion functions, such as: and initiating requests of shutdown, restart, CPU state acquisition and the like to the CPU. Moreover, after the invention is adopted, the number of the interrupted devices can be flexibly increased and decreased, and the later development and maintenance are convenient.

2. According to the interrupt expansion method for the server system, the host CPU in the server system cannot directly execute interrupt, and the CPU can read the value of the interrupt status register. The interrupt status register stores an interrupt ID (interrupt number) mapped in one-to-one correspondence with the peripheral (slave). Then, different interrupt service programs are executed according to different interrupt IDs, the interrupt is cleared at the same time, and the interrupt request task is executed on the other thread.

Drawings

FIG. 1 is a schematic flow chart of a method in a specific application example of the present invention.

FIG. 2 is a diagram illustrating the number of interrupts supported by SerIRQ.

Fig. 3 is a schematic diagram of the topology of the control in a specific application example of the invention.

FIG. 4 is a diagram illustrating register settings in an exemplary embodiment of the present invention.

Fig. 5 is a schematic diagram of the topology of the control in a specific application example of the invention.

Detailed Description

The invention will be described in further detail below with reference to the drawings and specific examples.

FIG. 2 is a diagram illustrating the number of interrupts supported by the SerIRQ. In the framework of the master and the slave of the server system, an LPC interface is generally provided, and SerIRQ interrupt is attached to the LPC interface. It is usually used by a slave (proprietary device) that is adapted to the SerIRQ interrupt, although such a slave (proprietary device) includes the BMC. Fixed modules in the BMC (e.g., SOL modules, superIO modules, ACPI modules, etc.) will send commands to the CPU via the interrupt. Obviously, the above fixed modules are all limited, and SerIRQ is a serial interrupt that can carry multiple devices, so the present invention will adopt an interrupt that is not occupied by other fixed modules to implement several expansion functions, such as: and initiating requests of shutdown, restart, CPU state acquisition and the like to the CPU.

As shown in fig. 1, the interrupt expansion method for a server system according to the present invention enables a host and a slave in the server system to use the same clock source, and connects the host and the multiple slaves together through an interrupt line; the slave comprises a BMC; firstly, determining interrupt IDs (interrupt numbers) used by a plurality of slaves (proprietary devices) and interrupt IDs (interrupt numbers) of a host and storing the interrupt IDs (interrupt numbers) into an interrupt state register; the interrupt state register adopts uart virtual serial port interrupt; after the interrupt is sent, the CPU of the host needs to perform an interrupt operation through the uart virtual serial port according to the set interrupt ID.

By adopting the scheme of the invention, the CPU can not directly execute the interrupt, and the CPU can read the value of the interrupt status register. The interrupt status register stores an interrupt ID (interrupt number) mapped in one-to-one correspondence with the peripheral (slave). Then, different interrupt service programs are executed according to different interrupt IDs, the interrupt is cleared at the same time, and the interrupt request task is executed on the other thread.

In a specific application example, an interrupt ID (interrupt number) used by a plurality of slaves (exclusive devices) and an interrupt ID (interrupt number) of a master are set in the register and stored in the form of a specific numerical value. When the modification is needed, the corresponding value which needs to be determined is directly written.

In a specific application example, the definition of the register interrupt ID may be adjusted by the 7 th bit to the 4 th bit of the register in fig. 2, but the server of the opposite party needs to know that the interrupt ID (interrupt number) corresponds to the virtual serial port function. Therefore, the invention can customize the interrupt ID, so that more devices can be added to the interrupt.

SerIRQ interrupts, which accompany LPC interfaces, are typically used by proprietary devices that conform to SerIRQ interrupts, including BMC, of course. Fixed modules in the BMC, such as SOL modules, superIO modules, ACPI modules, etc., will send commands to the CPU through the interrupt. The above modules are all limited, and SerIRQ is a serial interrupt that can carry multiple devices, so this scheme will adopt interrupts that other modules do not occupy to implement as follows: and initiating requests of shutdown, restart, CPU state acquisition and the like to the CPU.

Specific application example 1: referring to fig. 3, the present invention is described by taking an example that the BMC initiates a shutdown command to the CPU. The hardware connection of the present invention and the conventional LPC interface realize the connection of the master and the slave without adjustment, so the description of the hardware is omitted.

The specific process of the invention is as follows:

step S1: and determining the interrupts used by all the devices, including the slave and the master in the server system, determining the value of the register in the figure 4 according to the interrupt ID selected by the slave and the master, and writing the determined value.

Step S2: by rewriting the value of 0x1e787020 of the BMC in the slave to 0x23, an interrupt request can be issued to the CPU of the master. In this example, the register itself is a virtual serial interrupt for uart.

Step S3: after the interrupt is issued, the CPU of the host needs to go through the operation flow of shutdown based on the interrupt ID set in step S1 described above.

Therefore, the interruption of the virtual serial port of uart is used, and the function of shutdown operation is realized.

Specific application example 2: referring to fig. 5, when the BMC detects that any component such as a fan and a temperature is abnormal in the peripheral of the whole device, the BMC can report to the CPU of the Server through the interrupt, so that the CPU performs down-conversion, task transfer and other work, thereby preventing the whole computing node from being failed due to the abnormality of the component, and further preventing a large amount of data from being lost.

The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.

Claims

1. An interrupt propagation method for a server system, comprising:

2. The outage augmentation method for server systems according to claim 1, characterized in that: the master and the slaves in the server system use the same clock source, and one master and a plurality of slaves are connected together through an interrupt line.

3. The outage augmentation method for server systems according to claim 2, characterized in that: the slave machine comprises a BMC which initiates an interrupt command to the CPU.

4. The outage augmentation method for server systems according to claim 3, characterized in that: and setting level conversion when the BMC is connected with the CPU.

5. The outage extension method for the server system according to any one of claims 1-4, characterized by: and determining interrupt IDs used by a plurality of slaves in the server system and the interrupt ID of the master, and storing the interrupt IDs in an interrupt status register.

6. The outage extension method for the server system according to any one of claims 1-4, characterized by: the interrupt state register adopts uart virtual serial port interrupt; and after the interrupt is sent out, the CPU of the host carries out interrupt operation through a uart virtual serial port according to the set interrupt ID.

7. The outage extension method for the server system according to any one of claims 1-4, characterized by: the interrupt status register is provided with interrupt IDs used by a plurality of slaves and an interrupt ID of a master.

8. The outage augmentation method for server systems according to claim 7, characterized in that: the definition of the interrupt ID in the interrupt status register adopts a user-defined mode, so that the slave can judge that the interrupt ID corresponds to the virtual serial port function.

9. The outage augmentation method for server systems according to claim 7, characterized in that: when the interrupt ID needs to be modified, the corresponding value needing to be determined is directly written.

10. The outage extension method for the server system according to any one of claims 1-4, characterized by: the host's CPU chooses to walk different branch threads based on different interrupt IDs.