CN115980197A

CN115980197A - Ultrasonic control circuit, driving method thereof and ultrasonic monitoring device

Info

Publication number: CN115980197A
Application number: CN202211634436.7A
Authority: CN
Inventors: 王玉波; 李扬冰; 王雷; 崔亮; 赵宇鹏; 马媛媛; 曹永刚; 佟月; 李彦正
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2022-12-19
Filing date: 2022-12-19
Publication date: 2023-04-18

Abstract

The application provides an ultrasonic control circuit, a driving method thereof and an ultrasonic monitoring device, and relates to the technical field of ultrasonic waves. The ultrasonic control circuit includes: the ultrasonic sensor is electrically connected with the first node and is configured to be capable of receiving echo signals of an object and writing the echo signals into the first node; and a first reset sub-circuit electrically connected to the first reset signal line, the first control signal line and the first node, configured to reset the first node under control of a first reset signal of the first reset signal line when the first reset sub-circuit is in a first state, and configured to not operate when the first reset sub-circuit is in a second state.

Description

Ultrasonic control circuit, driving method thereof and ultrasonic monitoring device

Technical Field

The application relates to the technical field of ultrasonic waves, in particular to an ultrasonic control circuit, a driving method thereof and an ultrasonic monitoring device.

Background

With the development of science and technology, ultrasonic sensors are widely used, for example, in medical diagnosis, medical treatment, etc., and a large-area integrated flexible ultrasonic sensor is one of them.

In the existing large-area integrated flexible ultrasonic sensor, a control circuit often has the problems of background noises (background noises) such as thermal noise, flicker noise, shot noise and the like, the background noises may cause ultrasonic signal distortion and the like, the effectiveness of an image cannot be ensured, and the user experience is poor.

Disclosure of Invention

The embodiment of the application provides an ultrasonic control circuit, a driving method thereof and an ultrasonic monitoring device, and the ultrasonic control circuit can effectively reduce or even eliminate background noise and improve the signal-to-noise ratio.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

in one aspect, an ultrasound control circuit is provided, the ultrasound control circuit comprising:

the ultrasonic sensor is electrically connected with the first node and is configured to be capable of receiving an echo signal of an object and writing the echo signal into the first node;

a first reset sub-circuit electrically connected to a first reset signal line, a first control signal line, and the first node, configured to reset the first node under control of a first reset signal of the first reset signal line in a first state, and configured to be disabled in a second state;

a second reset sub-circuit electrically connected to a second reset signal line, a ground terminal, and a second node, and configured to reset the second node under control of a second reset signal of the second reset signal line;

a signal transmission sub-circuit electrically connected to a second control signal line, a third node and the first node, and configured to write a signal of the first node into the third node under control of a second control signal of the second control signal line;

an output sub-circuit electrically connected to a gate signal line, the third node, a voltage signal line, and the second node, and configured to write a voltage signal of the voltage signal line and the signal of the third node into the second node under control of a gate signal of the gate signal line and the signal of the third node;

a storage sub-circuit electrically connected to the second node, a third control signal line, and a processing sub-circuit, configured to write a signal of the second node into the processing sub-circuit under control of a third control signal of the third control signal line;

a processing sub-circuit configured to receive and process the signal of the second node.

Optionally, the ultrasound control circuit further includes a regulator sub-circuit, the regulator sub-circuit is electrically connected to the third node, a regulating signal line and the ground terminal, and is configured to control an electrical signal of the third node under the control of a regulating signal of the regulating signal line.

Optionally, the first reset sub-circuit includes a first transistor;

the control electrode of the first transistor is electrically connected with the first reset signal line, the first electrode of the first transistor is electrically connected with the first control signal line, and the second electrode of the first transistor is electrically connected with the first node.

Optionally, the first reset sub-circuit includes a first transistor;

the control electrode of the first transistor is electrically connected with the first reset signal line, the first electrode of the first transistor is electrically connected with the voltage signal line, and the second electrode of the first transistor is electrically connected with the first node.

Optionally, the second reset sub-circuit includes a fifth transistor;

a control electrode of the fifth transistor is electrically connected to the second reset signal line, a first electrode is electrically connected to the ground terminal, and a second electrode is electrically connected to the second node.

Optionally, the signal transmission sub-circuit includes a second transistor;

the control pole of the second transistor is electrically connected with the second control signal line, the first pole of the second transistor is electrically connected with the first node, and the second pole of the second transistor is electrically connected with the third node.

Optionally, the output sub-circuit includes a third transistor, a fourth transistor and a first capacitor;

a control electrode of the third transistor is electrically connected with the third node, a first electrode of the third transistor is electrically connected with the voltage signal wire, and a second electrode of the third transistor is electrically connected with the second node;

a control electrode of the fourth transistor is electrically connected to the gate signal line, a first electrode is electrically connected to the second node, and a second electrode is electrically connected to the third node;

the first end of the first capacitor is electrically connected with the third node, and the second end of the first capacitor is electrically connected with the ground terminal.

Optionally, the storage sub-circuit includes at least a sixth transistor and a second capacitor;

a control electrode of the sixth transistor is electrically connected with a first third control signal line, a first electrode of the sixth transistor is electrically connected with the second node, and a second electrode of the sixth transistor is electrically connected with the first end of the second capacitor;

the first end of the second capacitor is electrically connected with the processing sub-circuit, and the second end of the second capacitor is electrically connected with the grounding terminal.

Optionally, the storage sub-circuit includes the sixth transistor, the second capacitor, a seventh transistor, and a third capacitor;

a control electrode of the seventh transistor is electrically connected with a second third control signal line, a first electrode of the seventh transistor is electrically connected with the second node, and a second electrode of the seventh transistor is electrically connected with the first end of the third capacitor;

the first end of the third capacitor is electrically connected with the processing sub-circuit, and the second end of the third capacitor is electrically connected with the grounding terminal.

Optionally, the processing sub-circuit comprises at least an amplifier;

the first end of the amplifier is electrically connected with the storage sub-circuit.

Optionally, the adjusting sub-circuit includes at least one switching transistor and an adjusting capacitor;

a control electrode of the switching transistor is electrically connected with the adjusting signal line, a first electrode of the switching transistor is electrically connected with the adjusting capacitor, and a second electrode of the switching transistor is electrically connected with the third node;

and the second end of the adjusting capacitor is electrically connected with the grounding end.

In another aspect, an ultrasound monitoring device is provided, comprising at least one ultrasound control circuit as described above.

In still another aspect, a driving method is provided for driving the ultrasonic control circuit;

the method comprises the following steps:

writing a first reset signal to the first reset signal line in a first state;

in the second state phase, the first reset signal is not written to the first reset signal line.

An embodiment of the present application provides an ultrasound control circuit, including: the ultrasonic sensor is electrically connected with the first node and is configured to be capable of receiving an echo signal of an object and writing the echo signal into the first node; a first reset sub-circuit electrically connected to the first reset signal line, the first control signal line, and the first node, configured to reset the first node under control of a first reset signal of the first reset signal line in a first state, and to be inoperative in a second state; a second reset sub-circuit electrically connected to the second reset signal line, the ground terminal, and the second node, and configured to reset the second node under control of a second reset signal of the second reset signal line; a signal transmission sub-circuit electrically connected to the second control signal line, the third node, and the first node, and configured to write a signal of the first node into the third node under control of a second control signal of the second control signal line; an output sub circuit electrically connected to the gate signal line, the third node, the voltage signal line, and the second node, and configured to write the voltage signal of the voltage signal line and the signal of the third node into the second node under control of the gate signal line and the signal of the third node; a storage sub-circuit electrically connected to the second node, the third control signal line, and the processing sub-circuit, and configured to write a signal of the second node into the processing sub-circuit under control of a third control signal of the third control signal line; a processing sub-circuit configured to receive and process a signal of the second node.

In this way, when the ultrasonic control circuit is in the first state, since the first reset sub-circuit is configured to reset the first node under the control of the first reset signal line, the echo signal does not affect the potential of the third node no matter whether the ultrasonic sensor transmits the echo signal, the third node can maintain the first reset signal of the first reset signal line, and at this time, the ultrasonic control circuit can obtain the first electric signal with noise floor. When the ultrasonic control circuit is in the second state, because the first reset sub-circuit does not work, if the ultrasonic sensor transmits an echo signal, the echo signal can affect the electric potential of the third node, and the electric potential of the third node changes, at the moment, the ultrasonic control circuit can obtain a second electric signal of a signal with background noise and an effective signal. Therefore, the effective signal of the ultrasonic control circuit is obtained by subtracting the first electric signal from the second electric signal, and further can be better analyzed according to the effective signal. Therefore, the method and the device effectively reduce or even eliminate the bottom noise of the ultrasonic control circuit and improve the signal to noise ratio, so that the ultrasonic control circuit with low noise is obtained, and the user experience is good.

The foregoing description is only an overview of the technical solutions of the present application, and the present application can be implemented according to the content of the description in order to make the technical means of the present application more clearly understood, and the following detailed description of the present application is given in order to make the above and other objects, features, and advantages of the present application more clearly understandable.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic diagram of an ultrasonic sensor emitting sound waves according to an embodiment of the present application;

fig. 2 is a schematic diagram illustrating a principle that an ultrasonic sensor receives sound waves according to an embodiment of the present application;

FIG. 3 is a schematic diagram of another ultrasonic sensor provided in the embodiments of the present application for receiving sound waves;

fig. 4 is a diagram of a practical application of an ultrasonic sensor provided in an embodiment of the present application;

FIG. 5 is a schematic diagram of an ultrasound control circuit provided in an embodiment of the present application;

fig. 6 is a driving timing diagram of an ultrasonic control circuit according to an embodiment of the present application;

FIG. 7 is a schematic diagram of yet another ultrasound control circuit provided by an embodiment of the present application;

FIG. 8 is a timing diagram of the driving of another ultrasound control circuit provided in the embodiments of the present application;

FIG. 9 is a schematic diagram of yet another ultrasound control circuit provided in an embodiment of the present application;

FIG. 10 is a schematic diagram of an electrical connection of two ultrasound control circuits provided by an embodiment of the present application;

fig. 11-16 are schematic driving diagrams of the ultrasonic control circuit of fig. 9 at the driving timing of fig. 6.

Detailed Description

The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the embodiments of the present application, the words "first", "second", "third", "fourth", "fifth", "sixth", "seventh", "eighth", "ninth", "8 + n", "4 + n" and the like are used to distinguish the same or similar items with basically the same functions and actions, and are only used for clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

In the embodiments of the present application, "at least one" means one or more unless specifically defined otherwise.

In the embodiment of the present invention, the gate of the transistor is referred to as a control electrode, and one of the source and the drain is referred to as a first electrode and the other is referred to as a second electrode. In the embodiments of the present invention, the first electrodes of all the transistors are referred to as drains, and the second electrodes are referred to as sources.

In the embodiments of the present invention, the term "electrically connected" may mean that two components are directly electrically connected, or may mean that two components are electrically connected via one or more other components; "electrically connected" may mean electrically connected by a wire, or may mean electrically connected by a radio signal.

With the development of science and technology, ultrasonic waves are applied more and more widely, for example, the ultrasonic wave can be applied to the fields of industrial nondestructive inspection, distance measurement and thickness measurement, agricultural breeding, seedling culture and spawning promotion, biological and medical diagnosis and treatment, fingerprint identification in consumer electronics and the like, so that ultrasonic sensors utilizing ultrasonic waves are also researched more and more widely.

The generation principle and the reception principle of ultrasonic waves in the ultrasonic sensor of fig. 1 and 2 are explained below, respectively. Referring to fig. 1 and 2, the ultrasonic sensor includes an upper electrode (Top electrode), a piezoelectric material layer (polymer), and a lower electrode (Bottom electrode), the piezoelectric material layer being disposed between the upper electrode and the lower electrode. Wherein the upper electrode and the lower electrode are arranged in a whole layer.

Referring to fig. 1, a voltage having a phase difference may be input between the upper electrode and the lower electrode, for example, an Alternating Current (AC) voltage may be input to the upper electrode and the lower electrode, and at this time, the piezoelectric material layer may be deformed to generate an acoustic wave, where the acoustic wave is an ultrasonic wave.

Referring to fig. 2, an object reflects sound waves, and the sound waves are converted into an AC voltage when reflected to the piezoelectric material layer, and at this time, if the upper electrode is grounded, the lower electrode can serve as a receiving terminal to output the AC voltage.

The material of the piezoelectric material layer may include a polymer piezoelectric material, for example: PVDF (Polyvinylidene Fluoride), PVDF-TrFE (Poly (Vinylidene Fluoride-Co-trifluorethylene), polyvinylidene Fluoride Trifluoroethylene), and the like; alternatively, the material of the piezoelectric material layer may include inorganic materials such as: alN (aluminum nitride), PZT (lead zirconate titanate piezoelectric ceramic), znO (zinc oxide), and the like.

The principle of the ultrasonic wave in the ultrasonic sensor of fig. 3 will be described below. Referring to fig. 3, the ultrasonic sensor includes a lower electrode (Ag), a piezoelectric material layer (PVDF), an upper electrode, a driving circuit (TFT), and a substrate (Glass) sequentially stacked, wherein the lower electrode is disposed in a whole layer, and the upper electrode includes a plurality of sub-electrodes (RX) separately and at intervals.

Referring to fig. 3, PZT emits sound waves to the object, the sound waves reflected by the object are emitted to the ultrasonic sensor, and the ultrasonic sensor receives the sound waves reflected by the object, converts the sound waves into an electric signal, and transmits the electric signal to the TFT driving circuit through the RX electrode. At the moment, the PZT transmits an excitation signal, and the transmitting energy of a PZT sound source is larger.

Note that in fig. 3, the acoustic wave is generated by PZT, and the ultrasonic sensor receives only the acoustic wave. It is of course also possible that the ultrasonic sensor itself generates and receives sound waves, and this is not particularly limited here.

In traditional medical ultrasonic imaging, ultrasonic focusing beams are usually used for detecting human tissues, and due to the fact that the focusing beams are narrow, each time of focusing imaging is linear, after images focused by multiple times of scanning are spliced into a two-dimensional image, a probe is moved and scanned into a three-dimensional image. The technology has the defects of slow imaging speed, complex equipment structure, generally only 30 frames/second and the like. In order to solve the problem, fig. 4 provides a large-area integrated flexible ultrasonic sensor, and referring to fig. 4, the ultrasonic sensor can be integrally covered on the surface of human tissue, such as the back, the belly, the arms, the thighs and other large tissue surfaces of the human body, so as to realize the advantages of high-precision, large-area, multi-dimensional real-time imaging and the like.

However, in the existing large-area integrated flexible ultrasonic sensor, the ultrasonic control circuit often has the bottom noise problems of thermal noise, flicker noise, shot noise and the like, and the bottom noise of the ultrasonic control circuit in the ultrasonic sensor may cause ultrasonic signal distortion and the like, so that the effectiveness of an image cannot be ensured, and the user experience is poor.

In order to solve the above problem, an embodiment of the present application provides an ultrasound control circuit, as shown in fig. 5 and 7, including:

the ultrasonic sensor 1 is electrically connected to the first node P, and is configured to be capable of receiving an echo signal of an object and writing the echo signal into the first node P.

The first Reset sub-circuit 2 is electrically connected to the first Reset signal line Reset1, the first control signal line Drst, and the first node P, and is configured to Reset the first node P under control of a first Reset signal of the first Reset signal line Reset1 when in the first state, and to be disabled when in the second state.

The second Reset sub-circuit 5 is electrically connected to the second Reset signal line Reset2, the ground terminal GND and the second node Q, and configured to Reset the second node Q under the control of a second Reset signal of the second Reset signal line Reset 2.

The signal transmission sub-circuit 3 is electrically connected to the second control signal line Vclose, the third node W, and the first node P, and configured to write a signal of the first node P into the third node W under the control of a second control signal of the second control signal line Vclose.

And an output sub circuit 4 electrically connected to the Gate signal line Gate, the third node W, the voltage signal line VDD, and the second node Q, and configured to write a voltage signal of the voltage signal line VDD and a signal of the third node W into the second node Q under the control of a Gate signal of the Gate signal line Gate and a signal of the third node W.

And a memory sub-circuit 6 electrically connected to the second node Q, the third control signal line Vg, and the processing sub-circuit 7, and configured to write the signal of the second node Q into the processing sub-circuit 7 under the control of the third control signal line Vg.

A processing sub-circuit 7 configured to receive and process the signal of the second node Q.

The echo is not particularly limited, and may include, for example, a sound wave reflected by an object, a sound wave scattered by an object, and the like.

The first state may be a state in which the ultrasonic sensor does not transmit a signal, or a state in which the ultrasonic sensor transmits a signal but the signal does not affect the potential of the third node. At this time, the ultrasonic control circuit outputs an electric signal having a noise floor (noise floor) of the ultrasonic control circuit.

The second state may be a state in which the ultrasonic sensor transmits a signal, and the signal affects the potential of the third node. The ultrasonic control circuit outputs an electric signal having a noise floor (noise floor) of the ultrasonic control circuit and an effective signal, wherein the effective signal is an echo signal of an object.

The specific circuit structures of the first reset sub-circuit, the second reset sub-circuit, the signal transmission sub-circuit, the output sub-circuit, and the processing sub-circuit are not limited as long as the corresponding functions are satisfied.

The first node, the second node, and the third node are defined only for convenience of describing a circuit structure, and the first node, the second node, and the third node are not an actual circuit unit.

An embodiment of the present application provides an ultrasound control circuit, including: the ultrasonic sensor is electrically connected with the first node and is configured to be capable of receiving echo signals of an object and writing the echo signals into the first node; a first reset sub-circuit electrically connected to the first reset signal line, the first control signal line, and the first node, configured to reset the first node under control of a first reset signal of the first reset signal line in a first state, and to be inoperative in a second state; a second reset sub-circuit electrically connected to the second reset signal line, the ground terminal, and the second node, and configured to reset the second node under control of a second reset signal of the second reset signal line; a signal transmission sub-circuit electrically connected to the second control signal line, the third node, and the first node, and configured to write a signal of the first node into the third node under control of a second control signal of the second control signal line; an output sub circuit electrically connected to the gate signal line, the third node, the voltage signal line, and the second node, and configured to write the voltage signal of the voltage signal line and the signal of the third node into the second node under control of the gate signal line and the signal of the third node; a storage sub-circuit electrically connected to the second node, the third control signal line, and the processing sub-circuit, and configured to write a signal of the second node into the processing sub-circuit under control of a third control signal of the third control signal line; a processing sub-circuit configured to receive and process a signal of the second node.

In this way, when the ultrasonic control circuit is in the first state, since the first reset sub-circuit is configured to reset the first node under the control of the first reset signal line, the echo signal does not affect the potential of the third node no matter whether the ultrasonic sensor transmits the echo signal, the third node can maintain the first reset signal of the first reset signal line, and at this time, the ultrasonic control circuit can obtain the first electric signal with noise floor. When the ultrasonic control circuit is in the second state, because the first reset sub-circuit does not work, if the ultrasonic sensor transmits an echo signal, the echo signal can affect the electric potential of the third node, the electric potential of the third node changes, and at the moment, the ultrasonic control circuit can obtain a signal with background noise and a second electric signal of an effective signal. Therefore, the effective signal of the ultrasonic control circuit is obtained by subtracting the first electric signal from the second electric signal, and further can be better analyzed according to the effective signal. Therefore, the application effectively reduces or even eliminates the background noise of the ultrasonic control circuit, and improves the signal to noise ratio, thereby obtaining the ultrasonic control circuit with low noise and having good user experience.

Optionally, referring to fig. 9, the ultrasound control circuit further includes an adjusting sub-circuit 8, the adjusting sub-circuit 8 is electrically connected to the third node W, the adjusting signal line Vgc and the ground terminal GND, and is configured to control an electrical signal of the third node W under the control of an adjusting signal of the adjusting signal line Vgc.

In the ultrasonic control circuit provided by the embodiment of the application, the adjusting sub-circuit is in a working state and in a non-working state, the potential of the third node is different, so that different electric signals can be controlled and output, the acquisition range of ultrasonic echo signals is widened, the ultrasonic control circuit has a piezoelectric signal with a high dynamic range and low noise, and the ultrasonic control circuit can be widely applied.

Alternatively, referring to fig. 5, the first reset sub-circuit 2 includes a first transistor M1; a control electrode of the first transistor M1 is electrically connected to the first Reset signal line Reset1, the first electrode is electrically connected to the first control signal line Drst, and the second electrode is electrically connected to the first node P.

Alternatively, referring to fig. 7, the first reset sub-circuit 2 includes a first transistor M1; the control electrode of the first transistor M1 is electrically connected to the first Reset signal line Reset1, the first electrode is electrically connected to the voltage signal line VDD, and the second electrode is electrically connected to the first node P. Compared with fig. 5, in fig. 7, the first pole of the first transistor M1 is electrically connected to the voltage signal line VDD instead of the first control signal line Drst, so that one power supply design can be saved.

Alternatively, referring to fig. 5 and 7, the second reset sub-circuit 5 includes a fifth transistor M5; the control electrode of the fifth transistor M5 is electrically connected to the second Reset signal Reset2, the first electrode is electrically connected to the ground GND, and the second electrode is electrically connected to the second node Q.

Alternatively, as shown with reference to fig. 5 and 7, the signal transmission sub-circuit 3 includes a second transistor M2; the control electrode of the second transistor M2 is electrically connected to the second control signal line Vclose, the first electrode is electrically connected to the first node P, and the second electrode is electrically connected to the third node W.

Alternatively, referring to fig. 5 and 7, the output sub-circuit 4 includes a third transistor M3, a fourth transistor M4, and a first capacitor Cg; a control electrode of the third transistor M3 is electrically connected to the third node W, the first electrode is electrically connected to the voltage signal line VDD, and the second electrode is electrically connected to the second node Q; a control electrode of the fourth transistor M4 is electrically connected to the Gate signal line Gate, the first electrode is electrically connected to the second node Q, and the second electrode is electrically connected to the third node W; the first end of the first capacitor Cg is electrically connected to the third node W, and the second end is electrically connected to the ground GND.

Alternatively, referring to fig. 5, the memory sub-circuit 6 includes at least a sixth transistor M6 and a second capacitor Cp1; a control electrode of the sixth transistor M6 is electrically connected to the first third control signal line Vg6, the first electrode is electrically connected to the second node Q, and the second electrode is electrically connected to the first end of the second capacitor Cp1; the first terminal of the second capacitor Cp1 is further electrically connected to the processing sub-circuit 7, and the second terminal is electrically connected to the ground GND.

The storage sub-circuit at least comprises a sixth transistor and a second capacitor, and the storage sub-circuit comprises: the storage sub-circuit only comprises a sixth transistor and a second capacitor; alternatively, the memory sub-circuit may include another transistor and another capacitor in addition to the sixth transistor and the second capacitor.

It should be noted that, when the storage sub-circuit only includes the sixth transistor and the second capacitor, the second capacitor needs to store the electrical signal of the ultrasound control circuit in the first state and the electrical signal of the ultrasound control circuit in the second state, and then, after the second capacitor stores the electrical signal of the ultrasound control circuit in a certain state, the sixth transistor needs to be reset first, and then the second capacitor needs to store the electrical signal of the ultrasound control circuit in another state.

Alternatively, referring to fig. 5, the memory sub-circuit 6 includes a sixth transistor M6, a second capacitor Cp1, a seventh transistor M7, and a third capacitor Cp2; a control electrode of the seventh transistor M7 is electrically connected to the second third control signal line Vg7, the first electrode is electrically connected to the second node Q, and the second electrode is electrically connected to the first end of the third capacitor Cp2; the first terminal of the third capacitor Cp2 is further electrically connected to the processing sub-circuit 7, and the second terminal is electrically connected to the ground GND.

Alternatively, as shown with reference to fig. 7, the processing sub-circuit 7 comprises at least an amplifier; the first terminal of the amplifier is electrically connected to the memory sub-circuit 6.

The processing sub-circuit at least comprises an amplifier, and the processing sub-circuit comprises: the processing sub-circuit comprises only an amplifier; alternatively, the processing sub-circuit may comprise, in addition to the amplifier, other components, such as: an ADC (Analog-to-digital Converter), a processor, etc. The processor may be an FPGA (Field Programmable Gate Array), a PC (Personal Computer), a microprocessor, or the like. Fig. 7 shows an example in which the processing sub-circuit includes an instrumentation amplifier 71 and an ADC 72.

The type of the amplifier is not particularly limited, and the amplifier may include an instrumentation amplifier. Referring to fig. 7, the instrumentation amplifier 71 has a first terminal Vi _ P and a second terminal Vi _ N so that an electrical signal can be received through the first terminal Vi _ P and the second terminal Vi _ N.

Alternatively, referring to fig. 9, the adjusting sub-circuit 8 comprises at least one switching transistor M8+ n and an adjusting capacitor C4+ n; a control electrode of the switching transistor M8+ n is electrically connected to the adjustment signal line Vgcn, a first electrode is electrically connected to the adjustment capacitor C4+ n, and a second electrode is electrically connected to the third node W; and the second end of the adjusting capacitor C4+ n is electrically connected with the ground end GND, wherein n is an integer greater than or equal to zero.

The regulation subcircuit comprises at least one switching transistor and a regulation capacitor, and the regulation subcircuit refers to that: the regulating sub-circuit only comprises a switching transistor and a regulating capacitor; alternatively, the adjusting sub-circuit includes a plurality of switching transistors and an adjusting capacitor, and is not limited herein. Fig. 9 is illustrated with the example that the adjustment sub-circuit 8 includes an eighth transistor M8 and a fourth capacitor C4, a ninth transistor M9 and a fifth capacitor C5, an 8+ n transistor M8+ n and a 4+ n capacitor C4+ n.

If the ultrasonic sensor can receive echoes with different intensities, for example, the echo intensity received by the ultrasonic sensor when the ultrasonic sensor is close to the object is higher, and the echo intensity received by the ultrasonic sensor when the ultrasonic sensor is far from the object is lower. When the switch transistor and the adjusting capacitor are additionally arranged in the ultrasonic control circuit, whether the adjusting capacitor is connected to the ultrasonic control circuit or not can be controlled by opening or closing the switch transistor. Specifically, when ultrasonic sensor needs the great echo of received intensity, can insert and adjust electric capacity, along with adjusting the increase of electric capacity quantity, adjust electric capacity and first electric capacity and can realize bigger total electric capacity to make echo signal's voltage reduce, the quantity of the regulation electric capacity that here needs to open can be confirmed according to actual need. Of course, when the ultrasonic sensor needs to receive echoes with small intensity, the adjusting capacitor is not turned on or only a small number of adjusting capacitors are turned on, specifically based on actual needs.

It should be noted that the adjustment signal line Vgc1 and the adjustment signal line Vgc2 \ 8230in fig. 9 "...\ the adjustment signal line Vgcn may be determined according to whether the 4+ n capacitor C4+ n electrically connected to the 8+ n transistor M8+ n correspondingly needs to be connected to the ultrasonic control circuit, that is, when the 4+ n capacitor C4+ n needs to be connected to the ultrasonic control circuit, the 8+ n transistor M8+ n may be controlled to be turned on; when the 4 < th > n capacitor C4+ n does not need to be connected to the ultrasonic control circuit, the 8 < th > n + transistor M8+ n can be controlled to be turned off.

In order to make the manufacturing process uniform and facilitate a driving method of a subsequent circuit to be simpler, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the 8+ N transistor are all N-type transistors. Of course, all the transistors may also be P-type transistors, and in the case that the transistors are P-type transistors, the design principle is similar to that of the present invention, and the present invention also belongs to the protection scope of the present invention.

The type of the transistor is not limited, and the transistor may be a thin film transistor, which may be a low temperature polysilicon thin film transistor or an oxide thin film transistor.

The embodiment of the application also provides an ultrasonic monitoring device which comprises at least one ultrasonic control circuit.

The specific number of the ultrasonic control circuits is not limited, and for example, the ultrasonic control circuit may include one; alternatively, the ultrasonic control circuit may include a plurality of circuits, which are not particularly limited herein. Fig. 10 is a diagram showing an example in which the number of the ultrasonic control circuits is two.

The following description will be given taking an example in which the ultrasonic monitoring device includes two electrically connected ultrasonic control circuits.

Referring to fig. 10, the column select lines 11 of the two ultrasonic control circuits are electrically connected so that when the fourth transistor M4 of one of the ultrasonic control circuits is turned on, the fourth transistor M4 of the other ultrasonic control circuit is turned off, and thus the electric signal of the ultrasonic control circuit in which the fourth transistor M4 is turned on is read.

The embodiment of the application provides an ultrasonic monitoring device, when the ultrasonic control circuit in this ultrasonic monitoring device is in the first state, because first reset sub-circuit is configured to reset first node under the control of the first reset signal of first reset signal line, so no matter whether ultrasonic sensor transmits echo signal, this echo signal can not influence the electric potential of third node, the third node can keep the first reset signal of first reset signal line, ultrasonic control circuit can obtain the first signal of telecommunication with background noise this moment. When the ultrasonic control circuit is in the second state, because the first reset sub-circuit does not work, if the ultrasonic sensor transmits an echo signal, the echo signal can affect the electric potential of the third node, and the electric potential of the third node changes, at the moment, the ultrasonic control circuit can obtain a second electric signal of a signal with background noise and an effective signal. Therefore, the effective signal of the ultrasonic control circuit is obtained by subtracting the first electric signal from the second electric signal, and further can be better analyzed according to the effective signal.

The embodiment of the application also provides a driving method for driving the ultrasonic control circuit.

The method comprises the following steps:

s1, writing a first reset signal into a first reset signal line in a first state stage.

And S2, in the second state stage, the first reset signal is not written into the first reset signal line.

The operation principle of the ultrasonic control circuit shown in fig. 9 provided in this embodiment will be described in detail below by taking the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the 8+ N transistor as N-type transistors as examples, and combining the timing diagrams of the signal lines shown in fig. 6. Note that in fig. 11 to 16, the transistor is off by an "x" mark.

In the period from t1 to t2 in fig. 6, a high level is input to the first control signal line Drst, the voltage signal line VDD, the Gate signal line Gate, the first and third control signal lines Vg6, the second and third control signal lines Vg7, and the second Reset signal line Reset2, and a low level is input to the first Reset signal line Reset1 and the second control signal line Vclose. At this time, referring to fig. 11, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all turned on, and the first transistor M1, the second transistor M2, the third transistor M3, the eighth transistor M8, the ninth transistor M9, and the 8+ n th transistor M8+ n are all turned off. Then, since the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all turned on before the next ultrasound signal acquisition is finished, the sixth transistor M6 and the seventh transistor M7 can be all reset, and the second capacitor Cp1 and the third capacitor Cp2 can be held at the potential of 0.

In the period from t2 to t3 in fig. 6, a high level is input to both the first control signal line Drst and the voltage signal line VDD, and a low level is input to both the first Reset signal line Reset1, the second Reset signal line Reset2, the second control signal line Vclose, the Gate signal line Gate, the first third control signal line Vg6, and the second third control signal line Vg 7. At this time, all transistors remain in the off state and do not operate.

The stages t2 to t3 may be omitted.

In the period from t3 to t4 in fig. 6, a high level is input to the first control signal line Drst, the voltage signal line VDD, the first Reset signal line Reset1, and the second control signal line Vclose, and a low level is input to the second Reset signal line Reset2, the Gate signal line Gate, the first third control signal line Vg6, and the second third control signal line Vg 7. At this time, when the ultrasonic control circuit is in the first state, referring to fig. 12, the first transistor M1 and the second transistor M2 are all turned on, and the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the third transistor M3, the eighth transistor M8, the ninth transistor M9, and the 8+ n transistor M8+ n are all turned off. Since the first and second transistors M1 and M2 are both turned on, the third node W (i.e., the control electrode of the third transistor M3) may be reset by the first control signal of the first control signal line Drst.

At the stage t4 to t5 in fig. 6, a high level is input to the first control signal line Drst, the voltage signal line VDD, the first Reset signal line Reset1, the second control signal line Vclose, the Gate signal line Gate, and the first third control signal line Vg6, and a low level is input to the second third control signal line Vg7, the first Reset signal line Reset1, the second Reset signal line Reset2, and the second control signal line Vclose. At this time, referring to fig. 13, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are all turned on, and the fifth transistor M5, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the 8+ n transistor M8+ n are all turned off. Since the third transistor M3 holds the control signal of the first control signal line Drst, it is turned on. Since both the fourth transistor M4 and the sixth transistor M6 are turned on, the echo-free electric signal V1 can be stored in the second capacitor Cp1, and the electric signal V1 at this time has a noise floor.

At the stage t5 to t6 in fig. 6, a high level is input to the first control signal line Drst, the voltage signal line VDD, the first Reset signal line Reset1, and the second control signal line Vclose, a low level is input to the second Reset signal line Reset2, the Gate signal line Gate, the first third control signal line Vg6, and the second third control signal line Vg7, and when the ultrasonic control circuit is in the second state, the ultrasonic sensor PVDF transmits ultrasonic waves. At this time, referring to fig. 14, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned on, and the fourth transistor M4, the sixth transistor M6, the fifth transistor M5, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the 8+ n transistor M8+ n are all turned off. This keeps the potential of the third node W before the echo starts to be acquired, where t6 is the arrival time of the echo peak.

At the stage t6 to t7 in fig. 6, a high level is input to the first control signal line Drst, the voltage signal line VDD, and the second control signal line Vclose, a low level is input to the Gate signal line Gate, the first third control signal line Vg6, the second third control signal line Vg7, the first Reset signal line Reset1, and the second Reset signal line Reset2, and at this time, the ultrasonic sensor PVDF transmits ultrasonic waves. At this time, referring to fig. 15, the second transistor M2 and the third transistor M3 are all turned on, and the first transistor M1, the fourth transistor M4, the sixth transistor M6, the fifth transistor M5, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the 8+ n transistor M8+ n are all turned off. Since the second transistor M2 and the third transistor M3 are both turned on and the first transistor M1 is turned off, the electric signal V2 of the echo can be collected to the third node W, and the echo peak value can be collected when the echo peak value arrives at time t 6.

It should be noted that the second transistor M2 may be turned off at time T7 after half cycle time has elapsed from T6, that is, T7-T6= T/2 (T is a cycle time) is maintained, so that the start time of T6 may be adjusted by a certain step to acquire the maximum signal amount, that is, the echo peak value. Of course, the second transistor M2 may not be turned off at time t7, and the echo peak may not be detected.

At the stage t7 to t8 in fig. 6, a high level is input to both the first control signal line Drst and the voltage signal line VDD, a low level is input to each of the Gate signal line Gate, the first third control signal line Vg6, the second third control signal line Vg7, the first Reset signal line Reset1, the second Reset signal line Reset2, and the second control signal line Vclose, and at this time, the ultrasonic sensor PVDF transmits ultrasonic waves. This is the interval between the acquisition of the echo signal and the readout of the echo signal, and all the transistors are kept in the off state, and are not operated, so that the acquired echo signal can be kept on the third node W (i.e., the control electrode of the third transistor M3).

The stages t7 to t8 may be omitted.

At the stage t8 to t9 in fig. 6, a high level is input to the first control signal line Drst, the voltage signal line VDD, the Gate signal line Gate, and the second and third control signal lines Vg7, and a low level is input to the first and third control signal lines Vg6, the first Reset signal line Reset1, the second Reset signal line Reset2, and the second control signal line Vclose. At this time, referring to fig. 16, the second transistor M2, the third transistor M3, the fourth transistor M4, and the seventh transistor M7 are all turned on, and the first transistor M1, the sixth transistor M6, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9, and the 8+ n transistor M8+ n are all turned off. Since the second transistor M2, the third transistor M3, the fourth transistor M4, and the seventh transistor M7 are all turned on, the echo signal V2 of the third node W may be stored into the third capacitor Cp 2.

At the stage t 9-stage in fig. 6, the first end Vi _ P of the instrumentation amplifier obtains the electrical signal V1 on the second capacitor Cp1, and the second end Vi _ N obtains the electrical signal V2 on the second capacitor Cp2, and after differential processing is performed in the instrumentation amplifier, amplification of the signal and removal of background noise of the ultrasonic control circuit are realized, so that the ultrasonic control circuit has strong anti-Interference and anti-EMI (Electromagnetic Interference) capabilities.

The differential signal in the instrumentation amplifier may then be analog-to-digital converted by the ADC72 as shown in fig. 9.

The electrical signal V1 at the second capacitor Cp1 and the electrical signal V2 at the second capacitor Cp2 may be amplified and then subjected to differential processing, which is not particularly limited herein.

Fig. 11 to 16 are all explained by taking the example that the transistors M8 to M8+ n are off. The adjustment of echo signals with different intensities can be realized by adjusting the on and off of the transistors M8-M8 + n. In particular, the required total capacitance value, and thus the number of transistors that are turned on, may be selected according to the actual situation. The wide-range adjustment of the capacitance value of the third node W (i.e., the control electrode of the third transistor M3) can also be realized by turning on the combination of transistors with different positions and different numbers, so as to realize the wide-range adjustment of the echo signal, thereby obtaining the APS type ultrasonic control circuit with a high dynamic range.

It should be noted that, when selecting the capacitor, it is necessary to ensure that the transistors M8 to M8+ n remain in the on state or the off state during one acquisition process of t1 to t 9.

The following takes the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor as N-type transistors as an example, and details the operation principle of the ultrasound control circuit shown in fig. 7 provided in this embodiment with reference to the timing diagram of each signal line shown in fig. 8.

In the period t1 to t2 in fig. 8, a high level is input to the voltage signal line VDD, the Gate signal line Gate, the first third control signal line Vg6, the second third control signal line Vg7, and the second Reset signal line Reset2, and a low level is input to the first Reset signal line Reset1 and the second control signal line Vclose. At this time, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all turned on, and the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off. Then, since the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all turned on before the next ultrasound signal acquisition after the previous ultrasound signal acquisition is finished, the sixth transistor M6 and the seventh transistor M7 can be all reset, and the potentials of the second capacitor Cp1 and the third capacitor Cp2 can be maintained to 0.

In the period from t2 to t3 in fig. 8, a high level is input to the voltage signal line VDD, and a low level is input to each of the first Reset signal line Reset1, the second Reset signal line Reset2, the second control signal line Vclose, the Gate signal line Gate, the first third control signal line Vg6, and the second third control signal line Vg 7. At this time, all transistors remain in the off state and do not operate.

The stages t2 to t3 may be omitted.

In the period from t3 to t4 in fig. 8, a high level is input to the voltage signal line VDD, the first Reset signal line Reset1, and the second control signal line Vclose, and a low level is input to the second Reset signal line Reset2, the Gate signal line Gate, the first third control signal line Vg6, and the second third control signal line Vg 7. At this time, under the condition that the ultrasonic control circuit is in the first state, the first transistor M1 and the second transistor M2 are both turned on, and the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the third transistor M3 are all turned off. Since the first transistor M1 and the second transistor M2 are both turned on, the third node W (i.e., the control electrode of the third transistor M3) may be reset by the voltage signal of the voltage signal line VDD.

In the period from t4 to t5 in fig. 8, a high level is input to the voltage signal line VDD, and a low level is input to each of the first Reset signal line Reset1, the second control signal line Vclose, the Gate signal line Gate, the first third control signal line Vg6, the second third control signal line Vg7, the first Reset signal line Reset1, the second Reset signal line Reset2, and the second control signal line Vclose. At this time, all transistors are turned off and do not operate.

The stages t4 to t5 may be omitted.

In the period t5 to t6 in fig. 8, a high level is input to the voltage signal line VDD, the first and third control signal lines Vg6, and the Gate signal line Gate, and a low level is input to the first Reset signal line Reset1, the second control signal line Vclose, the second Reset signal line Reset2, and the second and third control signal lines Vg 7. At this time, the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are all turned on, and the first transistor M1, the second transistor M2, the fifth transistor M5, and the seventh transistor M7 are all turned off. Since the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are all turned on, the echo-free electrical signal V1 may be stored in the second capacitor Cp1, where the electrical signal V1 has a noise floor.

At the stage t6 to t7 in fig. 8, a high level is input to the voltage signal line VDD, a low level is input to the second control signal line Vclose, the Gate signal line Gate, the first and third control signal lines Vg6, the second and third control signal lines Vg7, the first Reset signal line Reset1, and the second Reset signal line Reset2, and when the ultrasonic control circuit is in the second state, the ultrasonic sensor PVDF transmits ultrasonic waves. At this time, all transistors are turned off and do not operate.

The stages t6 to t7 may be omitted.

At the stage t7 to t8 in fig. 8, a high level is input to both the voltage signal line VDD and the second control signal line Vclose, a low level is input to both the Gate signal line Gate, the first and third control signal lines Vg6, the second and third control signal lines Vg7, the first Reset signal line Reset1, and the second Reset signal line Reset2, and at this time, the ultrasonic sensor PVDF transmits ultrasonic waves. At this time, the second transistor M2 and the third transistor M3 are all turned on, and the fourth transistor M4, the sixth transistor M6, the first transistor M1, the fifth transistor M5, and the seventh transistor M7 are all turned off. Since the second transistor M2 is turned on and the ultrasonic sensor PVDF transmits ultrasonic waves, an electric signal V2 of an echo can be collected to the third node W, and an echo peak value can be collected when the echo peak value arrives at time t 7.

It should be noted that the second transistor M2 may be turned off at time T8 after half of the cycle time has elapsed from T7, that is, T8-T7= T/2 (T is a cycle time) is maintained, so that the start time of T7 may be adjusted by a certain step to acquire the maximum signal amount, that is, the echo peak value. Of course, the second transistor M2 may not be turned off at time t8, and the echo peak may not be detected.

At the stage t8 to t9 in fig. 8, a high level is input to the voltage signal line VDD, a low level is input to each of the Gate signal line Gate, the second and third control signal lines Vg7, the first and third control signal lines Vg6, the first Reset signal line Reset1, the second Reset signal line Reset2, and the second control signal line Vclose, and at this time, the ultrasonic sensor PVDF transmits ultrasonic waves. This is the interval between the acquisition of the echo signal and the readout of the echo signal, and all the transistors are kept in the off state, and are not operated, so that the acquired echo signal can be kept on the third node W (i.e., the control electrode of the third transistor M3).

The stages t8 to t9 may be omitted.

In the period from t9 to t10 in fig. 8, a high level is input to the second third control signal line Vg7, the Gate signal line Gate, and the voltage signal line VDD, and a low level is input to the first third control signal line Vg6, the first Reset signal line Reset1, the second Reset signal line Reset2, and the second control signal line Vclose. At this time, the third transistor M3, the fourth transistor M4, and the seventh transistor M7 are all turned on, and the second transistor M2, the sixth transistor M6, the first transistor M1, and the fifth transistor M5 are all turned off. Since the third transistor M3, the fourth transistor M4, and the seventh transistor M7 are all turned on, the echo signal V2 of the third node W may be stored into the third capacitor Cp 2.

At the stage t 10-stage in fig. 8, the first end Vi _ P of the instrumentation amplifier obtains the electrical signal V1 on the second capacitor Cp1, and the second end Vi _ N obtains the electrical signal V2 on the second capacitor Cp2, and after differential processing is performed in the instrumentation amplifier, amplification of the signals and removal of background noise of the ultrasonic control circuit are realized, so that the ultrasonic control circuit has strong anti-interference and anti-EMI capabilities.

The differential signal in the instrumentation amplifier may then be analog-to-digital converted by the ADC72 as shown in fig. 7.

The electrical signal V1 on the second capacitor Cp1 and the electrical signal V2 on the second capacitor Cp2 may be amplified and then subjected to differential processing, which is not particularly limited herein.

It should be noted that the other processes in fig. 7 are similar to the processes in fig. 9, and are not described again here. A regulator sub-circuit may also be added in fig. 7 with reference to fig. 9, and will not be described here again.

In the timing sequence of fig. 8, after the first transistor M1 and the second transistor M2 clear the column select line and clear and reset the second capacitor Cp1 and the third capacitor Cp2, they are only turned on for a period of time, so that the potential of the control electrode of the third transistor M3 and the potential of the ultrasonic sensor PVDF when there is no echo can be reset to the voltage signal of the voltage signal line VDD, and at this time, the voltage difference signal of the echo collected from the peak value to the valley value can still ensure that the third transistor M3 works in the saturation region.

The acquisition of the echo signal can be realized by controlling the on and off time t7-t 8 of the second transistor M2, and the same process of finding the optimal acquisition time in fig. 6 is also required.

The embodiment of the application provides a driving method, and by the driving method, when the ultrasonic control circuit is in the first state, because the first reset sub-circuit is configured to reset the first node under the control of the first reset signal line, no matter whether the ultrasonic sensor transmits an echo signal, the echo signal does not affect the potential of the third node, the third node can keep the first reset signal of the first reset signal line, and at this time, the ultrasonic control circuit can obtain the first electric signal with background noise. When the ultrasonic control circuit is in the second state, because the first reset sub-circuit does not work, if the ultrasonic sensor transmits an echo signal, the echo signal can affect the electric potential of the third node, the electric potential of the third node changes, and at the moment, the ultrasonic control circuit can obtain a signal with background noise and a second electric signal of an effective signal. Therefore, the effective signal of the ultrasonic control circuit is obtained by subtracting the first electric signal from the second electric signal, and further can be better analyzed according to the effective signal.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present application.

Claims

1. An ultrasound control circuit, comprising:

a first reset sub-circuit electrically connected to a first reset signal line, a first control signal line, and the first node, configured to reset the first node under control of a first reset signal of the first reset signal line in a first state, and configured to be inactive in a second state;

2. The ultrasound control circuit of claim 1, further comprising a regulation subcircuit electrically connected to the third node, a regulation signal line, and the ground, configured to control an electrical signal of the third node under control of a regulation signal of the regulation signal line.

3. The ultrasound control circuit of claim 1, wherein the first reset sub-circuit comprises a first transistor;

4. The ultrasound control circuit of claim 1, wherein the first reset sub-circuit comprises a first transistor;

5. The ultrasound control circuit of claim 1, wherein the second reset sub-circuit comprises a fifth transistor;

6. The ultrasound control circuit of claim 1, wherein the signal transmission subcircuit comprises a second transistor;

the control pole of the second transistor is electrically connected with the second control signal line, the first pole is electrically connected with the first node, and the second pole is electrically connected with the third node.

7. The ultrasound control circuit of claim 1, wherein the output sub-circuit comprises a third transistor, a fourth transistor, and a first capacitor;

the first end of the first capacitor is electrically connected with the third node, and the second end of the first capacitor is electrically connected with the grounding terminal.

8. The ultrasound control circuit of claim 1, wherein the memory sub-circuit comprises at least a sixth transistor and a second capacitor;

9. The ultrasound control circuit of claim 8, wherein the memory sub-circuit comprises the sixth transistor, the second capacitor, a seventh transistor, and a third capacitor;

10. The ultrasound control circuit of claim 1, wherein the processing sub-circuit comprises at least an amplifier;

11. The ultrasound control circuit of claim 2, wherein the conditioning sub-circuit comprises at least one switching transistor and a conditioning capacitor;

12. An ultrasound monitoring device comprising at least one ultrasound control circuit according to any of claims 1-11.

13. A driving method for driving the ultrasonic control circuit according to any one of claims 1 to 11;

the method comprises the following steps:

writing a first reset signal to the first reset signal line in a first state;