CN115966511A

CN115966511A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN115966511A
Application number: CN202211550267.9A
Authority: CN
Inventors: 赵常宝; 胡胜; 叶国梁
Original assignee: Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Current assignee: Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Priority date: 2022-12-05
Filing date: 2022-12-05
Publication date: 2023-04-14

Abstract

The embodiment of the application provides A semiconductor device and a method of manufacturing the same. The manufacturing method of the semiconductor device comprises the steps that M substrates are bonded in sequence, wherein the Nth substrate is bonded to the (N-1) th substrate, and an Nth device is formed on one side, away from the (N-1) th substrate, of the Nth substrate; forming N-1 groups of first openings on one side, away from the N-1 substrate, of the Nth substrate on the periphery of the Nth device, wherein the N-1 groups of first openings penetrate through the Nth substrate so as to expose the N-1 th device and the N-2 groups of first openings on the N-1 th substrate respectively; and filling a conductive material in the N-1 group of first openings on the Nth substrate to form conductive plugs, so that the conductive plugs can electrically lead out the devices respectively arranged on the M substrates, thereby facilitating the subsequent use of more circuit structures and improving the area utilization rate of the semiconductor devices.

Description

Semiconductor device with a plurality of transistors and method for producing the same

Technical Field

Background

With the continuous development of semiconductor technology, the semiconductor device is provided with a plurality of semiconductor chips, semiconductor devices are widely used in more and more fields. The planar plate capacitor structure provided in the semiconductor device has not been able to satisfy the power supply requirements of the lines.

At present, the number of the current day, the capacitance density is improved by providing deep trench capacitance structures in the semiconductor device. Although the capacitance density of the deep trench capacitor structure is dozens of times of that of the planar flat capacitor structure, the deep trench capacitor structure is limited by the aspect ratio of the trench, so that the capacitance density in a unit area can only be increased in a limited way.

Disclosure of Invention

The semiconductor device and the manufacturing method thereof provided by the embodiment of the application aim to solve the problem that the existing deep trench capacitor is low in capacitor density in unit area.

<xnotran> , : </xnotran> Provided is a method for manufacturing a semiconductor device, including:

sequentially bonding the M substrates, wherein the step of bonding the Nth substrate to the (N-1) th substrate comprises,

bonding the Nth substrate to the (N-1) th substrate, and forming an Nth device on one side of the Nth substrate far away from the (N-1) th substrate;

forming N-1 groups of first openings on the Nth substrate, wherein the N-1 groups of first openings are positioned on the periphery of the Nth device, and the N-1 groups of first openings are formed on one side of the Nth substrate, which is far away from the N-1 group of first openings, and penetrate through the Nth substrate so as to expose the N-1 group of first openings and the N-2 groups of first openings formed on the N-1 group of first openings respectively;

filling a conductive material into the N-1 group of first openings on the Nth substrate to form conductive plugs;

wherein N is more than or equal to 2 and less than or equal to M, and N and M are integers.

When N = M, a second opening is formed in the Mth substrate, and the second opening is formed in the Mth substrate on the side far away from the M-1 th substrate to expose the Mth device.

When N = M, after filling the conductive material in the N-1 group of first openings and the second openings on the nth substrate, forming a redistribution layer on one side of the mth substrate away from the M-1 group of substrate, where the redistribution layer electrically leads out the conductive plugs in the M-1 group of first openings and the second openings of the mth substrate.

Wherein the N device at least partially overlaps with an orthographic projection of the N-1 device on the Nth substrate surface.

Wherein the device is a deep trench capacitor.

Wherein, the forming method of the Nth deep trench capacitor comprises,

the Nth substrate is provided with a first surface and a second surface which are opposite;

forming an Nth groove extending from the first surface to the second surface on the first surface of the Nth substrate, and forming an Nth deep groove capacitor in the Nth groove, wherein the Nth deep groove capacitor comprises a first conducting layer and a second conducting layer which sequentially cover the surface of the Nth groove and the first surface of the Nth substrate at the periphery of the Nth groove along with the shape, and a dielectric layer which is positioned between the first conducting layer and the second conducting layer and insulates the first conducting layer and the second conducting layer; the first conducting layer and the second conducting layer are respectively used as an upper polar plate and a lower polar plate of the deep trench capacitor.

Wherein the second surface of the nth substrate is bonded to the first surface of the (N-1) th substrate.

Wherein after the Nth substrate is bonded to the (N-1) th substrate and before the Nth device is formed,

and thinning the side of the Nth substrate far away from the N-1 th substrate.

In order to solve the above technical problem, another technical solution adopted by the present application is: provided is a semiconductor device including:

m substrates bonded in sequence, wherein,

an Nth device is formed on one side, away from the (N-1) th substrate, of the Nth substrate;

the side, away from the (N-1) th substrate, of the Nth substrate on the periphery of the Nth device is provided with N-1 groups of first openings, and the N-1 groups of first openings penetrate through the Nth substrate to expose the (N-1) th device and N-2 groups of first openings on the (N-1) th substrate respectively;

the N-1 group of first openings on the Nth substrate are filled with conductive plugs;

When N = M, a second opening is opened on one side of the Mth substrate away from the M-1 th substrate, and the Mth device is exposed by the second opening.

Wherein, the second opening is filled with a conductive plug;

and a rewiring layer is formed on one side of the Mth substrate far away from the Mth-1 substrate, and the rewiring layer leads out the conductive plugs in the first opening and the second opening of the Mth substrate M-1 group electrically.

The beneficial effect of this application is: different from the prior art, the semiconductor device and the manufacturing method thereof provided by the embodiment of the application have the advantages that the manufacturing method of the semiconductor device sequentially bonds M substrates, wherein the Nth substrate is bonded to the (N-1) th substrate, and the Nth device is formed on one side of the Nth substrate away from the (N-1) th substrate; forming N-1 groups of first openings on one side, away from the N-1 substrate, of the Nth substrate on the periphery of the Nth device, wherein the N-1 groups of first openings penetrate through the Nth substrate so as to expose the N-1 th device and the N-2 groups of first openings on the N-1 th substrate respectively; and filling a conductive material in the N-1 group of first openings on the Nth substrate to form conductive plugs, so that the conductive plugs can electrically lead out the devices respectively arranged on the M substrates, thereby facilitating the subsequent use of more circuit structures and improving the area utilization rate of the semiconductor devices.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:

fig. 1 is a flow chart of a method of manufacturing a semiconductor device provided herein;

FIG. 2 is a flow chart of a method of fabricating a semiconductor device according to an embodiment of the present application;

fig. 3 (a) -3 (j) are schematic structural diagrams corresponding to steps in the method for manufacturing the semiconductor device provided in fig. 2 of the present application;

FIG. 4 is a flow chart of a method of fabricating a semiconductor device according to another embodiment of the present application;

FIGS. 5 (a) -5 (h) are schematic structural diagrams corresponding to the steps in the method for manufacturing the semiconductor device provided in FIG. 4 of the present application;

fig. 6 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application.

In the figure: a semiconductor device 100;

a first substrate 11; a first surface 111; a second surface 112; a first trench 12; a first deep trench capacitor 13; a first conductive layer 131; a second conductive layer 132; a dielectric layer 133; a first protective layer 14;

a second substrate 21; a first surface 211; a second surface 212; a second trench 22; a second deep trench capacitor 23; a first conductive layer 231; a second conductive layer 232; a dielectric layer 233; a second protective layer 24;

a third substrate 31; a first surface 311; a second surface 312; a third groove 32; a third deep trench capacitor 33; a first conductive layer 331; a second conductive layer 332; a dielectric layer 333; a third protective layer 34;

a first opening 25; a second opening 26; a first conductive plug 27; a second conductive plug 28;

two sets of first openings 35; a first set of first openings 351; a second set of first apertures 352; a second opening 36; a first conductive plug 37; a first set of conductive plugs 371; a second set of conductive plugs 372; a second conductive plug 38;

and a rewiring layer 6.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first", "second" and "third" in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any indication of the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise. In the embodiment of the present application, all directional indicators (such as up, down, left, right, front, rear \8230;) are used only to explain the relative positional relationship between the components, the motion situation, etc. at a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. <xnotran> , . </xnotran> It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The present application will be described in detail with reference to the drawings, wherein the cross-sectional views illustrating the structure of the device are not enlarged partially in general scale for convenience of illustration, and the drawings are only exemplary and should not be construed as limiting the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

Referring to fig. 1, fig. 1 is a flow chart illustrating a method for manufacturing a semiconductor device according to the present application. The method for manufacturing the semiconductor device specifically comprises the following steps.

s1: and bonding the Nth substrate to the (N-1) th substrate, and forming an Nth device on one side of the Nth substrate far away from the (N-1) th substrate.

S2: and forming N-1 groups of first openings on the Nth substrate, wherein the N-1 groups of first openings are positioned on the periphery of the Nth device, are formed on one side of the Nth substrate, which is far away from the N-1 th substrate, and penetrate through the Nth substrate so as to expose the N-1 th device and the N-2 groups of first openings formed on the N-1 th substrate respectively.

S3: and filling the conductive material in the N-1 group of first openings on the Nth substrate to form conductive plugs.

The semiconductor device manufacturing method can realize stacking of devices formed on the M substrates respectively by sequentially bonding the M substrates so as to increase the density of the semiconductor device in a unit area.

In one embodiment, the signals are transmitted at M =2, that is, the manufacturing method of the semiconductor device will be described in detail by taking the example of bonding 2 substrates in turn, and the value of N is 2. <xnotran> , , 1 , 2 , 1 , 2 , , N N . </xnotran>

When the ratio of N =2, bonding the N =2 th substrate to the N-1=1 th substrate specifically includes the following steps.

Referring to fig. 2 and fig. 3 (a) -3 (j), fig. 2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application; fig. 3 (a) -3 (j) are schematic structural diagrams corresponding to the steps in the method for manufacturing the semiconductor device provided in fig. 2 of the present application.

Step S11, bonding the N =2 th substrate to the N-1=1 th substrate, and forming the N =2 th device on the side of the N =2 th substrate away from the N-1=1 th substrate.

The substrate in some embodiments of the present application is any substrate known in the art, and the substrate material may include, but is not limited to, semiconductors, glass, ceramics, and the like. Preferably, the substrate may be a wafer or a chip, and is not limited in particular.

In some embodiments of the present application, the device may be a deep trench capacitor, and certainly, in other embodiments, the device may also be other active/passive devices such as a conductive plug and a transistor, and a wiring layer for electrically leading out the active/passive devices, which is not limited specifically.

In the following embodiments of the present application, a Deep Trench Capacitor (DTC) is taken as an example for explanation.

The method for forming the Nth deep trench capacitor comprises the steps that the Nth substrate is provided with a first surface and a second surface which are opposite; forming an Nth groove extending from the first surface to the second surface on the first surface of the Nth substrate, and forming an Nth deep groove capacitor in the Nth groove, wherein the Nth deep groove capacitor comprises a first conducting layer and a second conducting layer which sequentially cover the surface of the Nth groove and the first surface of the Nth substrate at the periphery of the Nth groove along with the shape, and a dielectric layer which is positioned between the first conducting layer and the second conducting layer and insulates the first conducting layer and the second conducting layer; the first conducting layer and the second conducting layer are respectively used as an upper polar plate and a lower polar plate of the deep trench capacitor. Wherein the Nth deep trench capacitor can be at least one; at least one nth trench may be formed in the first surface of the nth substrate.

Referring to fig. 3 (a) and 3 (b), a method of forming a first deep trench capacitor 13 on a first surface 111 of a first substrate 11 is disclosed in an embodiment of the present application. The first substrate 11 has a first surface 111 and a second surface 112 opposite to each other; forming a first trench 12 in the first surface 111 of the first substrate 11 from the first surface 111 to the second surface 113 by a method known in the art; the first conductive layer 131 and the second conductive layer 132 and the dielectric layer 133 which is located between the first conductive layer 131 and the second conductive layer 132 and insulates the first conductive layer 131 and the second conductive layer 132 are sequentially formed on the surface of the first trench 12 and the first surface 111 of the first substrate 11 at the periphery of the first trench 12, so as to form the first deep trench capacitor 13 in the first trench 12. Wherein, the number of the first deep trench capacitor 13 can be at least one; at least one first trench 12 may be formed in the first surface 111 of the first substrate 11. The first conductive layer 131 and the second conductive layer 132 are respectively used as an upper plate and a lower plate of the first deep trench capacitor 13, and the first conductive layer 131 and the second conductive layer 132 extend to the first surface 111 of the first substrate 11 at the periphery of the first trench 12. Specifically, the first conductive layer 131 and the second conductive layer 132 on the first surface 111 may be selectively exposed by the subsequently disposed opening portion, so as to facilitate subsequent electrical leading-out of the upper plate and the lower plate. The number of layers of the first conductive layer 131, the second conductive layer 132, and the dielectric layer 133 may be set as needed. In this embodiment, the material of the dielectric layer 133 may include, but is not limited to, one or more combinations of polyimide, tetraethyl orthosilicate, silicon oxide, silicon nitride, silicon oxynitride, undoped silicon glass, benzocyclobutene (BCB), and Polybenzoxazole (PBO). The material of the first conductive layer 131 and/or the second conductive layer 132 may include, but is not limited to, one or more of copper, silver, aluminum, doped silicon, titanium nitride, and the like. Optionally, referring to fig. 3 (c), a first protection layer 14 is covered on a side of the first deep trench capacitor 13 away from the first substrate 11 to protect the first deep trench capacitor 13. The material of the first protection layer 14 may be the same as or different from the material of the dielectric layer 133. It is understood that the nth deep trench capacitor formed on the nth substrate in the present embodiment may be the same as or different from the first deep trench capacitor 13 formed on the first substrate 11, and the forming method of the nth deep trench capacitor includes, but is not limited to, the above forming method, and the nth deep trench capacitor in the present application may also be in other forms.

In the following embodiments of the present application, the second surface of the nth substrate is bonded to the first surface of the N-1 st substrate, but in other alternative embodiments, the first surface of the nth substrate may be bonded to the first surface of the N-1 st substrate, the device is formed on the first surface and/or the second surface of the Nth substrate, namely the deep trench capacitor is formed on the first surface and/or the second surface of the Nth substrate. Further, after the Nth substrate is bonded to the (N-1) th substrate and before an Nth device is formed, thinning the side, away from the (N-1) th substrate, of the Nth substrate.

Referring to fig. 3 (d) and 3 (e), bonding the second surface 212 of the second substrate 21 to the first surface 111 of the first substrate 11, and bonding the second substrate 21 to the first substrate 11 may include, but is not limited to, hybrid bonding, fusion bonding, bump bonding, and the like. After the second substrate 21 is bonded to the first substrate 11, before the second deep trench capacitor 23 is formed, further comprising, and thinning the side of the second substrate 21 away from the first substrate 11, and forming a second deep trench capacitor 23 on the side of the thinned second substrate 21 away from the first substrate 11. A second trench 22 can be formed on the first surface 211 of the second substrate 21 according to the manner of forming the first deep trench capacitor 13, and a second deep trench capacitor 23 can be formed. The second deep trench capacitor 23 includes a first conductive layer 231, a second conductive layer 232, and a dielectric layer 233 disposed between the first conductive layer 231 and the second conductive layer 232 for insulating the first conductive layer 231 from the second conductive layer 232.

In an alternative embodiment, a second protection layer 24 can be covered on a side of the second deep trench capacitor 23 away from the second substrate 21 to protect the second deep trench capacitor 23. The material of the second passivation layer 24 may be the same as or different from the material of the dielectric layer 233.

Optionally, the nth device at least partially overlaps with an orthographic projection of the nth-1 device on the first surface of the nth substrate. With continued reference to fig. 3 (e), the second deep trench capacitor 23 at least partially overlaps the orthographic projection of the first deep trench capacitor 13 on the first surface 211 of the second substrate 21.

Step S12, forming N-1=1 group of first openings in the nth =2 substrate, forming N-1=1 group of first openings in the N =2 device periphery from the N =2 substrate on a side away from the N-1=1 substrate and penetrating through the N =2 substrate to expose the N-2=0 group of first openings formed in the N-1=1 device and the N-1=1 substrate, respectively.

Optionally, an orthographic projection of the N-1 group of first openings formed in the nth substrate on the first surface of the first substrate is located in an orthographic projection of the first device on the first surface of the first substrate and is not overlapped with an orthographic projection of the nth device on the first surface of the first substrate.

Optionally, a kth group of first openings of the N-1 groups of first openings formed in the nth substrate are used for electrically leading out the kth device through the conductive plug. The first sub-opening in the kth group of first openings is used for leading out the kth device selectively and electrically through the conductive plug, wherein k is more than or equal to 1 and less than or equal to N-1, and k is an integer. For convenience of description, in the following embodiments of the present application, when k =1, the 1 st group of first openings is expressed as a first group of first openings, the 1 st device is expressed as a first device, it should be understood that the arabic numerals k in the kth group of first openings, the kth device, are instead expressed in corresponding lower case chinese numerals.

Referring to fig. 3 (f), a set of first openings 25 is formed in the second substrate 21, and the set of first openings 25 is formed in the periphery of the second deep trench capacitor 23 from the side of the second substrate 21 away from the first substrate 11 and penetrates through the second substrate 21 to expose the first conductive layer 131 and/or the second conductive layer 132 of the first deep trench capacitor 13. The group of first openings 25 formed in the second substrate 21 avoids the second deep trench capacitor 23, an orthographic projection of the group of first openings 25 formed in the second substrate 21 on the first surface 111 of the first substrate 11 is located in an orthographic projection of the first deep trench capacitor 13 on the first surface 111 of the first substrate 11, and is not overlapped with the orthographic projection of the second deep trench capacitor 23 on the first surface 111 of the first substrate 11, so that the group of first openings 25 is electrically led out of the first conductive layer 131 and/or the second conductive layer 132 in the first deep trench capacitor 13 of the first substrate 11 through a conductive plug. Since k is equal to or greater than 1 and equal to or less than N-1=1, k is an integer, the value of k is 1, when k =1, the set of first openings 25 formed in the second substrate 21 only includes the first set of first openings, and the set of first openings 25 formed in the second substrate 21 is used for electrically leading out the first conductive layer 131 and/or the second conductive layer 132 in the first deep trench capacitor 13 through the conductive plug. The first opening 25 includes at least one first sub-opening 251 (not shown), and the first sub-opening 251 is used for selectively and electrically leading out the first conductive layer 131 and the second conductive layer 132 in each layer of the first deep trench capacitor 13 through a conductive plug. The number of the first sub-openings 251 in the first opening 25 depends on the number of the first conductive layer 131 and the second conductive layer 132 in each layer of the first deep trench capacitor 13 that need to be electrically led out. For example, the first deep trench capacitor 13 has three first conductive layers 131 and three second conductive layers 132, the first deep trench capacitor 13 needs to be electrically led out the first conductive layer 131 as two layers, and the second conductive layer 132 as one layer, so that the number of the first sub-openings 251 in the first opening 25 is three.

In step S13, a conductive material is filled in N-1=1 group of first openings on the nth =2 substrate to form a conductive plug.

A first conductive plug 27 is formed by filling a conductive material in the first opening 25 on the second substrate 21.

Further, when N = M, a second opening is opened in the mth substrate, and the second opening is opened from a side of the mth substrate away from the M-1 th substrate to expose the mth device. Before filling the conductive material in the N-1 groups of first openings on the Nth substrate, opening second openings on the Mth substrate before, after, between and/or simultaneously with the M-1 groups of first openings on the Mth substrate; after the N-1 groups of first openings on the Nth substrate are filled with the conductive material, second openings can be formed on the Mth substrate.

Optionally, an orthogonal projection of the second opening formed in the mth substrate on the first surface of the mth substrate is located in an orthogonal projection of the mth deep trench capacitor on the first surface of the mth substrate.

Optionally, a second opening formed in the mth substrate is used for electrically leading out the mth device through the conductive plug, where the second opening includes at least one second sub-opening, and the second sub-opening of the second opening is used for selectively electrically leading out the conductive layer in the mth device through the conductive plug.

Step S131, referring to fig. 3 (g), when N = M =2, before the group of first openings 25 on the second substrate 21 is filled with the conductive material, before the group of first openings 25 on the second substrate 21 is opened, a second opening 26 is opened on the second substrate 21 before the group of first openings 25 is opened, and the second opening 26 is opened from a side of the second substrate 21 away from the first substrate 11 to expose the first conductive layer 231 and/or the second conductive layer 232 in the second deep trench capacitor 23. In another embodiment, referring to fig. 3 (h), before the group of first openings 25 on the second substrate 21 is filled with the conductive material, after the group of first openings 25 is opened on the second substrate 21, a second opening 26 is opened on the second substrate, and the second opening 26 is opened from a side of the second substrate 21 away from the first substrate 11 to expose the first conductive layer 231 and/or the second conductive layer 232 in the second deep trench capacitor 23.

The second opening 26 formed in the second substrate 21 is formed on the first surface 211 of the second substrate 21 the projection is located within the orthographic projection of the second deep trench capacitor 23 on the first surface 211 of the second substrate 21, for electrically leading out the first conductive layer 231 and/or the second conductive layer 232 in the second deep trench capacitor 23 of the second substrate 21 through the conductive plug. The second opening 26 includes at least one second sub-opening 261 (not shown), and the second sub-opening 261 is used for selectively and electrically leading out the first conductive layer 231 and the second conductive layer 232 of each layer of the second deep trench capacitor 23 through the conductive plug. The number of the second sub-openings 261 depends on the number of the first conductive layers 231 and the second conductive layers 232 in the second deep trench capacitor 23 that need to be electrically led out. For example, the second deep trench capacitor 23 has three first conductive layers 231 and three second conductive layers 232, the first conductive layer 231 and the second conductive layer 232 need to be electrically led out as two layers, and the number of the second sub-openings 261 in the second opening 26 formed in the second substrate 21 is three.

Referring to fig. 3 (i), a first conductive plug 27 may be formed by filling a conductive material in a group of first openings 25 on the second substrate 21, and a second conductive plug 28 may be formed by filling a conductive material in a group of second openings 26 on the second substrate 21. In other embodiments, the first conductive plug 27 may be formed by filling a conductive material in the first opening 25 and the second conductive plug 28 may be formed by filling a conductive material in the second opening 26.

Further, when N = M, after the conductive material is filled in the N-1 sets of first openings and the second openings on the nth substrate, a redistribution layer is formed on a side of the mth substrate away from the M-1 set of substrate, and the redistribution layer electrically leads out the conductive plugs in the M-1 sets of first openings and the second openings of the mth substrate.

<xnotran> S132, 3 (j), 21 25 26 , 21 11 (Redietribution Layer, RDL) 6, 6 21 25 27 26 28 . </xnotran>

<xnotran> , M =3 , 3 , , N 2 3. </xnotran> For convenience of description, in the following embodiments of the present application, the 3 rd substrate is expressed as a third substrate, and the 3 rd device is expressed as a third device, it should be understood that the arabic numerals N in the nth substrate are replaced with corresponding lower case chinese numerals.

When N =2, the step of bonding the N =2 th substrate to the N-1=1 st substrate may be referred to the above description, and is not described herein again.

When N =3, bonding the N =3 th substrate to the N-1=2 th substrate specifically includes the following steps.

Referring to fig. 4 and fig. 5 (a) -5 (h), fig. 4 is a flow chart of a method for manufacturing a semiconductor device according to another embodiment of the present application; fig. 5 (a) -5 (h) are schematic structural diagrams corresponding to the steps in the method for manufacturing the semiconductor device provided in fig. 4 of the present application.

Step S21, bonding the N =3 th substrate to the N-1=2 th substrate, and forming the N =3 devices on the side of the N =3 th substrate away from the N-1=2 th substrate.

Referring to fig. 5 (a) -5 (b), before the third substrate 31 is bonded to the second substrate 21, the first conductive plugs 27 are formed in the first openings 25 of the second substrate 21, after the third substrate 31 is bonded to the second substrate 21, a side of the third substrate 31 away from the second substrate 21 is thinned, and a third deep trench capacitor 33 is formed on a side of the thinned third substrate 31 away from the second substrate 21. A third trench 32 can be opened on the first surface 311 of the third substrate 31 according to the manner of manufacturing the first deep trench capacitor 13, and a third deep trench capacitor 33 can be manufactured. The third deep trench capacitor 33 includes a first conductive layer 331, a second conductive layer 332, and a dielectric layer 333 disposed between the first conductive layer 331 and the second conductive layer 332 for insulating the first conductive layer 331 and the second conductive layer 332.

In an alternative embodiment, a third protection layer 34 may be covered on a side of the third deep trench capacitor 33 away from the third substrate 31 to protect the third deep trench capacitor 33. The material of the third protective layer 34 may be the same as or different from the material of the dielectric layer 333.

Optionally, the nth device at least partially overlaps with an orthographic projection of the nth-1 device on the first surface of the nth substrate. With continued reference to fig. 5 (b), the third deep trench capacitor 33 at least partially overlaps the orthographic projection of the second deep trench capacitor 23 on the first surface 311 of the third substrate 31.

Step S22, forming N-1=2 groups of first openings in the nth =3 substrate, wherein the N-1=2 groups of first openings are formed in the N =3 device periphery and penetrate through the N =3 substrate from the side of the N =3 substrate away from the N-1=2 substrate to expose the N-1=2 devices and the N-2=1 groups of first openings formed in the N-1=2 substrate, respectively.

Optionally, an orthographic projection of the nth-1 group of first openings formed in the nth substrate on the first surface of the first substrate is located in an orthographic projection of the first device on the first surface of the first substrate and is not overlapped with an orthographic projection of the nth device on the first surface of the first substrate.

Optionally, a kth group of first openings of the N-1 groups of first openings formed on the nth substrate are used for electrically leading out the kth device through the conductive plug, wherein the kth group of first openings includes at least one first sub-opening, and the first sub-opening of the kth group of first openingsUsed for selectively and electrically leading out the kth device, wherein k is more than or equal to 1 and is less than or equal to N-1 _， k is an integer. For convenience of description, in the following embodiments of the present application, when k =2, the 2 nd group of first openings is expressed as the second group of first openings, and the 2 nd device is expressed as the second device, it should be understood that the arabic numerals k in the k-th group of first openings and the k-th device are replaced by corresponding lower case Chinese numerals.

Referring to fig. 5 (c), two sets of first openings 35 are opened in the third substrate 31, wherein the two sets of first openings 35 include a first set of first openings 351 and a second set of first openings 352, the first set of first openings 351 and the second set of first openings 352 are opened at the periphery of the third deep trench capacitor 33 from the side of the third substrate 31 away from the second substrate 21 and penetrate through the third substrate 31 to expose the set of first openings 25 on the second substrate 21 and the first conductive layer 231 and/or the second conductive layer 232 of the second deep trench capacitor 23, respectively, that is, the second set of first openings 352 expose the first conductive layer 231 and/or the second conductive layer 232 of the second deep trench capacitor 23, and the first set of first openings 351 expose the set of first openings 25 on the second substrate 21. The first group of first openings 351 and the second group of first openings 352 formed in the third substrate 31 avoid the third deep trench capacitor 33, that is, orthographic projections of the first group of first openings 351 and the second group of first openings 352 formed in the third substrate 31 on the first surface 111 of the first substrate 11 are located in the orthographic projection of the first deep trench capacitor 13 on the first surface 111 of the first substrate 11, and do not overlap with the orthographic projection of the third deep trench capacitor 33 on the first surface 111 of the first substrate 11. Since k is not less than 1 and not more than N-1=2, and k is an integer, the value of k is 1 and 2, and when k =2, the second group of first openings 352 is used to electrically lead out the first conductive layer 231 and/or the second conductive layer 232 of the second deep trench capacitor 23 through the conductive plug; when k =1, the first group of first openings 351 is used to electrically lead out the first conductive layer 131 and the second conductive layer 132 of the first deep trench capacitor 13 through the conductive plugs and the conductive plugs in the group of first openings 25 on the second substrate 21, and as the number of layers of the substrate increases, the problem that the devices of the lowermost substrate cannot be electrically led out due to the difficulty of high-depth-width etching and the difficulty of filling can be avoided. The first group of first openings 351 and the second group of first openings 352 each include at least one first sub-opening, the first sub-opening in the first group of first openings 351 is used for selectively and electrically leading out the first conductive layer 131 and the second conductive layer 132 in each layer of the first deep trench capacitor 13 through a conductive plug, and the first sub-opening in the second group of first openings 352 is used for selectively and electrically leading out the first conductive layer 231 and the second conductive layer 232 in each layer of the second deep trench capacitor 23 through a conductive plug. The number of the first sub-openings in the first group 351 of the first openings and the number of the first sub-openings in the second group 352 of the first openings are respectively selected

Depending on the number of layers of the first conductive layer and the second conductive layer of the first deep trench capacitor 13 and the second deep trench capacitor 12 that are desired to be electrically extracted. For example, the first deep trench capacitor 13 has three first conductive layers 131 and three second conductive layers 132, respectively, the second deep trench capacitor 23 has four first conductive layers 231 and four second conductive layers 232, respectively, the first deep trench capacitor 13 is expected to electrically lead the first conductive layer 131 as one layer, the second conductive layer 132 as one layer, and the second deep trench capacitor 13 is expected to electrically lead the first conductive layer 131 as one layer

The deep trench capacitor 23 is desired to be electrically led out the first conductive layer 231 into four layers and the second conductive layer 232 into three layers, so that the number of the first sub-openings in the first group of the first openings 351 is three and the number of the first sub-openings in the second group of the first openings 352 is seven.

In a step S23, the process is carried out, and filling a conductive material in the N-1=2 groups of first openings on the N =3 substrates to form conductive plugs.

Referring to fig. 5 (d), the two sets of first openings 35 (the first set of first openings 351, the second set of first openings 352) on the third substrate 31 are filled with a conductive material to form first conductive plugs 37

(first group of conductive plugs 371, second group of conductive plugs 372).

Further, when N = M, the method further includes forming a second opening in the mth substrate before/after/between/while forming M-1 sets of first openings in the mth substrate, the second opening extending from the mth substrate

One side of each substrate, which is far away from the (M-1) th substrate, is opened to expose the Mth device. Before filling the conductive material in the N-1 groups of first openings on the Nth substrate, opening second openings on the Mth substrate before, after, between and/or simultaneously with the M-1 groups of first openings on the Mth substrate; after the N-1 groups of first openings on the Nth substrate are filled with the conductive material, second openings can be formed on the Mth substrate.

Optionally, a second opening formed in the mth substrate is used for electrically leading out the mth device through the conductive plug, where the second opening includes at least one second sub-opening, and the second sub-opening of the second opening is used for selectively electrically leading out the mth device through the conductive plug.

Step S221, see fig. 5 (e) and 5 (f), when N = M =3, figure 5 (e) shows the third substrate with two sets of first openings 35 (first set of first openings 351, second set of first openings 352) filled with conductive material, the second opening 36 is opened in the third substrate 31 before the two sets of first openings 35 (the first set of first openings 351, the second set of first openings 352) are opened in the third substrate 31, and the second opening 36 is opened from the third substrate 31 on the side away from the second substrate 21 to expose the first conductive layer 331 and the second conductive layer 332 of the third deep trench capacitor 33.

Fig. 5 (f) shows that before the two sets of first openings 35 (the first set of first openings 351, the second set of first openings 352) on the third substrate 31 are filled with the conductive material, the two sets of first openings 35 (the first set of first openings 351, the second set of first openings 352) are opened on the third substrate 31, then the second opening 36 is opened on the third substrate 31, and the second opening 36 is opened from the side of the third substrate 31 away from the second substrate 21 to expose the first conductive layer 331 and the second conductive layer 332 of the third deep trench capacitor 33. The orthographic projection of the second opening 36 opened on the third substrate 31 on the first surface 311 of the third substrate 31 is located in the orthographic projection of the third deep trench capacitor 33 on the first surface 311 of the third substrate 31, and the second opening is used for electrically leading out the first conductive layer 331 and/or the second conductive layer 332 in the third deep trench capacitor 33 of the third substrate 31 through the conductive plug. The second opening 36 includes at least one second sub-opening, and the second sub-opening of the second opening 36 is used for selectively and electrically leading out the first conductive layer 331 and the second conductive layer 332 of each layer of the third deep trench capacitor 33 through the conductive plug. For example, the third deep trench capacitor 33 has three first conductive layers 331 and three second conductive layers 332, and if it is desired to electrically lead the first conductive layers 331 out of two and the second conductive layers 332 out of one, the number of the second sub-openings in the second opening 36 formed in the third substrate 31 is three.

Referring to fig. 5 (g), a first group of conductive plugs 371 may be formed by filling a conductive material in the first group of first openings 351 of the third substrate 31, a second group of conductive plugs 372 may be formed by filling a conductive material in the second group of first openings 352, and a second group of conductive plugs 38 may be formed by filling a conductive material in the second group of second openings 36 of the third substrate 31. In other embodiments, the first group of first openings 351 may be filled with a conductive material to form the first group of conductive plugs 371, the second group of first openings 352 may be filled with a conductive material to form the second group of conductive plugs 372, and the second openings 36 may be filled with a conductive material to form the second conductive plugs 38.

In step S231, referring to fig. 5 (h), when N = M =3, after the two groups of the first opening 35 and the second opening 36 on the third substrate 31 are filled with the conductive material to form the conductive plug, a redistribution Layer (redistribution Layer, RDL) 6, the redistribution Layer 6 electrically leads out the conductive plugs (the first conductive plugs 37 and the second conductive plugs 38) in the two sets of the first openings 35 (the first set of the first openings 351 and the second set of the first openings 352) and the second openings 36 on the third substrate 31.

According to the manufacturing method of the semiconductor device, the M substrates are bonded in sequence, wherein the Nth substrate is bonded to the (N-1) th substrate, and the Nth device is formed on one side, far away from the (N-1) th substrate, of the Nth substrate; forming N-1 groups of first openings on one side, away from the N-1 substrate, of the Nth substrate on the periphery of the Nth device, wherein the N-1 groups of first openings penetrate through the Nth substrate so as to expose the N-1 th device and the N-2 groups of first openings on the N-1 th substrate respectively; and filling a conductive material in the N-1 group of first openings on the Nth substrate to form conductive plugs, so that the conductive plugs can electrically lead out the devices respectively arranged on the M substrates, thereby facilitating the subsequent use of more circuit structures and improving the area utilization rate of the semiconductor devices.

Referring to fig. 6, fig. 6 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure.

The application also provides a semiconductor device 100, wherein the semiconductor device 100 comprises M substrates which are bonded in sequence, wherein an Nth device is formed on one side of the Nth substrate, which is far away from the (N-1) th substrate; the side, away from the (N-1) th substrate, of the Nth substrate on the periphery of the Nth device is provided with N-1 groups of first openings, and the N-1 groups of first openings penetrate through the Nth substrate to expose the (N-1) th device and N-2 groups of first openings on the (N-1) th substrate respectively; the N-1 group of first openings on the Nth substrate are filled with conductive plugs; wherein N is more than or equal to 2 and less than or equal to M, and N and M are integers.

The semiconductor device can be sequentially bonded with the M substrates, so that the M substrates are stacked, and the devices formed on the M substrates are electrically interconnected in the three-dimensional direction, and the density of the semiconductor device in a unit area is increased.

Each of the M substrates has opposing first and second surfaces. An Nth groove is arranged on the first surface of the Nth substrate, and an Nth deep groove capacitor is arranged on the surface of the Nth groove and the first surface of the Nth substrate at the periphery of the Nth groove. The Nth deep groove capacitor comprises a first conducting layer and a second conducting layer which are sequentially covered on the surface of the Nth groove and the first surface of the Nth substrate at the periphery of the Nth groove along with the shape, and a dielectric layer which is positioned between the first conducting layer and the second conducting layer and insulates the first conducting layer and the second conducting layer. Wherein the content of the first and second substances, the Nth deep trench capacitor can be at least one; the first surface of the Nth substrate is provided with the nth trench may be at least one. Wherein the first conductive layer and the second conductive layer are respectively used as an upper electrode plate and a lower electrode plate of the deep trench capacitor, and the first conductive layer and the second conductive layer extend to the first surface of the substrate at the periphery of the trench. Specifically, the first conductive layer and the second conductive layer on the first surface can be selectively exposed by the subsequently disposed opening part, so as to lead out the upper polar plate and the lower polar plate electrically in the follow-up process. The number of layers of the first conductive layer, the second conductive layer and the dielectric layer can be set according to requirements. In this embodiment, the material of the dielectric layer may include, but is not limited to, one or more combinations of polyimide, tetraethyl orthosilicate, silicon oxide, silicon nitride, silicon oxynitride, undoped silicon glass, benzocyclobutene (BCB), and Polybenzoxazole (PBO). The material of the first conductive layer and/or the second conductive layer may include, but is not limited to, one or more of conductive materials such as copper, silver, aluminum, doped silicon, titanium nitride, and the like.

In the following embodiments of the present application, the second surface of the nth substrate is bonded to the first surface of the N-1 st substrate for illustration, and in other optional embodiments, the first surface of the nth substrate may also be bonded to the first surface of the N-1 st substrate, wherein the first surface and/or the second surface of the nth substrate are/is formed with the above-mentioned device, that is, the first surface and/or the second surface of the nth substrate is/are formed with the above-mentioned deep trench capacitor.

In an optional embodiment, a side of the nth deep trench capacitor away from the nth substrate may be covered with a protection layer to protect the nth deep trench capacitor. The material of the protective layer may be the same as or different from that of the dielectric layer.

Optionally, the nth device at least partially overlaps with an orthographic projection of the nth-1 device on the first surface of the nth substrate.

Optionally, a kth group of first openings of the N-1 groups of first openings formed in the nth substrate are used for electrically leading out the kth device through the conductive plug. The first sub-opening in the kth group of first openings is used for leading out the kth device selectively and electrically through the conductive plug, wherein k is more than or equal to 1 and less than or equal to N-1, and k is an integer.

Further, when N = M, a second opening is opened on a side of the mth substrate away from the M-1 th substrate, and the second opening exposes the mth device.

Optionally, an orthogonal projection of the second opening formed in the mth substrate on the first surface of the mth substrate is located in an orthogonal projection of the mth device on the first surface of the mth substrate.

Optionally, the second opening formed in the mth substrate is used for electrically leading out the mth device through the conductive plug. The second opening comprises at least one second sub-opening, and the second sub-opening of the second opening is used for selectively and electrically leading out the Mth device through the conductive plug. The number of the second sub-openings in the second opening depends on the number of the first conductive layers and the second conductive layers in the Mth deep trench capacitor which need to be electrically led out.

The first opening and the second opening are filled with conductive plugs, so that the device electrical property exposed by the first opening and the second opening is led out to one side of the Nth substrate far away from the (N-1) th substrate through the conductive plugs.

Optionally, a redistribution layer is formed on one side of the mth substrate, which is away from the M-1 th substrate, and the redistribution layer electrically leads out the conductive plugs in the first opening and the second opening of the mth substrate M-1 group.

In one embodiment, the semiconductor device is described in detail with M =3, i.e. three substrates bonded in sequence, the values of N are 2 and 3.

Referring to fig. 6, a first deep trench capacitor 13 is formed on the first surface 111 of the first substrate 11. When N =2, the second surface 212 of the second substrate 21 is bonded to the first surface 111 of the first substrate 11, a second deep trench capacitor 23 is formed on one side of the second substrate 21 away from the first substrate 11; a set of first openings 25 is formed in the second substrate 21 at a side of the second deep trench capacitor 23 away from the first substrate 11, and the set of first openings 25 penetrates through the second substrate 21 to expose the first conductive layer 131 and/or the second conductive layer 132 of the first deep trench capacitor 13. The first conductive plugs 27 are filled in the first openings 25 of the second substrate 21. When N =3, the second surface 312 of the third substrate 31 is bonded to the first surface 211 of the second substrate 21, a third deep trench capacitor 33 is formed on the third substrate 31 at a side away from the second substrate 21; two sets of first openings 35 (a first set of first openings 351 and a second set of first openings 352) are formed on a side of the third substrate 31 away from the second substrate 21, which is peripheral to the third deep trench capacitor 33, wherein the two sets of first openings 35 penetrate through the third substrate 31 to expose the first conductive layer 231 and/or the second conductive layer 232 of the second deep trench capacitor 23 and the set of first openings 25 on the second substrate 21, that is, the second set of first openings 352 expose the first conductive layer 231 and/or the second conductive layer 232 of the second deep trench capacitor 23, and the first set of first openings 351 expose the set of first openings 25 on the second substrate 21. The first conductive plugs 37 are filled in the two groups of first openings 35 on the third substrate 31, the first group of first openings 351 are filled with the first group of conductive plugs 371, and the second group of first openings 352 are filled with the second group of conductive plugs 372. A second opening 36 is further formed on a side of the third substrate 31 away from the second substrate 21, the second opening 36 exposes the first conductive layer 331 and/or the second conductive layer 332 of the third deep trench capacitor 33, the orthographic projection of the second opening 36 on the first surface 311 of the third substrate 31 is located in the orthographic projection of the third deep trench capacitor 33 on the first surface 311 of the third substrate 31, and the second opening 36 is filled with the second conductive plug 38.

In the alternative, orthographic projections of the third deep trench capacitor 33, the second deep trench capacitor 23, and the first deep trench capacitor 13 on the first surface 311 of the third substrate 31 at least partially overlap.

Optionally, a redistribution Layer (RDL) 6 is formed on a side of the third substrate 31 away from the second substrate 21, the redistribution Layer 6 electrically leads out the conductive plugs (the first conductive plug 37 and the second conductive plug 38) in the two sets of the first opening 35 and the second opening 36 of the third substrate 31.

Optionally, the orthographic projections of the two sets of first openings 35 (the first set of first openings 351, the second set of first openings 352) opened on the third substrate 31 on the first surface 111 of the first substrate 11 are located in the orthographic projection of the first deep trench capacitor 13 on the first surface 111 of the first substrate 11 and do not overlap with the orthographic projection of the third deep trench capacitor 33 on the first surface 111 of the first substrate 11. The orthographic projection of a group of first openings 25 formed on the second substrate 21 on the first surface 111 of the first substrate 11 is positioned on the first deep trench capacitor 13 on the second surface the orthographic projection of the first surface 111 of the first substrate 11 is not overlapped with the orthographic projection of the second deep trench capacitor 23 on the first surface 111 of the first substrate 11.

Wherein the content of the first and second substances, the first group of first openings 351 are used for electrically leading out the first conductive layer 131 and/or the second conductive layer 132 of the first deep trench capacitor 13 through the first group of conductive plugs 371 and the first conductive plugs 27 in the group of first openings 25 formed in the second substrate 21; a second set of first openings 352 through a second set of conductive plugs 372 for coupling a second one the first conductive layer 131 and/or the second conductive layer 132 of the deep trench capacitor 23 are electrically led out; the second opening 36 is used to electrically lead out the first conductive layer 331 and/or the second conductive layer 332 of the third deep trench capacitor 33 through the second conductive plug 38.

The two groups of first openings 35 formed in the third substrate 31 and the one group of first openings 25 formed in the second substrate 21 may each include at least one first sub-opening, and the first sub-opening in the first group of first openings 351 is used for selectively and electrically leading out the first conductive layer 131 and the second conductive layer 132 of the first deep trench capacitor 13 through the conductive plug and the conductive plug in the first sub-opening in the one group of first openings 25 formed in the second substrate 21; a first sub-opening of the second group of first openings 352 is used for selectively and electrically leading out the first conductive layer 131 and the second conductive layer 132 of the second deep trench capacitor 23 through a conductive plug; the second opening 36 formed in the third substrate 31 may include at least one second sub-opening, and the second sub-opening of the second opening 36 is used for selectively and electrically leading out the first conductive layer 331 and the second conductive layer 332 of the third deep trench capacitor 33 through a conductive plug.

According to the semiconductor device provided by the embodiment of the application, M substrates are sequentially bonded, an Nth device is formed on one side, away from the (N-1) th substrate, of the Nth substrate, N-1 groups of first openings are formed in the side, away from the (N-1) th substrate, of the Nth substrate on the periphery of the Nth device, and the N-1 groups of first openings penetrate through the Nth substrate to expose the (N-1) th device and N-2 groups of first openings in the (N-1) th substrate respectively; the number of the deep trench capacitor structures can be increased under the same area by filling the conductive plugs in the N-1 group of first openings on the Nth substrate so as to electrically lead out the devices on each substrate through the conductive plugs, and the plurality of deep trench capacitor structures are sequentially stacked by increasing the number of the deep trench capacitor structures under the condition that the occupied area of the semiconductor device is the same so as to be used by more circuit structures and increase the capacitance density in the unit area of the semiconductor device.

It should be understood that, in this document, the numbers "first", "second", "third", etc. are only used for distinguishing each different component or process having the same name, and do not mean the order or positional relationship, etc. In addition, for respective different components having the same name, for example, "first conductive layer" and "second conductive layer", "first substrate" and "second substrate", and the like, it does not mean that they all have the same structure or component. For example, although not shown, in most cases, the components formed in the "first substrate" and the "second substrate" are different, and the structure of the wafer may be different. In some embodiments, the wafer may be of a semiconductor material, made of any semiconductor material suitable for semiconductor devices (such as Si, siC, siGe, etc.). In other embodiments, the wafer may be a composite substrate such as a silicon-on-insulator (SOI) substrate or a silicon germanium-on-insulator (sige-on-insulator substrate). It will be understood by those skilled in the art that the substrate is not subject to any limitations, but may be selected according to the actual application. The wafer may also have other layers or components, such as: gate structures, contact holes, dielectric layers, metal lines and openings, and the like.

The above embodiments are merely examples and are not intended to limit the scope of the present disclosure, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present disclosure or those directly or indirectly applied to other related technical fields are intended to be included in the scope of the present disclosure.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming N-1 groups of first openings on an Nth substrate, wherein the N-1 groups of first openings are positioned on the periphery of the Nth device, and the N-1 groups of first openings are formed on one side of the Nth substrate, which is far away from the N-1 substrate, and penetrate through the Nth substrate so as to expose the N-1 devices and the N-2 groups of first openings formed on the N-1 substrate respectively;

2. The method of claim 1,

when N = M, further comprising opening a second opening in the mth substrate, the second opening being opened from a side of the mth substrate away from the M-1 st substrate to expose the mth device.

3. The method of claim 2,

when N = M, after the conductive material is filled in the N-1 group of first openings and the second openings on the nth substrate, forming a redistribution layer on a side of the mth substrate away from the M-1 substrate, where the redistribution layer electrically leads out the conductive plugs in the M-1 group of first openings and the second openings of the mth substrate.

4. The method of claim 1, wherein the nth device at least partially overlaps an orthographic projection of the N-1 th device on the nth substrate surface.

5. The method of claim 1, wherein the device is a deep trench capacitor.

6. The method of claim 5, wherein the forming of the Nth deep trench capacitor comprises,

forming an Nth groove extending from the first surface to the second surface on the first surface of the Nth substrate, and forming an Nth deep groove capacitor in the Nth groove, wherein the Nth deep groove capacitor comprises a first conductive layer and a second conductive layer which sequentially cover the surface of the Nth groove and the first surface of the Nth substrate at the periphery of the Nth groove, and a dielectric layer which is positioned between the first conductive layer and the second conductive layer and insulates the first conductive layer and the second conductive layer; wherein the first conductive layer and the second conductive layer are respectively used as the upper electrode plate and the lower electrode plate of the deep trench capacitor.

7. The method of claim 6, wherein the second surface of the nth substrate is bonded to the first surface of the N-1 th substrate.

8. The method of claim 1,

and thinning the side of the Nth substrate far away from the Nth-1 substrate after the Nth substrate is bonded to the Nth-1 substrate and before the Nth device is formed.

9. A semiconductor device, comprising: m substrates bonded in sequence, wherein,

the side, away from the N-1 substrate, of the Nth substrate on the periphery of the Nth device is provided with N-1 groups of first openings, and the N-1 groups of first openings penetrate through the Nth substrate to expose the N-1 device and N-2 groups of first openings on the N-1 substrate respectively;

10. The method of claim 9,

when N = M, a second opening is opened on the side of the Mth substrate away from the M-1 th substrate, and the second opening exposes the Mth device.

11. The method of claim 10,

the second opening is filled with a conductive plug;

and a redistribution layer is formed on one side of the Mth substrate, which is far away from the Mth-1 substrate, and the redistribution layer leads out the conductive plugs in the first opening and the second opening of the Mth substrate M-1 group electrically.