CN115955913A - Capacitor structure, preparation method thereof and semiconductor structure - Google Patents
Capacitor structure, preparation method thereof and semiconductor structure Download PDFInfo
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- 239000003990 capacitor Substances 0.000 title claims abstract description 75
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 238000003475 lamination Methods 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims description 27
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 8
- 239000007789 gas Substances 0.000 description 16
- 230000008021 deposition Effects 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 7
- 239000012495 reaction gas Substances 0.000 description 4
- 229910001415 sodium ion Inorganic materials 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- FKNQFGJONOIPTF-UHFFFAOYSA-N Sodium cation Chemical compound [Na+] FKNQFGJONOIPTF-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/13—Energy storage using capacitors
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Abstract
The application relates to a capacitor structure, a preparation method thereof and a semiconductor structure. The capacitor structure includes: a first electrode plate; the dielectric lamination comprises a first dielectric layer, a second dielectric layer and a third dielectric layer which are sequentially laminated, wherein the first dielectric layer is positioned on the surface of the first polar plate; the refractive index of the first medium layer and the refractive index of the third medium layer are both lower than the refractive index of the second medium layer; and the second polar plate is positioned on the surface of the third medium layer, which is far away from the first polar plate. The dielectric lamination of the capacitor structure has a high dielectric constant value, the capacitor density is improved, and the refractive index of the first dielectric layer and the refractive index of the third dielectric layer are both lower than the refractive index of the second dielectric layer, so that the stress of the dielectric layer directly contacted with the upper and lower electrode plates of the capacitor is low, and the problem of dielectric layer stress increase caused by improving the capacitor density is solved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a capacitor structure, a method for manufacturing the capacitor structure, and a semiconductor structure.
Background
With the development of semiconductor technology, attention has been given to elements such as capacitors, which are important in semiconductor devices, and attention has been given to technologies related to the increase in capacitance density of capacitors. In order to increase the capacitance density of the capacitor, it is usually achieved by increasing the dielectric constant of the dielectric layer.
However, the way of increasing the dielectric constant of the dielectric layer to increase the capacitance density will cause the stress of the dielectric layer to increase, and the problem of larger stress will weaken the original insulation and passivation effects of the dielectric layer, directly affecting the performance of the semiconductor device.
Disclosure of Invention
In view of the above, it is necessary to provide a capacitor structure, a method for manufacturing the same, and a semiconductor structure.
In order to solve the above problem, in a first aspect, the application provides a capacitor structure, including:
a first electrode plate;
the dielectric lamination comprises a first dielectric layer, a second dielectric layer and a third dielectric layer which are sequentially laminated, wherein the first dielectric layer is positioned on the surface of the first polar plate; the refractive index of the first medium layer and the refractive index of the third medium layer are both lower than the refractive index of the second medium layer;
and the second polar plate is positioned on the surface of the third medium layer far away from the first polar plate.
The capacitor structure comprises a first polar plate, a dielectric lamination and a second polar plate, wherein the dielectric lamination comprises a first dielectric layer, a second dielectric layer and a third dielectric layer, and the parameters of each dielectric layer are conveniently set by making the dielectric lamination into a lamination consisting of three dielectric layers; the refractive index of the first dielectric layer and the refractive index of the third dielectric layer are both lower than the refractive index of the second dielectric layer, and according to the direct proportion relation between the refractive indexes and the dielectric constant, the refractive index of the second dielectric layer is higher than the refractive indexes of the first dielectric layer and the third dielectric layer, so that the dielectric constant value of the dielectric lamination can be increased, and the capacitance density is improved; and the first dielectric layer is positioned on the surface of the first pole plate, the second pole plate is positioned on the surface of the third dielectric layer, and the refractive index of the first dielectric layer and the refractive index of the third dielectric layer are both lower than the refractive index of the second dielectric layer, so that the stress of the dielectric layer directly contacted with the upper pole plate and the lower pole plate of the capacitor is lower, and the problem of dielectric layer stress increase caused by improving the density of the capacitor is solved.
In one embodiment, the refractive index of the second medium layer is 1.1 to 1.2 times of the refractive index of the first medium layer; the refractive index of the second medium layer is 1.1 to 1.2 times of the refractive index of the third medium layer.
In one embodiment, the first dielectric layer, the second dielectric layer and the third dielectric layer comprise a silicon nitride layer.
In one embodiment, the thicknesses of the first dielectric layer and the third dielectric layer are both smaller than the thickness of the second dielectric layer.
In one embodiment, the sum of the thicknesses of the first dielectric layer and the third dielectric layer is the same as the thickness of the second dielectric layer.
In a second aspect, the present application further provides a method for manufacturing a capacitor structure, including:
forming a first polar plate;
forming a dielectric lamination on the surface of the first polar plate; the dielectric lamination comprises a first dielectric layer, a second dielectric layer and a third dielectric layer which are sequentially laminated, wherein the first dielectric layer is positioned on the surface of the first polar plate; the refractive index of the first medium layer and the refractive index of the third medium layer are both lower than the refractive index of the second medium layer;
and forming a second polar plate on the surface of the third dielectric layer far away from the first polar plate.
According to the preparation method of the capacitor structure, the dielectric lamination is formed on the surface of the first polar plate and comprises the first dielectric layer, the second dielectric layer and the third dielectric layer, and the parameters of each dielectric layer are conveniently set by making the dielectric lamination into the lamination formed by three dielectric layers; the refractive index of the first dielectric layer and the refractive index of the third dielectric layer are both lower than the refractive index of the second dielectric layer, and the refractive index of the second dielectric layer is higher than the refractive indexes of the first dielectric layer and the third dielectric layer according to the proportional relation between the refractive indexes and the dielectric constant, so that the dielectric constant value of the dielectric lamination can be increased, and the capacitance density is improved; and the first dielectric layer is positioned on the surface of the first pole plate, the second pole plate is positioned on the surface of the third dielectric layer, and the refractive index of the first dielectric layer and the refractive index of the third dielectric layer are both lower than the refractive index of the second dielectric layer, so that the stress of the dielectric layer directly contacted with the upper pole plate and the lower pole plate of the capacitor is lower, and the problem of dielectric layer stress increase caused by improving the density of the capacitor is solved.
In one embodiment, the forming a dielectric stack on the surface of the first plate includes:
forming the first dielectric layer on the surface of the first polar plate;
forming a second dielectric layer on the surface of the first dielectric layer far away from the first polar plate;
and forming the third dielectric layer on the surface of the second dielectric layer far away from the first dielectric layer.
In one embodiment, the stress of the first dielectric layer and the stress of the third dielectric layer are both smaller than the stress of the second dielectric layer by controlling the radio frequency power and the gas flow rate used in the process of forming the dielectric stack.
In one embodiment, the radio frequency power adopted in the process of forming the second dielectric layer is 200W to 450W, and the gas flow is 100sccm to 150sccm.
In a third aspect, the present application further provides a semiconductor structure, comprising:
a substrate;
the capacitor structure of any one of the above aspects, located on a surface of the substrate.
The semiconductor structure comprises the capacitor structure, wherein the capacitor structure comprises a first electrode plate, a dielectric lamination and a second electrode plate, wherein the dielectric lamination comprises a first dielectric layer, a second dielectric layer and a third dielectric layer, and the parameters of each dielectric layer are conveniently set by making the dielectric lamination into a lamination consisting of three dielectric layers; the refractive index of the first dielectric layer and the refractive index of the third dielectric layer are both lower than the refractive index of the second dielectric layer, and the refractive index of the second dielectric layer is higher than the refractive indexes of the first dielectric layer and the third dielectric layer according to the proportional relation between the refractive indexes and the dielectric constant, so that the dielectric constant value of the dielectric lamination can be increased, and the capacitance density is improved; and the first dielectric layer is positioned on the surface of the first pole plate, the second pole plate is positioned on the surface of the third dielectric layer, and the refractive index of the first dielectric layer and the refractive index of the third dielectric layer are both lower than the refractive index of the second dielectric layer, so that the stress of the dielectric layer directly contacted with the upper pole plate and the lower pole plate of the capacitor is lower, and the problem of dielectric layer stress increase caused by improving the density of the capacitor is solved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic cross-sectional view of a capacitor structure provided in one embodiment;
FIG. 2 is a flow chart illustrating steps in a method for fabricating a capacitor structure according to an embodiment;
FIG. 3 is a plot of RF power versus refractive index as provided in an embodiment;
FIG. 4 is a graph of refractive index versus gas flow provided in an embodiment;
FIG. 5 is a graphical illustration of the relationship between gas flow, RF power, and refractive index and deposition rate provided in one embodiment.
Description of reference numerals:
10-a first plate; 20-a dielectric stack; 201-a first dielectric layer; 202-a second dielectric layer; 203-a third dielectric layer; 30-second polar plate.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
With the development of semiconductor technology, attention has been given to elements such as capacitors, which are important in semiconductor devices, and attention has been given to technologies related to the increase in capacitance density of capacitors. In order to increase the capacitance density of the capacitor, it is usually achieved by reducing the thickness of the dielectric layer or increasing the dielectric constant of the dielectric layer.
However, the thickness of the capacitor dielectric layer cannot be decreased indefinitely due to process limitations. The way of improving the dielectric constant of the dielectric layer to improve the capacitance density can cause the stress of the dielectric layer to increase, and the problem of larger stress can weaken the original insulation and passivation effects of the dielectric layer and directly influence the performance of the semiconductor device.
In view of the foregoing, it is desirable to provide a capacitor structure, a method for fabricating the same, and a semiconductor structure.
The present application provides a capacitor structure, as shown in fig. 1, the capacitor structure includes a first plate 10, a dielectric stack 20, and a second plate 30; the dielectric stack 20 includes a first dielectric layer 201, a second dielectric layer 202 and a third dielectric layer 203 which are sequentially stacked, and the first dielectric layer 201 is located on the surface of the first electrode plate 10; the refractive index of the first dielectric layer 201 and the refractive index of the third dielectric layer 203 are both lower than the refractive index of the second dielectric layer 202; the second plate 30 is located on the surface of the third dielectric layer 203 far from the first plate 10.
Wherein, the first electrode plate 10 and the second electrode plate 30 may both include metal electrode plates; the second dielectric layer 202 is positioned on the surface of the first dielectric layer 201 far away from the first polar plate 10; the third dielectric layer 203 is located on the surface of the second dielectric layer 202 away from the first dielectric layer 201.
In some examples, the density of the second dielectric layer 202 is greater than the density of the first dielectric layer 201 and the third dielectric layer 203.
In the capacitor structure in the above embodiment, the dielectric stack 20 is made into a stack of three dielectric layers, so as to set parameters of each dielectric layer respectively; the refractive index of the first dielectric layer 201 and the refractive index of the third dielectric layer 203 are both lower than the refractive index of the second dielectric layer 202, and according to the direct proportion relationship between the refractive indexes and the dielectric constants, the refractive index of the second dielectric layer 202 is higher than the refractive indexes of the first dielectric layer 201 and the third dielectric layer 203, so that the dielectric constant value of the dielectric stack 20 can be increased, and the capacitance density can be improved; moreover, the first dielectric layer 201 is located on the surface of the first pole plate 10, the second pole plate 30 is located on the surface of the third dielectric layer 203, and the refractive index of the first dielectric layer 201 and the refractive index of the third dielectric layer 203 are both lower than the refractive index of the second dielectric layer 202, so that the stress of the dielectric layers directly contacting with the upper and lower pole plates of the capacitor is lower, and the problem of dielectric layer stress increase caused by improving the density of the capacitor is solved.
In one embodiment, the refractive index of the second dielectric layer 202 is 1.1 to 1.2 times of the refractive index of the first dielectric layer 201; the refractive index of the second dielectric layer 202 is 1.1 to 1.2 times of the refractive index of the third dielectric layer 203.
Illustratively, since the dielectric constant is proportional to the square of the refractive index, the dielectric constant of the first dielectric layer 201 and the dielectric constant of the third dielectric layer 203 are both lower than the dielectric constant of the second dielectric layer 202; further, the dielectric constant of the second dielectric layer 202 is 1.21 to 1.44 times of that of the first dielectric layer 201; the dielectric constant of the second dielectric layer 202 is 1.21 to 1.44 times that of the third dielectric layer 203.
In one embodiment, the first dielectric layer 201, the second dielectric layer 202, and the third dielectric layer 203 each comprise a silicon nitride layer.
Wherein, due to Si 3 N 4 The (silicon nitride) layer has strong sodium ion resistance and water vapor resistance, the diffusion rate of sodium ions and water vapor in the silicon nitride layer is very low, and the silicon nitride layer has the characteristics of good compactness, few pinholes, high hardness, wear resistance, good scratch resistance and the like, and can improve the performance of a capacitor structure when being used as a capacitor dielectric layer.
In one embodiment, the thickness of the first dielectric layer 201 and the third dielectric layer 203 are both less than the thickness of the second dielectric layer 202.
Since the dielectric constant of the capacitor is inversely proportional to the thickness of the dielectric layers, the thicknesses of the first dielectric layer 201 and the third dielectric layer 203 are both smaller than the thickness of the second dielectric layer 202, so that the dielectric constant of the whole capacitor can be increased, and the density of the capacitor can be improved. Moreover, the thickness of the dielectric layer also affects the stress, the thicknesses of the first dielectric layer 201 and the third dielectric layer 203 are smaller, so that the stresses of the first dielectric layer 201 and the third dielectric layer 203 are also smaller, the first dielectric layer 201 is positioned on the surface of the first electrode plate 10, and the second electrode plate 30 is positioned on the surface of the third dielectric layer 203, so that the overall stress of the capacitor is smaller, and the problem of dielectric layer stress increase caused by increasing the density of the capacitor is solved. And the thickness of the second dielectric layer 202 is larger than that of the first dielectric layer 201 and the third dielectric layer 203, so that the problem that the thickness of the capacitor dielectric layer cannot be reduced to a great extent due to process limitation is solved.
In one embodiment, the sum of the thicknesses of the first dielectric layer 201 and the third dielectric layer 203 is the same as the thickness of the second dielectric layer 202.
On the basis of balancing the requirements of thickness and refractive index, the stress of the dielectric laminated layer 20 is reduced as much as possible, and the sum of the thicknesses of the first dielectric layer 201 and the third dielectric layer 203 is set to be the same as the thickness of the second dielectric layer 202, so that the overall stress of the dielectric layers is balanced; further, the thickness of the first dielectric layer 201 may be the same as that of the third dielectric layer 203, so as to avoid the dielectric stack 20 from having too large difference in the upper and lower surface stresses.
The present application further provides a method for manufacturing a capacitor structure, as shown in fig. 2, the method for manufacturing a capacitor structure may include the following steps:
s201: forming a first plate 10.
Wherein the first plate 10 comprises a metal substrate.
S202: forming a dielectric stack 20 on the surface of the first electrode plate 10; the dielectric stack 20 includes a first dielectric layer 201, a second dielectric layer 202 and a third dielectric layer 203, which are sequentially stacked, wherein the first dielectric layer 201 is located on the surface of the first electrode plate 10; the refractive index of the first dielectric layer 201 and the refractive index of the third dielectric layer 203 are both lower than the refractive index of the second dielectric layer 202.
The second dielectric layer 202 is located on the surface of the first dielectric layer 201 far away from the first electrode plate 10; the third dielectric layer 203 is located on the surface of the second dielectric layer 202 away from the first dielectric layer 201.
S203: a second plate 30 is formed on the surface of the third dielectric layer 203 away from the first plate 10, as shown in fig. 1.
Wherein the second plate 30 includes a metal substrate.
In some examples, the density of the second dielectric layer 202 is greater than the density of the first dielectric layer 201 and the third dielectric layer 203.
The capacitor structure obtained after steps S201 to S203 can refer to fig. 1. Of course, in order to facilitate understanding of the present invention, fig. 1 shows an example of a semiconductor structure manufactured by the method for manufacturing a capacitor structure according to the present invention, and the capacitor structure manufactured by the method for manufacturing a capacitor structure according to the present invention may have other suitable examples, which are not limited herein.
In the method for manufacturing the capacitor structure in the above embodiment, the dielectric stack 20 is formed on the surface of the first electrode plate 10, the dielectric stack 20 includes the first dielectric layer 201, the second dielectric layer 202, and the third dielectric layer 203, and the parameters of each dielectric layer are set by forming the dielectric stack 20 into a stack of three dielectric layers; the refractive index of the first dielectric layer 201 and the refractive index of the third dielectric layer 203 are both lower than the refractive index of the second dielectric layer 202, and according to the proportional relation between the refractive indexes and the dielectric constants, the refractive index of the second dielectric layer 202 is higher than the refractive indexes of the first dielectric layer 201 and the third dielectric layer 203, so that the dielectric constant value of the dielectric stack 20 can be increased, and the capacitance density can be improved; moreover, the first dielectric layer 201 is located on the surface of the first pole plate 10, the second pole plate 30 is located on the surface of the third dielectric layer 203, and the refractive index of the first dielectric layer 201 and the refractive index of the third dielectric layer 203 are both lower than the refractive index of the second dielectric layer 202, so that the stress of the dielectric layers directly contacting with the upper and lower pole plates of the capacitor is lower, and the problem of dielectric layer stress increase caused by improving the density of the capacitor is solved.
In one embodiment, the refractive index of the second dielectric layer 202 is 1.1 to 1.2 times of the refractive index of the first dielectric layer 201; the refractive index of the second dielectric layer 202 is 1.1 to 1.2 times of the refractive index of the third dielectric layer 203.
Illustratively, since the dielectric constant is proportional to the square of the refractive index, the dielectric constant of the first dielectric layer 201 and the dielectric constant of the third dielectric layer 203 are both lower than the dielectric constant of the second dielectric layer 202; further, the dielectric constant of the second dielectric layer 202 is 1.21 to 1.44 times of that of the first dielectric layer 201; the dielectric constant of the second dielectric layer 202 is 1.21 to 1.44 times that of the third dielectric layer 203.
In one embodiment, the first dielectric layer 201, the second dielectric layer 202, and the third dielectric layer 203 each comprise a silicon nitride layer.
Wherein, due to Si 3 N 4 The (silicon nitride) layer has strong sodium ion resistance and water vapor resistance, the diffusion rate of sodium ions and water vapor in the silicon nitride layer is very low, and the silicon nitride layer has the characteristics of good compactness, few pinholes, high hardness, wear resistance, good scratch resistance and the like, and can improve the performance of a capacitor structure when being used as a capacitor dielectric layer.
In one embodiment, forming the dielectric stack 20 on the surface of the first plate 10 may include the following steps: forming a first dielectric layer 201 on the surface of the first electrode plate 10; forming a second dielectric layer 202 on the surface of the first dielectric layer 201 far away from the first electrode plate 10; and forming a third dielectric layer 203 on the surface of the second dielectric layer 202 far away from the first dielectric layer 201.
In one embodiment, the stress of the first dielectric layer 201 and the stress of the third dielectric layer 203 are both lower than the stress of the second dielectric layer 202 by controlling the rf power and the gas flow rate used in the process of forming the dielectric stack 20.
Wherein, the gas refers to reaction gas used in the process of forming the dielectric layer, and the gas flow comprises silane flow; referring to fig. 3 and 4, according to a relationship curve of the radio frequency power and the refractive index of the dielectric layer, a relationship curve of the gas flow and the refractive index of the dielectric layer, and a relationship between the radio frequency power and the deposition rate of the dielectric layer material, and a relationship between the gas flow and the deposition rate of the dielectric layer material, the relationship diagram of the gas flow, the radio frequency power, the refractive index and the deposition rate shown in fig. 5 can be obtained by fitting, wherein curve 1 represents the refractive index, and curve 2 represents the deposition rate; the gas flow rate, the radio frequency power, the deposition rate, and the like in the process conditions when forming each dielectric layer can be controlled based on the desired refractive index to obtain a dielectric layer having a desired refractive index. In addition, the dielectric stack 20 of the present application includes a first dielectric layer 201, a second dielectric layer 202, and a third dielectric layer 203, and the first dielectric layer 201, the second dielectric layer 202, and the third dielectric layer 203 are all formed separately, so that in the preparation process, the forming conditions of the first dielectric layer 201, the second dielectric layer 202, and the third dielectric layer 203 can be controlled respectively to obtain corresponding refractive indexes.
For example, if the dielectric layer material is silicon nitride and the reaction gas is silane, the lower the radio frequency power is, the slower the deposition rate of silicon nitride is, because the smaller the supplied energy is, the smaller the electron acquisition energy is, the weaker the molecular impact degree is, the slower the decomposition and ionization speed of the reaction gas is, the fewer the active groups required for the reaction are, and the slower the film forming rate is; the lower the gas flow, the slower the deposition rate, because of the SiH 4 (silane) is the source of silicon element in silicon nitride if SiH is present in the reaction gas 4 Less, the deposition rate of silicon nitride naturally slows down.
Illustratively, referring still to fig. 5, region a is the selected region for forming the second dielectric layer 202, and the corresponding rf power range and gas flow range in region a may be used to help achieve a higher index of refraction for the second dielectric layer 202 than for the first dielectric layer 201 and the third dielectric layer 203.
In one embodiment, the radio frequency power used in the process of forming the second dielectric layer 202 is 200W to 450W, and the gas flow is 100sccm to 150sccm.
For example, the radio frequency power used in the process of forming the second dielectric layer 202 may be 200W, 250W, 300W, 350W, 400W, or 450W, or may be other radio frequency powers between 200w to 450w, which is not limited in this embodiment; the gas flow rate used in the process of forming the second dielectric layer 202 can be 100sccm, 110sccm, 120sccm, 130sccm, 140sccm, or 150sccm, or other gas flow rates between 100sccm and 150sccm, which is not limited in this embodiment.
In one embodiment, the thickness of the first dielectric layer 201 and the third dielectric layer 203 are both less than the thickness of the second dielectric layer 202.
Since the dielectric constant of the capacitor is inversely proportional to the thickness of the dielectric layers, the thicknesses of the first dielectric layer 201 and the third dielectric layer 203 are both smaller than the thickness of the second dielectric layer 202, so that the dielectric constant of the whole capacitor can be increased, and the density of the capacitor can be improved. In addition, the thicknesses of the dielectric layers also affect the stress, the thicknesses of the first dielectric layer 201 and the third dielectric layer 203 are smaller, so that the stresses of the first dielectric layer 201 and the third dielectric layer 203 are also smaller, the first dielectric layer 201 is located on the surface of the first electrode plate 10, and the second electrode plate 30 is located on the surface of the third dielectric layer 203, so that the overall stress of the capacitor is smaller, and the problem of dielectric layer stress increase caused by improving the density of the capacitor is solved. And the thickness of the second dielectric layer 202 is larger than that of the first dielectric layer 201 and the third dielectric layer 203, so that the problem that the thickness of the capacitor dielectric layer cannot be reduced to a great extent due to process limitation is solved.
In one embodiment, the sum of the thicknesses of the first dielectric layer 201 and the third dielectric layer 203 is the same as the thickness of the second dielectric layer 202.
On the basis of balancing the requirements of thickness and refractive index, the stress of the dielectric laminated layer 20 is reduced as much as possible, and the sum of the thicknesses of the first dielectric layer 201 and the third dielectric layer 203 is set to be the same as the thickness of the second dielectric layer 202, so that the overall stress of the dielectric layers is balanced; further, the thickness of the first dielectric layer 201 may be the same as that of the third dielectric layer 203, so as to avoid the dielectric stack 20 from having an excessively large difference in the upper and lower surface stresses.
It should be understood that, although the steps in the flowcharts of the embodiments are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in the flowcharts of the embodiments may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a portion of the steps or stages in other steps.
Based on the same inventive concept, the present application also provides a semiconductor structure (not shown). The semiconductor structure includes: a substrate and a capacitive structure according to any aspect of the present application; the capacitor structure is located on the surface of the substrate.
The semiconductor structure in the above embodiment includes the capacitor structure of the present application, and the capacitor structure includes the first electrode plate 10, the dielectric stack 20 and the second electrode plate 30, where the dielectric stack 20 includes the first dielectric layer 201, the second dielectric layer 202 and the third dielectric layer 203, and the dielectric stack 20 is made into a stack of three dielectric layers, so as to set parameters of each dielectric layer respectively; the refractive index of the first dielectric layer 201 and the refractive index of the third dielectric layer 203 are both lower than the refractive index of the second dielectric layer 202, and according to the direct proportion relationship between the refractive indexes and the dielectric constants, the refractive index of the second dielectric layer 202 is higher than the refractive indexes of the first dielectric layer 201 and the third dielectric layer 203, so that the dielectric constant value of the dielectric stack 20 can be increased, and the capacitance density can be improved; moreover, the first dielectric layer 201 is located on the surface of the first pole plate 10, the second pole plate 30 is located on the surface of the third dielectric layer 203, and the refractive index of the first dielectric layer 201 and the refractive index of the third dielectric layer 203 are both lower than the refractive index of the second dielectric layer 202, so that the stress of the dielectric layers directly contacting with the upper and lower pole plates of the capacitor is lower, and the problem of dielectric layer stress increase caused by improving the density of the capacitor is solved.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A capacitive structure, comprising:
a first electrode plate;
the dielectric lamination comprises a first dielectric layer, a second dielectric layer and a third dielectric layer which are sequentially laminated, wherein the first dielectric layer is positioned on the surface of the first polar plate; the refractive index of the first medium layer and the refractive index of the third medium layer are both lower than the refractive index of the second medium layer;
and the second polar plate is positioned on the surface of the third medium layer far away from the first polar plate.
2. The capacitor structure according to claim 1, wherein the refractive index of the second dielectric layer is 1.1 to 1.2 times of the refractive index of the first dielectric layer; the refractive index of the second medium layer is 1.1 to 1.2 times of that of the third medium layer.
3. The capacitor structure of claim 1, wherein the first dielectric layer, the second dielectric layer, and the third dielectric layer each comprise a silicon nitride layer.
4. The capacitor structure of claim 1, wherein the thickness of the first dielectric layer and the third dielectric layer are both less than the thickness of the second dielectric layer.
5. The capacitor structure of claim 4, wherein the sum of the thicknesses of the first dielectric layer and the third dielectric layer is the same as the thickness of the second dielectric layer.
6. A method for manufacturing a capacitor structure, comprising:
forming a first polar plate;
forming a dielectric lamination on the surface of the first polar plate; the dielectric lamination comprises a first dielectric layer, a second dielectric layer and a third dielectric layer which are sequentially laminated, wherein the first dielectric layer is positioned on the surface of the first polar plate; the refractive index of the first medium layer and the refractive index of the third medium layer are both lower than the refractive index of the second medium layer;
and forming a second polar plate on the surface of the third dielectric layer far away from the first polar plate.
7. The method of claim 6, wherein forming a dielectric stack on the surface of the first plate comprises:
forming the first dielectric layer on the surface of the first polar plate;
forming the second dielectric layer on the surface of the first dielectric layer far away from the first polar plate;
and forming the third dielectric layer on the surface of the second dielectric layer far away from the first dielectric layer.
8. The method of claim 7, wherein the stress of the first dielectric layer and the stress of the third dielectric layer are both lower than the stress of the second dielectric layer by controlling the RF power and the gas flow rate used in the process of forming the dielectric stack.
9. The method for manufacturing the capacitor structure according to claim 8, wherein the radio frequency power used in the process of forming the second dielectric layer is 200W to 450W, and the gas flow is 100sccm to 150sccm.
10. A semiconductor structure, comprising:
a substrate;
the capacitive structure of any one of claims 1 to 5, located at a surface of the substrate.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116234429A (en) * | 2023-05-04 | 2023-06-06 | 粤芯半导体技术股份有限公司 | Capacitor structure and preparation method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060084236A1 (en) * | 2002-05-29 | 2006-04-20 | Infineon Technologies A G | Plasma-enhanced chemical vapour deposition process for depositing silicon nitride or silicon oxynitride, process for producing one such layer arrangement, and layer arrangement |
| JP2007035830A (en) * | 2005-07-26 | 2007-02-08 | Seiko Epson Corp | Element substrate manufacturing method, element substrate, electrooptical apparatus and electronic equipment |
| CN101188222A (en) * | 2006-11-21 | 2008-05-28 | 台湾积体电路制造股份有限公司 | IC and its making method |
| CN102332447A (en) * | 2011-07-28 | 2012-01-25 | 上海宏力半导体制造有限公司 | Capacitor and forming method thereof |
| CN105448886A (en) * | 2014-08-06 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Capacitor and preparation method thereof |
| CN111244039A (en) * | 2018-11-29 | 2020-06-05 | 合肥鑫晟光电科技有限公司 | Sealing structure, manufacturing method thereof and display device |
| CN111710658A (en) * | 2020-07-01 | 2020-09-25 | 华虹半导体(无锡)有限公司 | Anti-layering MIM capacitor and manufacturing method thereof |
-
2023
- 2023-02-13 CN CN202310104264.0A patent/CN115955913A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060084236A1 (en) * | 2002-05-29 | 2006-04-20 | Infineon Technologies A G | Plasma-enhanced chemical vapour deposition process for depositing silicon nitride or silicon oxynitride, process for producing one such layer arrangement, and layer arrangement |
| JP2007035830A (en) * | 2005-07-26 | 2007-02-08 | Seiko Epson Corp | Element substrate manufacturing method, element substrate, electrooptical apparatus and electronic equipment |
| CN101188222A (en) * | 2006-11-21 | 2008-05-28 | 台湾积体电路制造股份有限公司 | IC and its making method |
| CN102332447A (en) * | 2011-07-28 | 2012-01-25 | 上海宏力半导体制造有限公司 | Capacitor and forming method thereof |
| CN105448886A (en) * | 2014-08-06 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Capacitor and preparation method thereof |
| CN111244039A (en) * | 2018-11-29 | 2020-06-05 | 合肥鑫晟光电科技有限公司 | Sealing structure, manufacturing method thereof and display device |
| CN111710658A (en) * | 2020-07-01 | 2020-09-25 | 华虹半导体(无锡)有限公司 | Anti-layering MIM capacitor and manufacturing method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 冀婷: "稀土高K栅介质材料", 国防工业出版社, pages: 11 - 12 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116234429A (en) * | 2023-05-04 | 2023-06-06 | 粤芯半导体技术股份有限公司 | Capacitor structure and preparation method thereof |
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