CN115954393A

CN115954393A - Solar laminated cell and manufacturing method thereof, cell module and photovoltaic system

Info

Publication number: CN115954393A
Application number: CN202211663073.XA
Authority: CN
Inventors: 吴慧敏; 陈刚
Original assignee: Zhejiang Aiko Solar Energy Technology Co Ltd; Guangdong Aiko Technology Co Ltd; Tianjin Aiko Solar Energy Technology Co Ltd; Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
Current assignee: Zhejiang Aiko Solar Energy Technology Co Ltd; Guangdong Aiko Technology Co Ltd; Tianjin Aiko Solar Energy Technology Co Ltd; Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
Priority date: 2022-12-23
Filing date: 2022-12-23
Publication date: 2023-04-11

Abstract

The application is applicable to the technical field of solar cells, and provides a solar laminated cell, a manufacturing method thereof, a cell module and a photovoltaic system. The manufacturing method of the solar laminated cell comprises the following steps: sequentially forming a first through hole, a conductive contact structure and an emitting electrode on a silicon substrate to form a crystalline silicon bottom cell; forming a second through hole on the silicon substrate with the conductive contact structure; manufacturing a first main grid penetrating through the first through hole and a second main grid penetrating through the second through hole; manufacturing a first auxiliary grid communicated with the first main grid and a second auxiliary grid communicated with the second main grid on one side of the crystalline silicon bottom battery, which is far away from the conducting layer; sequentially manufacturing a conductive layer, a first carrier transmission layer, a light absorption layer and a second carrier transmission layer of the thin film top battery on the conductive contact structure; the first carrier transmission layer is communicated with a first main grid penetrating through the bottom cell; and manufacturing a front side auxiliary grid on the second carrier transmission layer, wherein the second carrier transmission layer and the front side auxiliary grid are communicated with a second main grid penetrating through the solar laminated cell.

Description

Solar laminated cell and manufacturing method thereof, cell module and photovoltaic system

Technical Field

The application belongs to the technical field of solar cells, and particularly relates to a solar laminated cell, a manufacturing method of the solar laminated cell, a cell module and a photovoltaic system.

Background

Solar cell power generation is a sustainable clean energy source that can convert sunlight into electrical energy using the photovoltaic effect of semiconductor p-n junctions.

The related art may stack a plurality of solar cells into a solar laminate cell. Generally, the solar cell stack adopts a sandwich structure, and a plurality of electrodes are connected in series or in parallel. However, this results in current and voltage losses. Moreover, the light receiving area of the front surface is reduced due to the extraction of the electrode on the front surface, and the short current of the thin film battery is reduced. Thus, the photoelectric conversion efficiency of the tandem cell is low.

Therefore, how to improve the photoelectric conversion efficiency of the tandem cell becomes a problem to be solved urgently.

Disclosure of Invention

The application provides a solar laminated cell, a manufacturing method thereof, a cell module and a photovoltaic system, and aims to solve the problem of how to improve the photoelectric conversion efficiency of the laminated cell.

In a first aspect, a method for manufacturing a solar cell includes:

forming a first through hole on a silicon substrate;

manufacturing a conductive contact structure and an emitter on the silicon substrate after the hole is opened to form a crystalline silicon bottom battery;

forming a second through hole on the silicon substrate with the conductive contact structure;

manufacturing a conductive layer of a thin film top battery on the conductive contact structure;

manufacturing a first main grid, wherein the first main grid penetrates through the first through hole;

manufacturing a second main grid, wherein the second main grid penetrates through the second through hole;

manufacturing a first auxiliary grid and a second auxiliary grid on one side of the crystalline silicon bottom battery, which is far away from the conducting layer, wherein the first auxiliary grid is communicated with the first main grid, and the second auxiliary grid is communicated with the second main grid;

manufacturing a first carrier transmission layer on the conductive layer, wherein the first carrier transmission layer is communicated with the first main grid, and the first main grid penetrates through the crystalline silicon bottom cell;

manufacturing a light absorption layer on the first carrier transmission layer;

manufacturing a second carrier transmission layer on the light absorption layer to form the thin film top battery;

and manufacturing a front side auxiliary grid on the second carrier transmission layer, wherein the second carrier transmission layer and the front side auxiliary grid are communicated with the second main grid, and the second main grid penetrates through the thin film top battery and the crystalline silicon bottom battery.

Optionally, opening a first via on the silicon substrate includes:

forming the first through hole on the silicon substrate by using laser;

the manufacturing method comprises the following steps:

treating the silicon substrate with the first through hole by adopting a wet alkali polishing process;

and/or, forming a second through hole on the silicon substrate with the conductive contact structure, including:

forming the second through hole on the silicon substrate with the conductive contact structure by using laser;

the manufacturing method comprises the following steps:

and treating the silicon substrate with the second through hole by adopting a wet alkali polishing process.

Optionally, fabricating a first main gate includes:

and filling and curing slurry in the first through hole, wherein the cured slurry penetrates out of the silicon substrate by a first preset thickness.

Optionally, fabricating a second main gate includes:

and filling and curing slurry in the second through hole, wherein the cured slurry penetrates out of the conductive contact structure by a first preset thickness.

Optionally, the manufacturing method includes:

and manufacturing an insulating structure at the outer side of the first main gate and/or the second main gate.

Optionally, the first carrier transport layer is an electron transport layer, the first main gate is a negative electrode main gate, the first auxiliary gate is a negative electrode auxiliary gate, the second carrier transport layer is a hole transport layer, the second main gate is a positive electrode main gate, the second auxiliary gate is a positive electrode auxiliary gate, and the positive electrode auxiliary gate is a positive electrode auxiliary gate;

the insulating structure comprises a first insulating part and a second insulating part, the insulating structure is manufactured at the outer side of the first main grid and/or the second main grid, and the insulating structure comprises:

manufacturing a first insulating part on one side of the crystalline silicon bottom battery, which is far away from the conducting layer, wherein the first insulating part is positioned between the first main grid and the second main grid;

forming a first groove on the outer side of the second main gate, wherein the first groove penetrates through the light absorption layer, the first carrier transmission layer, the conductive layer and the conductive contact structure;

and manufacturing the second insulating part in the first groove.

Optionally, the first carrier transport layer is a hole transport layer, the first main grid is an anode main grid, the first auxiliary grid is an anode auxiliary grid, the second carrier transport layer is an electron transport layer, the second main grid is a cathode main grid, the second auxiliary grid is a cathode auxiliary grid, and the front auxiliary grid is a cathode auxiliary grid;

the insulation structure comprises a first insulation piece, a third insulation piece and a fourth insulation piece, wherein the insulation structure is manufactured on the outer sides of the first main grid and the second main grid, and the insulation structure comprises:

a second groove is formed in the outer side of the second main grid and penetrates through the light absorption layer and the first carrier transmission layer;

forming a third groove on the outer side of the first main gate, wherein the third groove penetrates through the conductive layer and the conductive contact structure;

manufacturing the third insulating part in the second groove;

and manufacturing the fourth insulating part in the third groove.

In a second aspect, the present application provides a solar stacked cell, which is manufactured by using any one of the above methods for manufacturing a solar stacked cell.

In a third aspect, the present application provides a battery module including the solar tandem cell described above.

In a fourth aspect, the present application provides a photovoltaic system including the above-described cell assembly.

According to the solar laminated cell, the manufacturing method of the solar laminated cell, the cell module and the photovoltaic system, the second main grid is communicated with the front auxiliary grid and penetrates through the thin film top cell and the crystalline silicon bottom cell, so that the second main grid can be wound to the back of the solar laminated cell, the electrode is led out from the back, the light receiving area of the front of the solar laminated cell can be increased, and the short-circuit current is increased. Meanwhile, the first main grid is communicated with the first carrier transmission layer, penetrates through the crystalline silicon bottom cell and is communicated with the first auxiliary grid on the back side, and the second main grid is communicated with the front side auxiliary grid, the second carrier transmission layer and the second auxiliary grid on the back side, penetrates through the solar laminated cell and is communicated with the second auxiliary grid on the back side, so that the thin film top cell and the crystalline silicon bottom cell share the electrode, current and voltage loss in circuit conduction can be reduced, and cost can be reduced. Thus, the photoelectric conversion efficiency of the solar laminated cell is improved.

Drawings

Fig. 1 is a schematic flow chart of a method for manufacturing a solar tandem cell according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a solar cell stack according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a solar cell stack according to an embodiment of the present application;

fig. 4 is a schematic flow chart of a method for manufacturing a solar stacked cell according to an embodiment of the present application;

fig. 5 is a schematic flow chart of a method for manufacturing a solar tandem cell according to an embodiment of the present application;

fig. 6 is a schematic flow chart of a method for manufacturing a solar tandem cell according to an embodiment of the present application;

fig. 7 is a schematic flow chart of a method for manufacturing a solar tandem cell according to an embodiment of the present application;

fig. 8 is a schematic flow chart of a method for manufacturing a solar tandem cell according to an embodiment of the present application;

fig. 9 is a schematic flow chart of a method for manufacturing a solar tandem cell according to an embodiment of the present application;

fig. 10 is a schematic flow chart of a method for manufacturing a solar cell stack according to an embodiment of the present application;

description of the main element symbols:

the solar cell stack 100, the thin film top cell 10, the conductive layer 11, the first carrier transport layer 12, the light absorbing layer 13, the second carrier transport layer 14, the crystalline silicon bottom cell 20, the silicon substrate 21, the conductive contact structure 22, the tunneling oxide layer 221, the doped passivation layer 222, the first main gate 31, the second main gate 32, the front side sub-gate 33, the first insulator 41, the second insulator 42, the third insulator 43, and the fourth insulator 44.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. Examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application. Furthermore, it should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

In the description of the present application, it is to be understood that the terms "length," "width," "upper," "lower," "left," "right," "horizontal," "top," "bottom," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically, electrically or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature "on," "above" and "over" the second feature may include the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments, or examples, for implementing different features of the application. To simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Further, the present application may repeat reference numerals and/or reference letters in the various examples for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or arrangements discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art will recognize applications of other processes and/or scenarios of use of other materials.

In the application, the second main grid is communicated with the front auxiliary grid and penetrates through the thin film top cell and the crystalline silicon bottom cell, so that the second main grid can be wound on the back surface of the solar laminated cell, the electrode is led out from the back surface, the light receiving area of the front surface of the solar laminated cell can be increased, and the short-circuit current is increased. Meanwhile, the first main grid is communicated with the first carrier transmission layer, penetrates through the crystalline silicon bottom cell and is communicated with the first auxiliary grid on the back side, and the second main grid is communicated with the front side auxiliary grid, the second carrier transmission layer and the second auxiliary grid on the back side, penetrates through the solar laminated cell and is communicated with the second auxiliary grid on the back side, so that the thin film top cell and the crystalline silicon bottom cell share the electrode, current and voltage loss in circuit conduction can be reduced, and cost can be reduced. Thus, the photoelectric conversion efficiency of the solar laminated cell is improved.

Example one

Referring to fig. 1, fig. 2 and fig. 3, a method for manufacturing a solar stacked cell 100 according to an embodiment of the present disclosure includes:

step S11: forming a first through hole in the silicon substrate 21;

step S12: manufacturing a conductive contact structure 22 and an emitter on the silicon substrate 21 after the hole is opened to form a crystalline silicon bottom cell 20;

step S13: forming a second through hole in the silicon substrate 21 with the conductive contact structure 22;

step S14: fabricating the conductive layer 11 of the thin film top cell 10 on the conductive contact structure 22;

step S15: manufacturing a first main grid 31, wherein the first main grid 31 penetrates through the first through hole;

step S16: manufacturing a second main grid 32, wherein the second main grid 32 penetrates through the second through hole;

step S18: manufacturing a first auxiliary grid and a second auxiliary grid on one side of the crystalline silicon bottom cell 20, which is far away from the conducting layer 11, wherein the first auxiliary grid is communicated with the first main grid 31, and the second auxiliary grid is communicated with the second main grid 32;

step S19: manufacturing a first carrier transport layer 12 on the conductive layer 11, wherein the first carrier transport layer 12 is communicated with a first main grid 31, and the first main grid 31 penetrates through the crystalline silicon bottom cell 20;

step S20: fabricating a light absorbing layer 13 on the first carrier transporting layer 12;

step S21: manufacturing a second carrier transport layer 14 on the light absorption layer 13 to form the thin film top cell 10;

step S22: and manufacturing a front side auxiliary grid 33 on the second carrier transmission layer 14, wherein the second carrier transmission layer 14 and the front side auxiliary grid 33 are communicated with a second main grid 32, and the second main grid 32 penetrates through the thin film top cell 10 and the crystalline silicon bottom cell 20.

According to the preparation method of the solar tandem cell 100 in the embodiment of the application, the second main grid 32 is communicated with the front side auxiliary grid 33 and penetrates through the thin film top cell 10 and the crystalline silicon bottom cell 20, so that the second main grid 32 can be wound to the back side of the solar tandem cell 100, an electrode is led out from the back side, the light receiving area of the front side of the solar tandem cell 100 can be increased, and the short-circuit current is increased. Meanwhile, the first main grid 31 is communicated with the first carrier transmission layer 12, penetrates through the crystalline silicon bottom cell 20 and is communicated with the first auxiliary grid on the back side, and the second main grid 32 is communicated with the front side auxiliary grid 33, the second carrier transmission layer 14, penetrates through the solar laminated cell 100 and is communicated with the second auxiliary grid on the back side, so that the thin film top cell 10 and the crystalline silicon bottom cell 20 share electrodes, current and voltage loss in circuit conduction can be reduced, and cost can also be reduced. This is advantageous for improving the photoelectric conversion efficiency of the solar laminated cell 100.

Specifically, in step S11, the silicon substrate 21 is a P-type silicon substrate 21. In other embodiments, the silicon substrate 21 may be an N-type silicon substrate 21.

Specifically, in step S11, the number of the first through holes is plural. Further, the distance between any two adjacent first through holes is the same. In other embodiments, the pitches of some adjacent two first through holes may be the same, and the pitches of the other adjacent two first through holes are different; the distance between any two adjacent first through holes can be different. Further, all the first through holes may be regularly distributed. For example, in a matrix or in a line. Thus, the punching efficiency is higher. In other embodiments, the plurality of first through holes may be randomly distributed.

Specifically, in step S11, the silicon substrate 21 has a thickness of 50 μm to 200 μm. For example, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm.

Specifically, in step S12, the conductive contact structure 22 may be a passivation contact structure, the passivation contact structure includes a tunnel oxide layer 221 and a doped passivation layer 222, and step S12 includes: manufacturing a tunneling oxide layer 221 on the silicon substrate 21 after the hole is opened; forming an intrinsic layer on the tunneling oxide layer 221; the silicon wafer with the intrinsic layer is diffused to convert the intrinsic layer into the doped passivation layer 222, and an emitter is formed on the silicon substrate 21. Further, the tunnel oxide layer 221 may be formed by PECVD or LPCVD, and the intrinsic layer may be formed by PECVD or LPCVD. Therefore, a passivation contact structure can be efficiently manufactured, and better interface passivation and carrier selective collection are realized by using the passivation contact structure formed by the tunneling oxide layer 221 and the doped passivation layer 222, which is beneficial to improving the photoelectric conversion efficiency of the cell.

Specifically, the tunnel oxide layer 221 includes a silicon oxide layer.

Specifically, the doped passivation layer 222 comprises a doped polysilicon layer. Further, the surface doping concentration of the doped passivation layer 222 is 10E19cm ^-3 -10E21cm ^-3 . Therefore, the doping concentration is in a proper range, and the interface passivation effect is better.

Specifically, the tunnel oxide layer 221 has a thickness of 0.5nm to 3nm. For example, 0.5nm, 0.8nm, 1nm, 1.5nm, 1.8nm, 2nm, 2.5nm, 3nm. Therefore, the thickness of the tunnel oxide layer 221 is in a suitable range, which can avoid poor effect of tunnel oxidation caused by too large or too small thickness, so that the effect of tunnel oxidation is better.

Specifically, the thickness of the doped passivation layer 222 is 20nm to 300nm. Examples thereof include 20nm, 50nm, 80nm, 100nm, 150nm, 200nm, 280nm and 300nm. Therefore, the thickness of the doped passivation layer 222 is in a proper range, so that the poor interface passivation effect caused by too large or too small thickness can be avoided, and the interface passivation effect is better.

Specifically, in step S12, the conductive contact structure 22 may also be a diffusion structure. Further, the silicon substrate 21 may be directly diffused, thereby forming a diffusion structure.

Specifically, in step S13, the number of the second through holes is plural. Further, the distance between any two adjacent second through holes is the same. In other embodiments, the pitches of some adjacent two second through holes may be the same, and the pitches of the other adjacent two second through holes are different; the distance between any two adjacent second through holes can also be different. Further, all the second through holes may be regularly distributed. For example, in a matrix or in a line. Thus, the punching efficiency is higher. In other embodiments, the plurality of second through holes may be randomly distributed.

Specifically, in step S14, the conductive layer 11 may be fabricated by magnetron sputtering. The conductive layer 11 may be a transparent conductive film such as ITO or FTO. In this manner, the carrier collecting ability of the passivation contact structure and the light absorbing layer 13 can be improved.

Specifically, in step S14, the thickness of the conductive layer 11 is 15nm to 100nm. For example, 15nm, 18nm, 30nm, 50nm, 80nm, 95nm, 100nm. Thus, the thickness of the conductive layer 11 is in a proper range, so that poor conductive effect caused by too small thickness can be avoided, and material waste caused by too large thickness can also be avoided.

Specifically, in step S15, one first main gate 31 is fabricated in each first via hole. It is understood that in other embodiments, a plurality of first main gates 31 may be fabricated in each first via, or the first main gates 31 may be fabricated in only a portion of the first vias.

Specifically, in step S15, the first main gate 31 may fill the first through hole, and an insulating structure is disposed outside the first main gate 31 to insulate the first main gate 31 from a film layer that needs to be insulated. In other embodiments, the first main gate 31 may also form a gap with the inner wall of the first through hole, and the first main gate 31 is insulated from the film layer to be insulated by the gap.

Specifically, in step S16, one second main gate 32 is fabricated in each second via. It is understood that in other embodiments, a plurality of second main gates 32 may be formed in each second via, or only a portion of the second main gates 32 may be formed in the second vias.

Specifically, in step S16, the second main gate 32 may fill the second through hole, and an insulating structure is disposed outside the second main gate 32 to insulate the second main gate 32 from a film layer that needs to be insulated. In other embodiments, the second main gate 32 may also form a gap with the inner wall of the second through hole, and the second main gate 32 is insulated from the film layer to be insulated by the gap.

Specifically, in step S18, a groove may be formed in a side of the crystalline silicon bottom cell 20 away from the conductive layer 11, and the conductive contact structure 22 and the emitter in the groove region may be removed; and manufacturing positive auxiliary grids in the first auxiliary grid and the second auxiliary grid in the grooved area, and manufacturing negative auxiliary grids in the first auxiliary grid and the second auxiliary grid in the non-grooved area. In this way, the PN junction can be isolated by removing the conductive contact structure 22 and the emitter in a partial region by using the trench.

Furthermore, after slotting and before manufacturing the first and second auxiliary grids, the phosphosilicate glass formed by diffusion can be used as a protective layer in the non-slotted area, and the phosphosilicate glass is polished and removed in an alkali polishing slot and then removed by acid cleaning.

Further, the width of the groove is 100nm-300nm. Examples thereof include 100nm, 120nm, 150nm, 200nm, 250nm and 300nm.

Specifically, in step S18, the negative electrode sub-grid may be made using silver paste. In other embodiments, the negative electrode subgrid may also be made of one or more of aluminum paste, gold paste, titanium paste, and copper paste.

Specifically, in step S18, the width of the anode subgrid is 30nm to 70nm. For example, 30nm, 40nm, 50nm, 60nm, and 70nm.

Specifically, in step S18, the positive electrode sub-grid may be made using aluminum paste. In other embodiments, the positive electrode sub-grid can also be made of one or more of silver paste, gold paste, titanium paste and copper paste.

Specifically, in step S18, the width of the positive electrode sub-gate is 70nm to 250nm. For example, 70nm, 100nm, 150nm, 200nm, and 250nm.

Specifically, in the example of fig. 2, the first carrier transport layer 12 is an electron transport layer, and the second carrier transport layer 14 is a hole transport layer. In the example of fig. 3, the first carrier transport layer 12 is a hole transport layer and the second carrier transport layer 14 is an electron transport layer.

Further, zinc oxide (ZnO), titanium dioxide (TiO) and the like can be used as the electron transport layer ₂ ) Tin dioxide (SnO) ₂ ) One or more of (a).

Further, the thickness of the electron transport layer is 2nm to 400nm. For example, 2nm, 4nm, 80nm, 100nm, 200nm, 380nm, 400nm. Therefore, the thickness of the electron transmission layer is in a proper range, poor electron transmission effect caused by too large or too small thickness can be avoided, and the electron transmission effect is good. Preferably, the thickness of the electron transport layer is from 25nm to 400nm.

Further, as the hole transport layer, nickel oxide (NiOx), molybdenum oxide (MoOx), vanadium pentoxide (V) can be used ₂ Ox) is selected.

Further, the thickness of the hole transport layer is 2nm to 400nm. For example, 2nm, 4nm, 80nm, 100nm, 200nm, 380nm, 400nm. Therefore, the thickness of the hole transport layer is in a proper range, poor hole transport effect caused by too large or too small thickness can be avoided, and the hole transport effect is good.

Specifically, the electron transport layer can be fabricated using a magnetron sputtering method. It is understood that in other embodiments, the electron transport layer may be fabricated using PECVD or other means.

Specifically, the hole transport layer may be fabricated using an evaporation deposition method. It is understood that in other embodiments, the hole transport layer may be formed by PECVD or other methods.

Specifically, in step S20, the light absorbing layer 13 may be prepared by a two-step evaporation method.

Specifically, in step S20, the light absorbing layer 13 is a perovskite absorbing layer. Further, the titanium ore absorption layer can be a single crystal perovskite absorption layer and can also be a polycrystalline perovskite absorption layer. Further, the perovskite absorption layer has a crystal structure of ABX ₃ Type A is Cs ⁺ 、CH(NH ₂ ) ₂ ⁺ 、CH ₃ NH ₃ ⁺ 、C(NH ₂ ) ₃ ⁺ B is Pb ²⁺ 、Sn ²⁺ At least one of (1), X is Br ^- 、I ^- 、Cl ^- One or more of (a). Therefore, the light absorption effect of the perovskite absorption layer is good, and the photoelectric conversion efficiency is improved.

It is understood that in other embodiments, the light absorbing layer 13 may also be a silicon ferrous oxide absorbing layer, a copper indium gallium selenide absorbing layer, a microcrystalline silicon absorbing layer, a nanocrystalline silicon absorbing layer, an indium phosphide absorbing layer, an amorphous silicon absorbing layer, a gallium arsenide absorbing layer, or a cadmium telluride absorbing layer.

Specifically, the light absorbing layer 13 has a thickness of 0.5 μm to 3 μm. For example, 0.5. Mu.m, 0.6. Mu.m, 0.8. Mu.m, 1. Mu.m, 1.5. Mu.m, 1.7. Mu.m, 2. Mu.m, 2.5. Mu.m, 3 μm. Therefore, the thickness of the light absorption layer 13 is in a proper range, poor light absorption effect caused by too large or too small thickness can be avoided, and material waste caused by too large thickness can also be avoided.

Specifically, in step S22, the front side sub-gate 33 may be fabricated on the second carrier transport layer 14 according to the second main gate 32 using a screen printing process.

Specifically, the manufacturing method may further include: a surface passivation layer is made on the side of the crystalline silicon bottom cell 20 facing away from the conductive layer 11. Therefore, the reflection of the cell to sunlight can be reduced, more sunlight can be absorbed to excite more electrons and holes, the cell can be protected, the service life of the cell can be prolonged, recombination centers can be reduced, and the passivation effect can be achieved. Meanwhile, the surface passivation layer may also insulate the first and second

main gates

31 and 32.

Further, the surface passivation layer may be fabricated using PECVD or PEALD.

Further, the thickness of the surface passivation layer is 30nm-130nm. For example, 30nm, 50nm, 80nm, 90nm, 100nm, 120nm, and 130nm. Therefore, the thickness of the surface passivation layer is in a proper range, and the surface passivation effect is good.

Further, the surface passivation layer includes a silicon oxide layer and a silicon nitride layer. The thickness of the silicon oxide layer is 5nm to 20nm, for example, 5nm, 6nm, 10nm, 15nm, or 20nm. The thickness of the silicon nitride layer is 60nm to 110nm, such as 60nm, 65nm, 70nm, 100nm, 110nm. Thus, the solar cell 100 can be protected and antireflection can be achieved, which is beneficial to improving photoelectric conversion efficiency.

Note that in fig. 1, steps S11 to S22 are performed sequentially. However, in other embodiments, the steps S11 to S12 may be performed in other orders, or some of the steps may be performed together. For example, step S14 may be performed before step S15, or may be performed after step S19; for another example, step S15 and step S16 may be executed in steps or synchronously. That is, the sequence numbers of the steps and the drawings herein do not represent a limitation on the execution order of the steps, and can be appropriately adjusted.

Example two

Referring to fig. 4, in some alternative embodiments, step S11 includes:

step S111: forming a first through hole in the silicon substrate 21 by using laser;

the manufacturing method comprises the following steps:

step S112: and processing the silicon substrate 21 with the first through hole by adopting a wet alkali polishing process.

Therefore, the first through hole can be efficiently formed by using laser, the first main gate 31 which is wound through can be conveniently manufactured subsequently, laser damage can be removed by using alkali liquor, the silicon substrate 21 can be polished, and the subsequent structure can be conveniently manufactured.

Specifically, in step S112, the alkali solution is, for example, KOH solution.

Referring to fig. 5, in some alternative embodiments, step S13 includes:

step S131: forming a second through hole on the silicon substrate 21 with the conductive contact structure 22 by using laser;

the manufacturing method comprises the following steps:

step S132: and processing the silicon substrate 21 provided with the second through hole by adopting a wet alkali polishing process.

Therefore, the second through hole can be efficiently formed by using laser, so that the second main gate 32 which is wound through can be conveniently manufactured subsequently, laser damage can be removed by using alkali liquor, the silicon substrate 21 can be polished, and the subsequent structure can be conveniently manufactured.

Specifically, in step S132, the alkali solution is, for example, KOH solution.

EXAMPLE III

Referring to fig. 6, in some alternative embodiments, step S15 includes:

step S151: and filling and curing the slurry in the first through hole, wherein the cured slurry penetrates out of the silicon substrate 21 by a first preset thickness.

Thus, the first main gate 31 is disposed through the first through hole and penetrates out of the silicon substrate 21, so that the first main gate 31 is conveniently conducted with the first carrier transport layer 12 manufactured subsequently.

Specifically, the paste includes silver paste. It is understood that in other embodiments, the slurry may be one or more of aluminum slurry, gold slurry, titanium slurry, and copper slurry.

Specifically, the first preset thickness is 20nm-500nm. For example, 20nm, 25nm, 100nm, 250nm, 300nm, or 500nm. Therefore, the thickness of the first main gate 31 penetrating out is in a proper range, the first main gate 31 cannot be conducted with the first carrier transport layer 12 manufactured subsequently due to the fact that the thickness is too small can be avoided, and material waste and interference to other structures manufactured subsequently due to the fact that the thickness is too large can be avoided.

It is understood that in other embodiments, after the thin film top cell 10 and the crystalline silicon bottom cell 20 are fabricated, a first through hole is formed, and then the first main gate 31 is fabricated in the first through hole.

Example four

Referring to fig. 7, in some alternative embodiments, step S16 includes:

step S161: and filling and curing the slurry in the second through hole, wherein the cured slurry penetrates out of the conductive contact structure 22 by a second preset thickness.

In this way, the second main gate 32 penetrates through the second through hole and penetrates out of the conductive contact structure 22, so that the second main gate 32 is conveniently conducted with the front sub-gate 33 and the second carrier transport layer 14 which are manufactured subsequently.

Specifically, the paste includes aluminum paste. It is understood that in other embodiments, the paste may be one or more of silver paste, gold paste, titanium paste, and copper paste.

Specifically, the second preset thickness is 550nm-3500nm. Examples thereof include 550nm, 600nm, 1000nm, 2000nm, 2800nm and 3500nm. Therefore, the thickness of the second main grid 32 penetrating out is in a proper range, the second main grid 32 cannot be conducted with the front side sub-grid 33 and the second carrier transport layer 14 which are manufactured subsequently due to the fact that the thickness is too small can be avoided, and material waste and interference to other structures which are manufactured subsequently due to the fact that the thickness is too large can be avoided.

It is understood that in other embodiments, after the thin film top cell 10 and the crystalline silicon bottom cell 20 are fabricated, a second through hole is formed, and then the second main gate 32 is fabricated in the second through hole.

EXAMPLE five

Referring to fig. 8, in some alternative embodiments, the manufacturing method includes:

step S17: an insulating structure is fabricated outside the first main gate 31 and/or the second main gate 32.

In this way, the first main gate 31 and the second main gate 32 can be connected to the same polarity film or structure and insulated from the different polarity film or structure by using the insulating structure. Thus, short circuit can be avoided, and normal operation of the solar tandem cell 100 can be ensured.

It is understood that in other embodiments, a void may be formed outside the first main gate 31 and/or the second main gate 32, and insulation may be performed using the void.

Example six

Referring to fig. 2 and 9, in some alternative embodiments, the first carrier transport layer 12 is an electron transport layer, the first main grid 31 is a negative main grid, the first sub-grid is a negative sub-grid, the second carrier transport layer 14 is a hole transport layer, the second main grid 32 is a positive main grid, the second sub-grid is a positive sub-grid, and the front sub-grid 33 is a positive sub-grid;

the insulating structure includes a first insulating member 41 and a second insulating member 42, and step S17 includes:

step S171: manufacturing a first insulating part 41 on one side of the crystal silicon bottom cell 20, which is far away from the conducting layer 11, wherein the first insulating part 41 is positioned between the first main grid 31 and the second main grid 32;

step S172: a first groove is formed in the outer side of the second main grid 32, and penetrates through the light absorption layer 13, the first carrier transmission layer 12, the conductive layer 11 and the conductive contact structure 22;

step S173: a second insulator 42 is formed in the first recess.

In this way, the first main grid 31 and the second main grid 32 can be insulated by the first insulating member 41, and the second main grid 32 is ensured to be connected with the positive polarity film layer or structure and insulated from the negative polarity film layer or structure by the second insulating member 42. Thus, short circuit can be avoided, and normal operation of the solar tandem cell 100 can be ensured.

The negative first main grid 31 is connected to the electron transport layer, penetrates through the crystalline silicon bottom cell 20 and is connected to the negative first sub-grid on the back side, and the positive second main grid 32 and the positive front sub-grid 33 are connected to the hole transport layer, penetrates through the solar stacked cell 100 and is connected to the positive second sub-grid on the back side. Thus, the thin film top cell 10 and the crystalline silicon bottom cell 20 share the electrode, which can reduce current and voltage loss in circuit conduction and also reduce cost.

Specifically, the first insulating member 41 may be a partial region or a whole region of the surface passivation layer, and the first insulating member 41 may also be other structures independent of the surface passivation layer.

Specifically, a first groove may be formed using laser, the first groove surrounding the second main grid 32. Further, the width of the first groove is 200nm-1000nm. For example, 200nm, 250nm, 300nm, 500nm, 800nm, 1000nm.

Specifically, the second insulator 42 includes one or more of a ceramic insulator, a silicon oxide insulator, a polystyrene insulator, and an epoxy plastic insulator.

Specifically, the second insulating member 42 is continuously distributed outside the second main grid 32. Therefore, the insulation is continuous without leak, and the insulation effect is better.

EXAMPLE seven

Referring to fig. 3 and 10, in some alternative embodiments, the first carrier transport layer 12 is a hole transport layer, the first main gate 31 is a positive main gate, the first sub-gate is a positive sub-gate, the second carrier transport layer 14 is an electron transport layer, the second main gate 32 is a negative main gate, the second sub-gate is a negative sub-gate, and the front sub-gate 33 is a negative sub-gate;

the insulation structure includes a first insulation member 41, a third insulation member 43, and a fourth insulation member 44, and step S17 includes:

step S174: manufacturing a first insulating part 41 on one side of the crystal silicon bottom cell 20, which is far away from the conducting layer 11, wherein the first insulating part 41 is positioned between the first main grid 31 and the second main grid 32;

step S175: a second groove is formed in the outer side of the second main grid 32, and penetrates through the light absorption layer 13 and the first carrier transmission layer 12;

step S176: a third groove is formed in the outer side of the first main grid 31, and the third groove penetrates through the conductive layer 11 and the conductive contact structure 22;

step S177: making a third insulator 43 in the second groove;

step S178: a fourth insulator 44 is made in the third groove.

In this way, the first main gate 31 and the second main gate 32 may be insulated by the first insulating member 41, the second main gate 32 is ensured to be interconnected with the negative polarity film layer or structure and insulated from the positive polarity film layer or structure by the third insulating member 43, and the first main gate 31 is ensured to be interconnected with the positive polarity film layer or structure and insulated from the negative polarity film layer or structure by the fourth insulating member 44. Thus, short circuit can be avoided, and normal operation of the solar tandem cell 100 can be ensured.

The positive first main gate 31 is connected to the hole transport layer, penetrates the crystalline silicon bottom cell 20, and is connected to the back positive first sub-gate, and the negative second main gate 32 and the negative front sub-gate 33 are connected to the electron transport layer, and is connected to the back negative second sub-gate, and is connected to the solar cell 100. Thus, the thin film top cell 10 and the crystalline silicon bottom cell 20 share the electrode, which can reduce current and voltage loss in circuit conduction and also reduce cost.

Specifically, the first insulating member 41 may be a partial region or a whole region of the surface passivation layer, and the first insulating member 41 may also be another structure independent of the surface passivation layer.

In particular, a second groove may be laser-drilled, which surrounds the second main grid 32. Further, the width of the second groove is 200nm-1000nm. For example, 200nm, 250nm, 300nm, 500nm, 800nm, 1000nm.

Specifically, the third insulator 43 includes one or more of a ceramic insulator, a silicon oxide insulator, a polystyrene insulator, and an epoxy plastic insulator.

In particular, the third insulating members 43 are continuously distributed outside the second main grid 32. Therefore, the insulation is continuous without leak, and the insulation effect is better.

In particular, a third groove may be opened by laser, the third groove surrounding the first main grating 31. Further, the width of the third groove is 200nm-1000nm. For example, 200nm, 250nm, 300nm, 500nm, 800nm, 1000nm.

Specifically, the fourth insulator 44 includes one or more of a ceramic insulator, a silicon oxide insulator, a polystyrene insulator, and an epoxy plastic insulator.

Specifically, the fourth insulating member 44 is continuously distributed outside the first main grid 31. Therefore, the insulation is continuous without leak, and the insulation effect is better.

Example eight

The solar tandem cell 100 according to the embodiment of the present application is manufactured by the method for manufacturing the solar tandem cell 100 according to any one of the first to seventh embodiments.

In the solar tandem cell 100 of the embodiment of the application, the second main grid 32 is communicated with the front side auxiliary grid 33 and penetrates through the thin film top cell 10 and the crystalline silicon bottom cell 20, so that the second main grid 32 can be wound to the back side of the solar tandem cell 100, an electrode is led out from the back side, the light receiving area of the front side of the solar tandem cell 100 can be increased, and the short-circuit current is increased. Meanwhile, the first main grid 31 is communicated with the first carrier transmission layer 12, penetrates through the crystalline silicon bottom cell 20 and is communicated with the first auxiliary grid on the back side, and the second main grid 32 is communicated with the front side auxiliary grid 33, the second carrier transmission layer 14, penetrates through the solar laminated cell 100 and is communicated with the second auxiliary grid on the back side, so that the thin film top cell 10 and the crystalline silicon bottom cell 20 share electrodes, current and voltage loss in circuit conduction can be reduced, and cost can also be reduced. This is advantageous for improving the photoelectric conversion efficiency of the solar laminated cell 100.

Example nine

The cell module according to the embodiment of the present application includes the solar tandem cell 100 according to the eighth embodiment.

In the cell module according to the embodiment of the application, in the solar tandem cell 100, the second main grid 32 is communicated with the front side auxiliary grid 33 and penetrates through the thin film top cell 10 and the crystalline silicon bottom cell 20, so that the second main grid 32 can be wound to the back side of the solar tandem cell 100, an electrode can be led out from the back side, the light receiving area of the front side of the solar tandem cell 100 can be increased, and the short-circuit current can be increased. Meanwhile, the first main grid 31 is communicated with the first carrier transmission layer 12, penetrates through the crystalline silicon bottom cell 20 and is communicated with the first auxiliary grid on the back side, and the second main grid 32 is communicated with the front side auxiliary grid 33, the second carrier transmission layer 14, penetrates through the solar laminated cell 100 and is communicated with the second auxiliary grid on the back side, so that the thin film top cell 10 and the crystalline silicon bottom cell 20 share electrodes, current and voltage loss in circuit conduction can be reduced, and cost can also be reduced. This is advantageous for improving the photoelectric conversion efficiency of the solar laminated cell 100.

In the embodiment, a plurality of solar tandem cells 100 in the cell module may be sequentially connected in series to form a cell string, so as to implement a series bus output of current, for example, the series connection of the cells may be implemented by providing solder strips (bus bars, interconnection bars), a conductive back plate, and the like.

It is understood that in such embodiments, the cell assembly may further include a metal frame, a backsheet, a photovoltaic glass, and an adhesive film. The adhesive film may be filled between the front side and the back side of the solar laminated cell 100, the photovoltaic glass, the adjacent cell sheets, and the like, and as the filler, the adhesive film may be a transparent colloid with good light transmittance and aging resistance, for example, the adhesive film may be an EVA adhesive film or a POE adhesive film, which may be specifically selected according to actual situations, and is not limited herein.

The photovoltaic glass may be an ultra-white glass, which has high light transmittance, high transparency, and excellent physical, mechanical, and optical properties, for example, the light transmittance of the ultra-white glass may reach more than 92%, which may protect the solar tandem cell 100 without affecting the efficiency of the solar tandem cell 100 as much as possible. Meanwhile, the adhesive film can bond the photovoltaic glass and the solar laminated cell 100 together, and the existence of the adhesive film can seal, insulate, prevent water and prevent moisture for the solar laminated cell 100.

The back plate can be attached to an adhesive film on the back surface of the solar laminated cell 100, the back plate can protect and support the solar laminated cell 100, and has reliable insulation, water resistance and aging resistance, the back plate can be selected from multiple materials, and can be generally toughened glass, organic glass, an aluminum alloy TPT composite adhesive film and the like, and the back plate can be specifically arranged according to specific conditions, and is not limited herein. The whole of the back sheet, the solar tandem cell 100, the adhesive film and the photovoltaic glass can be disposed on a metal frame, which serves as a main external support structure of the whole cell module and can stably support and mount the cell module, for example, the cell module can be mounted at a position where the cell module is required to be mounted through the metal frame.

EXAMPLE ten

The photovoltaic system of this application embodiment includes the battery module of example nine.

In the photovoltaic system of the embodiment of the application, in the solar tandem cell 100, the second main grid 32 is communicated with the front side auxiliary grid 33 and penetrates through the thin film top cell 10 and the crystalline silicon bottom cell 20, so that the second main grid 32 can be wound to the back side of the solar tandem cell 100, an electrode is led out from the back side, the light receiving area of the front side of the solar tandem cell 100 can be increased, and the short-circuit current is increased. Meanwhile, the first main grid 31 is communicated with the first carrier transmission layer 12, penetrates through the crystalline silicon bottom cell 20 and is communicated with the first sub-grid on the back, and the second main grid 32 is communicated with the front sub-grid 33, the second carrier transmission layer 14, penetrates through the solar laminated cell 100 and is communicated with the second sub-grid on the back, so that the thin film top cell 10 and the crystalline silicon bottom cell 20 share an electrode, current and voltage loss in circuit transmission can be reduced, and cost can be reduced. This is advantageous for improving the photoelectric conversion efficiency of the solar laminated cell 100.

In this embodiment, the photovoltaic system can be applied to a photovoltaic power station, such as a ground power station, a roof power station, a surface power station, etc., and can also be applied to a device or apparatus that generates electricity by using solar energy, such as a user solar power supply, a solar street lamp, a solar car, a solar building, etc. Of course, it is understood that the application scenario of the photovoltaic system is not limited thereto, that is, the photovoltaic system can be applied in all fields requiring solar energy for power generation. Taking a photovoltaic power generation system network as an example, a photovoltaic system may include a photovoltaic array, a combiner box and an inverter, the photovoltaic array may be an array combination of a plurality of battery modules, for example, the plurality of battery modules may constitute a plurality of photovoltaic arrays, the photovoltaic array is connected to the combiner box, the combiner box may combine currents generated by the photovoltaic array, and the combined currents are converted into alternating currents required by a utility grid through the inverter and then are connected to the utility grid to realize solar power supply.

In the description herein, references to the description of the terms "some embodiments," "exemplary embodiments," "examples," "specific examples," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiments or examples is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In addition, the above description is only a preferred embodiment of the present application, and should not be taken as limiting the present application, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method for manufacturing a solar laminated cell is characterized by comprising the following steps:

forming a first through hole on a silicon substrate;

manufacturing a light absorption layer on the first carrier transmission layer;

2. The method of claim 1, wherein the forming the first via hole in the silicon substrate comprises:

forming the first through hole on the silicon substrate by using laser;

the manufacturing method comprises the following steps:

and/or, forming a second through hole on the silicon substrate on which the conductive contact structure is formed, wherein the second through hole comprises:

the manufacturing method comprises the following steps:

and treating the silicon substrate provided with the second through hole by adopting a wet alkali polishing process.

3. The method for manufacturing a solar laminated cell according to claim 1, wherein the manufacturing of the first main grid comprises:

4. The method for manufacturing a solar laminated cell according to claim 1, wherein the manufacturing of the second main grid comprises:

5. The method of claim 1, comprising:

6. The method according to claim 5, wherein the first carrier transport layer is an electron transport layer, the first main grid is a negative main grid, the first sub-grid is a negative sub-grid, the second carrier transport layer is a hole transport layer, the second main grid is a positive main grid, the second sub-grid is a positive sub-grid, and the front sub-grid is a positive sub-grid;

the insulation structure comprises a first insulation part and a second insulation part, the insulation structure is manufactured on the outer side of the first main grid and/or the second main grid, and the insulation structure comprises:

a first groove is formed in the outer side of the second main grid and penetrates through the light absorption layer, the first carrier transmission layer, the conducting layer and the conducting contact structure;

and manufacturing the second insulating part in the first groove.

7. The method according to claim 5, wherein the first carrier transport layer is a hole transport layer, the first main grid is a positive main grid, the first sub-grid is a positive sub-grid, the second carrier transport layer is an electron transport layer, the second main grid is a negative main grid, the second sub-grid is a negative sub-grid, and the front sub-grid is a negative sub-grid;

the insulation structure comprises a first insulation piece, a third insulation piece and a fourth insulation piece, the insulation structure is manufactured on the outer sides of the first main grid and the second main grid, and the insulation structure comprises:

forming a second groove on the outer side of the second main gate, wherein the second groove penetrates through the light absorption layer and the first carrier transmission layer;

manufacturing the third insulating part in the second groove;

and manufacturing the fourth insulating part in the third groove.

8. A solar laminated cell, characterized by being manufactured by the method for manufacturing a solar laminated cell according to any one of claims 1 to 7.

9. A cell module comprising the solar cell laminate according to claim 8.

10. A photovoltaic system comprising the cell assembly of claim 9.