CN115954267A

CN115954267A - 3D NAND wafer cutting process

Info

Publication number: CN115954267A
Application number: CN202310041476.9A
Authority: CN
Inventors: 张力; 李子悦; 何洪文
Original assignee: Hefei Peidun Storage Technology Co ltd
Current assignee: Hefei Peidun Storage Technology Co ltd
Priority date: 2023-01-12
Filing date: 2023-01-12
Publication date: 2023-04-11

Abstract

The invention discloses a 3D NAND wafer cutting process, and relates to the technical field of wafer cutting; the method comprises the following steps: taking a wafer to be processed, wherein the back surface of the wafer is a silicon substrate, and the front surface of the wafer is a circuit layer; the front surface of the wafer is provided with a plurality of cutting channels for grain separation; pasting a glass carrier plate 1 on a circuit layer on the front surface of a wafer; thinning the wafer silicon substrate; a layer of adhesive film is pressed on the glass carrier plate 2 in advance, and the silicon substrate is pressed on the adhesive film; removing the glass carrier plate 1; and coating photoresist on the surface of the wafer by using a photoetching process, exposing and developing. The invention is innovated aiming at the process flow, and realizes the wafer cutting of the circuit layer with the super-thick surface by using wet etching and dry etching technologies; because the carrier plate is used for supporting, the thickness of the wafer can be reduced to the limit theoretically, for example, the thickness of a silicon substrate is reduced to 10um; the minimum 30um limit thickness of the wafer grinding and thinning process is thinner than that of the conventional wafer grinding and thinning process.

Description

3D NAND wafer cutting process

Technical Field

The invention relates to the technical field of wafer cutting, in particular to a 3D NAND wafer cutting process.

Background

More and more stacks for 3D NAND, the circuit layers are thicker and thicker. The existing 3D NAND is generally provided with 128 layers, the thickness of a surface metal layer reaches 10-15 um, and the production can be carried out by adopting a laser grooving cutting mode or a laser back invisible cutting mode. The number of stacked layers will be more and more in the future, when 300 layers or even 400 layers are stacked, the thickness of a circuit layer is expected to reach 15-30 um, the existing schemes cannot be applied, and a method suitable for cutting the thicker circuit layer needs to be found;

the existing wafer cutting technical scheme is generally as follows:

1. and cutting by a blade. It is common to use a diamond saw blade (grinding wheel) to scribe and physically separate the wafer into individual grains.

2. And (5) laser cutting. The method is generally divided into three modes of laser front-surface grooving cutting, front-surface penetrating cutting and back-surface invisible cutting.

2.1 laser front grooving cutting, cutting a groove with the depth of about 1/4-1/5 of the thickness of the wafer on a wafer cutting channel, and then cutting and separating by a blade to obtain crystal grains.

2.3 laser front side through cutting, i.e. directly cutting through the whole wafer thickness by laser and separating to obtain crystal grains. This method requires a large scribe line width, requires a large amount of energy, and requires a long time.

2.4 laser back invisible cutting, wherein laser is projected through a silicon layer on the back of a wafer for cutting, the silicon layer is concealed and cracked by focusing on a modified layer formed at a specific height, and then the modified layer is pulled and cracked by grinding and low-temperature expansion, so that the effect of separating crystal grains is achieved. According to the scheme, when the wafer is manufactured, a protective layer is specially set in the internal circuit of the wafer, and the internal transistor circuit is prevented from being damaged by laser scattering of the Si silicon substrate layer when laser is cut from the back side.

And 3, plasma cutting. The silicon layer is generally dry etched by gas, and it is required that no metal layer or specific pattern remains on the scribe line.

Disclosure of Invention

The invention aims to solve the defects in the prior art and provides a 3D NAND wafer cutting process.

In order to achieve the purpose, the invention adopts the following technical scheme:

A3D NAND wafer cutting process comprises the following steps:

s1: taking a wafer to be processed, wherein the back surface of the wafer is a silicon substrate, and the front surface of the wafer is a circuit layer; the front surface of the wafer is provided with a plurality of cutting channels for grain separation;

s2: pasting a glass carrier plate 1 on a circuit layer on the front surface of a wafer;

s3: thinning the wafer silicon substrate;

s4: a layer of adhesive film is pressed on the glass carrier plate 2 in advance, and the silicon substrate is pressed on the adhesive film;

s5: removing the glass carrier plate 1;

s6: coating photoresist on the surface of the wafer by using a photoetching process, exposing and developing;

s7: then removing the metal layer of the cutting channel by wet etching to expose the silicon substrate;

s8: removing the silicon substrate in the cutting path area through dry etching;

s9: the adhesive film is separated by a blade with a proper width.

Preferably: in the step S1, the thickness of the silicon substrate on the back surface of the wafer is between 700 and 800um, and the thickness of the circuit layer on the front surface of the wafer is 2 to 30um.

Further: in the step S3, the thinning treatment mode is to carry out coarse grinding and fine grinding on the silicon substrate through mechanical grinding, and the silicon substrate is ground to the specified thickness of 10-100um.

Further preferably: in the step S4, the adhesive film is of a double-layer structure, and the double-layer structure comprises a base material and an adhesive layer.

As a preferable aspect of the present invention: in the step S5, the manner of removing the glass carrier plate 1 is as follows: laser dispergation or heating dispergation.

Further preferred as the invention: in the step S8, the thickness of the silicon substrate in the cutting path area is between 10 and 40 um.

As a still further scheme of the invention: in the step S9, the width of the adopted blade is less than or equal to 80% of the width of the cutting channel.

On the basis of the scheme: and after the step S7 is finished, if the thickness of the silicon substrate is larger than 40um, directly cutting through the silicon substrate and the bonding film by using a blade.

On the basis of the foregoing scheme, it is preferable that: and replacing the glass carrier plate with a silicon carrier plate.

The invention has the beneficial effects that:

1. the invention is innovated aiming at the process flow, and realizes the wafer cutting of the circuit layer with the super-thick surface by using wet etching and dry etching technologies; because the carrier plate is used for supporting, the thickness of the wafer can be reduced to the limit theoretically, for example, the thickness of the silicon substrate is reduced to 10um; the minimum 30um limit thickness is thinner than the prior conventional wafer grinding and thinning process.

2. The invention avoids the problems of knife breakage and front face breakage caused by only adopting a blade for cutting.

3. The method does not need to adopt the traditional laser grooving cutting, and avoids the problem that the grains are cracked randomly when the residual metal layer is cut by a subsequent blade.

4. The invention does not adopt laser front penetration cutting, thereby avoiding the damage to the chip easily caused by heat.

5. The wafer internal circuit of the invention does not need to set a special protective layer to prevent the laser scattering of the silicon layer from damaging the internal transistor circuit when the laser is cut from the back; the design and production cost of at least 1 layer of photomask on the wafer can be reduced.

Drawings

Fig. 1 is a schematic view of a wafer structure at step S1 in a 3D NAND wafer dicing process according to the present invention;

fig. 2 is a schematic view of a wafer substrate thinning processing structure at step S2 in the 3D NAND wafer dicing process according to the present invention;

FIG. 3 is a schematic structural diagram illustrating a silicon substrate laminated on an adhesive film in a 3D NAND wafer dicing process according to the present invention;

fig. 4 is a schematic structural diagram of removing the glass carrier 1 after performing laser de-gluing or heating on the glass carrier 1 in the 3D NAND wafer cutting process according to the present invention;

fig. 5 is a schematic structural diagram of the processing in steps S6 and S7 in the 3D NAND wafer dicing process according to the present invention;

fig. 6 is a schematic structural diagram of a silicon substrate in a dicing street region removed by dry etching in a 3D NAND wafer dicing process according to the present invention;

fig. 7 is a schematic structural diagram illustrating a structure in which an adhesive film is separated by a blade in a 3D NAND wafer dicing process according to the present invention.

Detailed Description

The technical solution of the present patent will be described in further detail with reference to the following embodiments.

Example 1:

A3D NAND wafer cutting process comprises the following steps:

s1: taking a wafer to be processed, wherein the back surface of the wafer is a silicon substrate, and the front surface of the wafer is a circuit layer; as shown in fig. 1, the front surface of the wafer is provided with a plurality of cutting streets for separating the crystal grains; various testing pads are generally designed on the cutting path for monitoring the stability of the FAB process flow;

s3: the wafer silicon substrate is thinned, so that the packaging volume of a chip can be reduced and the heat dissipation can be increased if the wafer silicon substrate is ultrathin, and the subsequent packaging process is facilitated;

s5: removing the glass carrier plate 1;

s7: then, removing the metal layer of the cutting channel by wet etching, and exposing the silicon substrate as shown in fig. 5;

s8: removing the silicon substrate in the scribe line region by dry etching, as shown in fig. 6; the method is generally applicable to the condition that the silicon substrate is relatively thin;

s9: the adhesive film is separated by a blade with a proper width.

In the step S1, the thickness of the silicon substrate on the back side of the wafer is usually between 700-800um, and the thickness of the circuit layer on the front side of the wafer is 2-30um.

In the step S3, the thinning treatment mode is to carry out rough grinding and fine grinding on the silicon substrate through mechanical grinding, and the silicon substrate is ground to the specified thickness of 10-100um.

In the step S4, the adhesive film has a double-layer structure, and the double-layer structure includes a substrate and an adhesive layer.

In the step S5, the manner of removing the glass carrier plate 1 is as follows: laser dispergation or heating dispergation.

In the step S8, the thickness of the silicon substrate in the cutting path area is between 10 and 40 um.

In the step S9, the width of the adopted blade is less than or equal to 80% of the width of the cutting street.

After the step S7 is completed, if the silicon substrate is thicker than 40um, the blade can be directly used to cut through the silicon substrate and the adhesive film, so that the appearance of the front circuit is not affected, and the front circuit layer is not cracked.

Example 2:

A3D NAND wafer cutting process comprises the following steps:

s1: taking a wafer to be processed, wherein the back surface of the wafer is a silicon substrate, and the front surface of the wafer is a circuit layer; as shown in fig. 1, the front surface of the wafer is provided with a plurality of cutting streets for separating the crystal grains; a plurality of test pads are generally designed on the cutting path for monitoring the stability of the FAB process flow;

s2: pasting a silicon carrier plate 1 on a circuit layer on the front surface of a wafer;

s4: a layer of adhesive film is pressed on the silicon carrier plate 2 in advance, and the silicon substrate is pressed on the adhesive film;

s5: removing the silicon carrier plate 1;

s7: then removing the metal layer of the cutting channel by wet etching, as shown in FIG. 5, exposing the silicon substrate;

s9: the adhesive film is separated by a blade with a proper width.

In the step S1, the thickness of the silicon substrate on the back side of the wafer is further defined to be 740 to 760 um.

In the step S5, the manner of removing the silicon carrier 1 is as follows: laser dispergation or heating dispergation.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.

Claims

1. A3D NAND wafer cutting process is characterized by comprising the following steps:

s3: thinning the wafer silicon substrate;

s5: removing the glass carrier plate 1;

s9: the adhesive film is separated by a blade with a proper width.

2. The 3D NAND wafer cutting process as claimed in claim 1, wherein in the step S1, the thickness of the silicon substrate on the back side of the wafer is 700-800um, and the thickness of the circuit layer on the front side of the wafer is 2-30um.

3. The 3D NAND wafer cutting process as claimed in claim 1, wherein in the step S3, the thinning process is performed by rough grinding and fine grinding through mechanical grinding, and the silicon substrate is ground to a specified thickness of 10-100um.

4. The process of claim 1, wherein in the step S4, the adhesive film has a double-layer structure, and the double-layer structure includes a substrate and an adhesive layer.

5. The 3D NAND wafer cutting process according to claim 1, wherein in the step S5, the manner of removing the glass carrier plate 1 is as follows: laser dispergation or heating dispergation.

6. The 3D NAND wafer dicing process of claim 1, wherein in the step S8, the thickness of the silicon substrate in the dicing street region is between 10-40 um.

7. The 3D NAND wafer dicing process as claimed in claim 6, wherein in the step S9, the width of the blade is less than or equal to 80% of the width of the scribe line.

8. The 3D NAND wafer dicing process according to claim 1, wherein after the step S7 is completed, if the silicon substrate is thicker than 40um, a blade is directly used to cut through the silicon substrate and the adhesive film.

9. The process of any one of claims 1 to 8, wherein a glass carrier is replaced with a silicon carrier.