CN115942549B - Constant current drive IO circuit and constant current drive IO chip - Google Patents

Constant current drive IO circuit and constant current drive IO chip Download PDF

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CN115942549B
CN115942549B CN202211692124.1A CN202211692124A CN115942549B CN 115942549 B CN115942549 B CN 115942549B CN 202211692124 A CN202211692124 A CN 202211692124A CN 115942549 B CN115942549 B CN 115942549B
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constant current
slew rate
transmission gate
input end
unit
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CN115942549A (en
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莫昌文
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Foshan Jusheng Microelectronics Co ltd
Zhuhai Jusheng Technology Co ltd
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Foshan Jusheng Microelectronics Co ltd
Zhuhai Jusheng Technology Co ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses a constant current driving IO circuit and a chip, wherein the constant current driving IO circuit is provided with a P-type analog driver, an N-type analog driver and an IO driving power unit; the P-type analog driver is used for receiving the constant current control enabling signal and the first logic control signal, and outputting a first constant current control signal to the IO driving power unit after receiving the first bias voltage signal according to the constant current control enabling signal; the N-type analog driver is used for receiving the constant current control enabling signal, outputting a second constant current control signal to the IO driving power unit after receiving the second bias voltage signal according to the constant current control enabling signal, and outputting an IO driving signal to a target IO port according to the received first constant current control signal and the second constant current control signal by the IO driving power unit; the technical problems of short service life of devices, and high cost caused by the fact that extra hardware is required to be added for brightness adjustment due to the fact that starting current impact is large when a chip drives an IO port through voltage in the related art are solved.

Description

Constant current drive IO circuit and constant current drive IO chip
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a constant current driving IO circuit and a constant current driving IO chip.
Background
In the related technology, the chip is used for driving the external LED lamp or the external LED segment code display screen mainly by adopting common voltage driving to drive the IO port, and constant current control can not be carried out on the external LED lamp or the external LED segment code display screen; when the non-constant current driving is performed, extra hardware cost is required to be increased, and when the non-constant current driving is started, larger impact current is easy to generate, so that the stability of chip design and the service life of an external LED lamp or the service life of an LED segment code display screen are influenced.
Therefore, how to solve the technical problems of high hardware cost and low service life of devices caused by the failure to realize constant current driving of the IO port in the related art becomes a technical problem to be overcome by the technicians in the field.
Disclosure of Invention
The embodiment of the invention provides a constant current driving IO circuit and a constant current driving IO chip, which are used for solving the technical problems of high hardware cost and low service life of devices caused by voltage driving IO in the related technology.
In a first aspect, an embodiment of the present invention provides a constant current drive IO circuit including:
The P-type driving simulator is used for receiving a constant current control enabling signal and a first logic control signal, receiving a first bias voltage signal according to the constant current control enabling signal, and outputting a first constant current control signal according to the constant current control enabling signal, the first bias voltage signal and the external logic control signal;
the N-type driving simulator is used for receiving the constant current control enabling signal and the second logic control signal, receiving a second bias voltage signal according to the constant current control enabling signal, and outputting a second constant current control signal according to the constant current control enabling signal, the second bias voltage signal and the second logic control signal;
and the IO driving power unit is used for receiving the first constant current control signal and the second constant current control signal and outputting an IO driving signal.
The constant current driving IO circuit provided by the embodiment of the invention has at least the following beneficial effects:
the embodiment of the invention discloses a constant current driving IO circuit, which is provided with a P-type analog driver, an N-type analog driver and an IO driving power unit; the P-type analog driver is used for receiving a constant current control enabling signal and a first logic control signal, outputting a first constant current control signal to the IO driving power unit according to the constant current control enabling signal, the first bias voltage signal and the first logic control signal after receiving the first bias voltage signal according to the constant current control enabling signal, and outputting a second constant current control signal to the IO driving power unit according to the constant current control enabling signal, the second logic control signal and the second bias voltage signal after receiving the constant current control enabling signal according to the constant current control enabling signal, and the IO driving power unit outputting an IO driving signal to the target IO port according to the received first constant current control signal and the received second constant current control signal for driving the target IO port; the technical problems of short service life of devices and high cost caused by the fact that extra hardware is required to be added for brightness adjustment due to the fact that starting current impact is large when a chip drives an IO port through voltage in the related technology are solved; the constant-current driving IO circuit is capable of performing constant-current driving IO ports, low in cost and capable of prolonging the service life of devices.
According to other embodiments of the present invention, the constant current driving IO circuit, the IO driving power unit includes a first PMOS tube and a first NMOS tube;
the drain electrode of the first PMOS tube is respectively connected with the drain electrode of the first NMOS tube and the output end of the IO drive power unit, the grid electrode of the first PMOS tube receives the first constant current control signal, the grid electrode of the first NMOS tube is used for receiving the second constant current control signal, the source electrode of the first PMOS tube is connected with the circuit power supply high potential end VDD, and the source electrode of the first NMOS tube is connected with the circuit low potential end VSS;
the first PMOS tube and the first NMOS tube are respectively controlled by the first constant current control signal and the second constant current control signal and used for outputting the IO driving signal.
According to other embodiments of the present invention, the P-type analog driver includes a first driving inverter, a P-terminal inverter unit, a P-terminal control transmission gate unit, a P-terminal slew rate inverter unit, a P-terminal slew rate transmission gate unit, and a first bias selection switch unit;
the first drive inverter is configured to receive the first logic control signal;
the output end of the first driving inverter is respectively connected with the input end of the P-end inverter unit, the first input end of the P-end slew rate transmission gate unit and the first input end of the P-end slew rate inverter unit, the output end of the P-end inverter unit is respectively connected with the first input end of the P-end control transmission gate unit, the second input end of the P-end slew rate inverter unit and the second input end of the P-end slew rate transmission gate unit, the second input end, the third input end and the fourth input end of the P-end control transmission gate unit are controlled by the constant current control enabling signal, the output end of the P-end control transmission gate unit is connected with the third input end of the P-end slew rate inverter unit, the first output end of the P-end slew rate inverter unit is respectively connected with the first input end of the IO driving power unit and the third input end of the P-end slew rate transmission gate unit, and the second output end of the P-end control transmission gate unit is connected with the fourth input end of the P-end slew rate transmission gate unit;
The first bias selection switch is connected with a fourth input end of the P-end slew rate transmission gate unit and is used for sending the first bias voltage signal to the P-end slew rate transmission gate unit according to the constant current control enabling signal.
According to other embodiments of the present invention, the constant current driving IO circuit includes a second driving inverter, an N-terminal inverter unit, an N-terminal control transmission gate unit, an N-terminal slew rate inverter unit, an N-terminal slew rate transmission gate unit, and a second bias selection switch unit;
the second drive inverter is configured to receive the second logic control signal;
the output end of the second driving inverter is respectively connected with the input end of the N-end inverter unit, the first input end of the N-end slew rate inverter unit and the first input end of the N-end slew rate transmission gate unit, the output end of the N-end inverter unit is respectively connected with the first input end of the N-end control transmission gate unit, the second input end of the N-end slew rate inverter unit and the second input end of the N-end slew rate transmission gate unit, the second input end, the third input end and the fourth input end of the N-end control transmission gate unit are controlled by the constant current control enabling signal, the output end of the N-end control transmission gate unit is connected with the third input end of the N-end slew rate inverter unit, the first output end of the N-end slew rate inverter unit is connected with the third input end of the N-end slew rate transmission gate unit, and the second output end of the N-end slew rate inverter unit is respectively connected with the second input end of the IO driving power unit and the fourth input end of the N-end slew rate transmission gate unit;
The second bias selection switch is connected with a third input end of the N-end slew rate control transmission gate unit and is used for sending the second bias voltage signal to the N-end slew rate control transmission gate unit according to the constant current control enabling signal.
According to other embodiments of the present invention, the P-terminal inverter unit includes a second PMOS transistor and a second NMOS transistor, and the N-terminal inverter unit includes a third PMOS transistor and a third NMOS transistor;
the grid electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the second PMOS tube is connected with the circuit power supply high potential end VDD, the source electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is connected with the circuit low potential end VSS, the grid electrode of the second PMOS tube is the input end of the P-end inverter unit, and the drain electrode of the second PMOS tube is the output end of the P-end inverter unit;
the grid electrode of the third PMOS tube is connected with the grid electrode of the third NMOS tube, the source electrode of the third PMOS tube is connected with the circuit power supply high potential end VDD, the source electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, the source electrode of the third NMOS tube is connected with the circuit low potential end VSS, the grid electrode of the third PMOS tube is the input end of the N-terminal inverter unit, and the drain electrode of the third PMOS tube is the output end of the N-terminal inverter unit.
According to other embodiments of the present invention, the P-terminal inverter unit includes a second PMOS transistor and a second NMOS transistor, and the N-terminal inverter unit includes a third PMOS transistor and a third NMOS transistor;
the grid electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the second PMOS tube is connected with the circuit power supply high potential end VDD, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is connected with the circuit low potential end VSS, the grid electrode of the second PMOS tube is the input end of the P-end inverter unit, and the drain electrode of the second PMOS tube is the output end of the P-end inverter unit;
the grid electrode of the third PMOS tube is connected with the grid electrode of the third NMOS tube, the source electrode of the third PMOS tube is connected with the circuit power supply high potential end VDD, the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, the source electrode of the third NMOS tube is connected with the circuit low potential end VSS, the grid electrode of the third PMOS tube is the input end of the N-terminal inverter unit, and the drain electrode of the third PMOS tube is the output end of the N-terminal inverter unit.
According to other embodiments of the present invention, the P-terminal control transmission gate unit includes a fourth PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor, and the N-terminal control transmission gate unit includes a fifth PMOS transistor, a sixth PMOS transistor, and a sixth NMOS transistor;
The drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is respectively connected with the source electrode of the fourth PMOS tube and the drain electrode of the fifth NMOS tube, the source electrode of the fifth NMOS tube is connected with the circuit low potential end VSS, the drain electrode of the fourth NMOS tube is the first input end of the P-end control transmission gate unit, and the source electrode of the fourth NMOS tube is the output end of the P-end control transmission gate unit; the grid of the fourth NMOS tube is a second input end of the P-end control transmission gate unit and is controlled by an inversion signal of the constant current control enabling signal; the gate of the fifth NMOS tube is a third input end of the P-end control transmission gate unit and is controlled by the constant current control enabling signal; the grid of the fourth PMOS tube is a fourth input end of the P-end control transmission gate unit and is controlled by the constant current control enabling signal;
the drain electrode of the fifth PMOS tube is connected with the drain electrode of the sixth NMOS tube, the source electrode of the sixth NMOS tube is respectively connected with the source electrode of the fifth PMOS tube and the drain electrode of the sixth PMOS tube, the source electrode of the sixth PMOS tube is connected with the circuit power supply high potential end VDD, and the drain electrode of the sixth NMOS tube is the first input end of the N-end control transmission gate unit; the grid of the sixth NMOS tube is a second input end of the N-terminal control transmission gate unit and is controlled by an inversion signal of the constant current control enabling signal; the grid of the sixth PMOS tube is a third input end of the N-end control transmission gate unit and is controlled by an inversion signal of the constant current control enabling signal; the grid of the fifth PMOS tube is a fourth input end of the N-end control transmission gate unit and is controlled by the constant current control enabling signal; and the source of the sixth NMOS tube is the output end of the N-terminal control transmission gate unit.
According to other embodiments of the present invention, the constant current driving IO circuit includes a P-side slew rate inverter unit including a seventh PMOS transistor, an eighth PMOS transistor, and a seventh NMOS transistor, and the N-side slew rate inverter unit includes a ninth PMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor;
the source electrode and the substrate of the seventh PMOS tube are connected with a circuit power supply high-potential end VDD, the drain electrode of the seventh PMOS tube is connected with the source electrode of the eighth PMOS tube, the substrate of the eighth PMOS tube is connected with the circuit power supply high-potential end VDD, the drain electrode of the eighth PMOS tube is connected with the drain electrode of the seventh NMOS tube, the source electrode of the seventh NMOS tube is connected with a circuit low-potential end VSS, the gate electrode of the eighth PMOS tube is a first input end of the P-end slew rate inverter unit, the gate electrode of the seventh PMOS tube is a second input end of the P-end slew rate inverter unit, the gate electrode of the seventh NMOS tube is a third input end of the P-end slew rate inverter unit, the drain electrode of the seventh PMOS tube is a first output end of the P-end slew rate inverter unit, and the drain electrode of the eighth PMOS tube is a second output end of the P-end slew rate inverter unit;
the source electrode and the substrate of the ninth PMOS tube are connected with a circuit power supply high potential end VDD, the drain electrode of the ninth PMOS tube is connected with the drain electrode of the eighth NMOS tube, the source electrode of the eighth NMOS tube is connected with a circuit low potential end VSS, the gate electrode of the eighth NMOS tube is a first input end of the N-end slew rate inverter unit, the gate electrode of the ninth NMOS tube is a second input end of the N-end slew rate inverter unit, the gate electrode of the ninth PMOS tube is a third input end of the N-end slew rate inverter unit, the drain electrode of the ninth PMOS tube is a first output end of the N-end slew rate inverter unit, and the drain electrode of the ninth NMOS tube is a second output end of the N-end slew rate inverter unit.
According to other embodiments of the present invention, the constant current driving IO circuit includes a P-side slew rate transmission gate unit including a tenth PMOS transistor and a tenth NMOS transistor, and the N-side slew rate transmission gate unit includes an eleventh PMOS transistor and an eleventh NMOS transistor;
the drain electrode of the tenth PMOS tube is connected with the drain electrode of the tenth NMOS tube, the substrate of the tenth PMOS tube is connected with the circuit power supply high potential end VDD, the source electrode of the tenth PMOS tube is connected with the source electrode of the tenth NMOS tube, the gate electrode of the tenth PMOS tube is the first input end of the P-end slew rate transmission gate unit, the gate electrode of the tenth NMOS tube is the second input end of the P-end slew rate transmission gate unit, the source electrode of the tenth PMOS tube is the third input end of the P-end slew rate transmission gate unit, and the drain electrode of the tenth PMOS tube is the fourth input end of the P-end slew rate transmission gate unit;
the drain electrode of the eleventh PMOS tube is connected with the drain electrode of the eleventh NMOS tube, the substrate of the eleventh PMOS tube is connected with the circuit power supply high potential end VDD, the source electrode of the eleventh PMOS tube is connected with the source electrode of the eleventh NMOS tube, the gate electrode of the eleventh NMOS tube is the first input end of the N-end slew rate transmission gate unit, the gate electrode of the eleventh PMOS tube is the second input end of the N-end slew rate transmission gate unit, the drain electrode of the eleventh PMOS tube is the third input end of the N-end slew rate transmission gate unit, and the source electrode of the eleventh PMOS tube is the fourth input end of the N-end slew rate transmission gate unit.
According to other embodiments of the present invention, the constant current driving IO circuit further includes a bias voltage generating circuit;
the bias voltage generating circuit is used for outputting a first bias voltage signal and a second bias voltage signal.
In a second aspect, an embodiment of the present invention provides a constant current driving IO chip, which includes a chip body and the constant current driving IO circuit described above.
Drawings
FIG. 1 is a schematic diagram of a first embodiment module connection of a constant current driving IO circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a module connection of a second embodiment of a constant current driving IO circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a module connection of a third embodiment of a constant current driving IO circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram showing the circuit configuration and connection of a constant current driving IO circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a relationship between a constant current control enable signal CCEN and a CENB signal CENH signal in a constant current driving IO circuit according to an embodiment of the present invention.
Detailed Description
The conception and technical effects of the present invention will be clearly and completely described in conjunction with the following examples to fully understand the objects, features and effects of the present invention. It is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments, and that other embodiments obtained by those skilled in the art without inventive effort are within the scope of the present invention based on the embodiments of the present invention.
In the description of the embodiments of the present invention, if "several" is referred to, it means more than one, if "multiple" is referred to, it is understood that the number is not included if "greater than", "less than", "exceeding", and it is understood that the number is included if "above", "below", "within" is referred to. If reference is made to "first", "second" it is to be understood as being used for distinguishing technical features and not as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
Referring to fig. 1, an embodiment of the present invention provides a constant current driving IO circuit including a P-type analog driver, an N-type analog driver, and an IO driving power unit. In this embodiment, the output ends of the P-type analog driver and the N-type analog driver are respectively connected with the input end of the IO drive power unit, and the P-type analog driver is configured to receive a first logic control signal and a constant current control enable signal, receive a first bias voltage signal according to the state of the constant current control enable signal therein, and output a first constant current control signal to the IO drive power unit according to the constant current control enable signal, the first bias voltage signal and the first logic control signal. The N-type analog driver is used for receiving the constant current control enabling signal and the second logic control signal, receiving the second bias voltage signal according to the state of the constant current control enabling signal, and outputting the second constant current control signal to the IO driving power unit according to the constant current control enabling signal, the second bias voltage signal and the second logic control signal. And the IO driving power unit outputs an IO driving signal to the target IO port according to the received first constant current control signal and the received second constant current control signal. In this embodiment, when the IO port needs to be driven in a constant current driving manner, the constant current control enable signal is a high level signal, the P-type analog driver receives a first bias voltage signal, and the N-type analog driver receives a second bias voltage signal, so that the IO drive signal output by the IO drive power unit is a constant current drive signal, when the IO port is driven in a voltage driving manner (in a non-constant current manner), the constant current control enable signal is a low level signal, the P-type analog driver cannot receive the first bias voltage signal, the N-type analog driver cannot receive the second bias voltage signal, and further, the IO drive signal output by the IO drive power unit is a non-constant current drive signal, and the first logic control signal and the second logic control signal are respectively used for controlling the operating states of the P-type analog driver and the N-type analog driver, so that the IO drive signal is output in a high current mode or a low current mode.
Referring to fig. 2, in some embodiments, the constant current driving IO circuit further includes a bias voltage generating circuit, a first output terminal of the bias voltage generating circuit is connected to an input terminal of the P-type analog driver, and is configured to input a first bias voltage signal to the P-type analog driver according to the constant current control enable signal; the second output end of the bias voltage generating circuit is connected with the input end of the N-type analog driver and is used for inputting a second bias voltage signal to the N-type analog driver according to the constant current control enabling signal. In this embodiment, when the output of the constant current driving IO circuit is in the constant current high current mode, the first bias voltage signal outputs a high level signal, and the second bias voltage signal outputs a low level signal; when the output of the constant current driving IO circuit is in a constant current low current mode, the first bias voltage signal is a low level signal, and the second bias voltage signal is a high level signal.
Referring to fig. 3, in some embodiments, the P-type analog driver includes a first driving inverter 110, a P-side inverter unit 130, a P-side control transmission gate unit 130, a P-side slew rate inverter unit 140, a P-side slew rate transmission gate unit 150, and a first bias selection switch 160. The output end of the first driving inverter 110 is respectively connected with the input end of the P-terminal inverter unit 120, the first input end of the P-terminal slew rate transmission gate unit 150, and the first input end of the P-terminal slew rate inverter 140, the output end of the P-terminal inverter unit 120 is respectively connected with the first input end of the P-terminal control transmission gate unit 130, the second input end of the P-terminal inverter unit 140, the second input end of the P-terminal slew rate transmission gate unit 150, the second input end, the third input end and the fourth input end of the P-terminal control transmission gate unit 130 are controlled by constant current control enable signals, the output end of the P-terminal control transmission gate unit 130 is connected with the third input end of the P-terminal slew rate transmission gate unit 140, the first output end of the P-terminal slew rate inverter unit 140 is respectively connected with the first input end of the IO driving power unit 100, the third input end of the P-terminal slew rate transmission gate unit 150, the second output end of the P-terminal slew rate inverter unit is connected with the first input end of the P-terminal slew rate transmission gate unit 150, the second output end of the P-terminal control transmission gate unit is connected with the first input end of the P-terminal 160 of the P-terminal slew rate transmission gate unit 150, the first bias signal is biased to the first input end of the first bias unit 160, and the first input end of the first bias unit is biased to the first input end of the first bias signal is biased to control gate unit 150. In this embodiment, the first driving inverter 110 is configured to receive a first logic control signal, so that the driving capability of the constant current driving IO circuit in the embodiment of the present invention is stronger, the signal variation response capability is enhanced, and the P-terminal inverter unit 120 is configured to cooperate with the subsequent units (including the P-terminal control transmission gate unit 130, the P-terminal slew rate inverter unit 140, and the P-terminal slew rate transmission gate unit 150) to perform design optimization of the overall circuit. In the present embodiment, the connection relationship between the respective units in fig. 3 is not fully shown, and the specific connection relationship is referred to the above description.
Referring to fig. 3, in some embodiments, the N-type analog driver includes a second driving inverter 210, an N-terminal inverter unit 220, an N-terminal control transmission gate unit 230, an N-terminal slew rate inverter unit 240, an N-terminal slew rate transmission gate unit 250, and a second bias selection switch 260. The second driving inverter is configured to receive a second logic control signal, the output end of the second driving inverter 210 is respectively connected to the input end of the N-terminal inverter unit 220, the first input end of the N-terminal slew rate inverter unit 240, and the first input end of the N-terminal slew rate transmission gate unit 250, the output end of the N-terminal inverter unit 220 is respectively connected to the first input end of the N-terminal control transmission gate unit 230, the second input end of the N-terminal slew rate inverter unit 240, the second input end of the N-terminal slew rate transmission gate unit 250, the second input end, the third input end and the fourth input end of the N-terminal control transmission gate unit 230 are controlled by constant current control enable signals, the output end of the N-terminal control transmission gate unit 230 is connected to the third input end of the N-terminal slew rate inverter unit 240, the first output end of the N-terminal slew rate inverter unit 240 is connected to the third input end of the N-terminal slew rate transmission gate unit 250, the second output end of the N-terminal slew rate inverter unit 240 is respectively connected to the second input end of the IO driving power unit 100, the second input end of the N-terminal slew rate transmission gate unit 260 is connected to the second input end of the second slew rate transmission gate unit 250, and the second input end of the second input signal is biased to the second input end of the second slew rate selection unit 260. In this embodiment, the second driving inverter 210 is configured to receive a second logic control signal, so that the driving capability of the constant current driving IO circuit in this embodiment of the present invention is stronger, the signal variation response capability is enhanced, and the N-terminal inverter unit 220 is configured to cooperate with the subsequent units (including the N-terminal control transmission gate unit 230, the N-terminal slew rate inverter unit 240, and the N-terminal slew rate transmission gate unit 250) to perform design optimization of the overall circuit. In the present embodiment, the connection relationship between the respective units in fig. 3 is not fully shown, and the specific connection relationship is referred to the above description.
The following describes the specific circuit composition of each unit by a specific embodiment:
referring to fig. 4, in the present embodiment, the IO driving power unit 100 includes a first PMOS transistor M11 and a first NMOS transistor M22; the source electrode and the substrate of the first PMOS tube M11 are connected with a circuit power supply high potential end VDD, the drain electrode of the first PMOS tube M11 is connected with the drain electrode of the first NMOS tube M22, and the source electrode of the first NMOS tube M22 is connected with a circuit low potential end VSS. The grid electrode of the first PMOS tube M11 is used as a first input end of the IO driving power unit 100 and is used for receiving a first constant current control signal; the gate of the first NMOS transistor is used as a second input end of the IO drive power unit 100, and is configured to receive a second constant current control signal; the PAD end connected with the drain electrode of the first PMOS transistor M11 (also connected with the drain electrode of the first NMOS transistor M22) is an output end of the IO driving power unit, and is configured to output an IO driving signal. In this embodiment, the P-side inverter unit 120 includes a second PMOS transistor M1 and a second NMOS transistor M2, the N-side inverter unit 220 includes a third PMOS transistor M12 and a third NMOS transistor M13, the P-side control transmission gate unit 130 includes a fourth PMOS transistor M3, a fourth NMOS transistor M4 and a fifth NMOS transistor M5, the N-side control transmission gate unit 230 includes a fifth PMOS transistor M14, a sixth PMOS transistor M16 and a sixth NMOS transistor M15, the P-side slew rate inverter unit 140 includes a seventh PMOS transistor M6, an eighth PMOS transistor M7 and a seventh NMOS transistor M8, the N-side slew rate inverter unit 240 includes a ninth PMOS transistor M17, an eighth NMOS transistor M18 and a ninth NMOS transistor M19, the P-side slew rate transmission gate unit 150 includes a tenth PMOS transistor M9 and a tenth NMOS transistor M10, and the N-side slew rate transmission gate unit 250 includes an eleventh PMOS transistor M20 and an eleventh NMOS transistor M21. In this embodiment, the specific connection relationship of each device in the P-type analog driver is as follows: the first driving inverter 110 is connected to the circuit power high voltage terminal VDD and the circuit low voltage terminal VSS, respectively, and the first driving inverter 110 is configured to receive a first logic control signal. In the P-terminal inverter unit 120: the grid of the second PMOS tube M1 is connected with the grid of the second NMOS tube M2, the source electrode of the second PMOS tube M1 is connected with the high-potential end VDD of circuit power supply, the drain electrode of the second PMOS tube M1 is connected with the drain electrode of the second NMOS tube M2, the source electrode of the second NMOS tube M2 is connected with the low-potential end VSS of circuit, the input end of the P-end inverter unit 120 is the grid of the second PMOS tube M1 (also the grid of the second NMOS tube M2), the output end of the P-end inverter unit 120 is the drain electrode of the second PMOS tube M1 (also the drain electrode of the second NMOS tube M2) and is connected with the input end of the P-end control transmission gate unit 130, the second input end of the P-end slew rate inverter unit 140 and the second input end of the P-end slew rate transmission gate unit 150. The P-terminal control transmission gate unit 130: the drain electrode of the fourth PMOS tube M3 is connected with the drain electrode of the fourth NMOS tube M4 and is used as the input end of the P-end control transmission gate unit 130, the source electrode of the fourth PMOS tube M3 is respectively connected with the source electrode of the fourth NMOS tube M4 and the source electrode of the fifth NMOS tube M5 and is used as the output end of the P-end control transmission gate unit 130 to be connected with the third input end of the P-end slew rate inverter unit 140, the source electrode of the fifth NMOS tube M5 is connected with the circuit low potential end VSS, the grid electrode of the fourth NMOS tube M4 is used as the second input end of the P-end control transmission gate unit 130 and is controlled by the inverting signal CENB of the constant current control enable signal CCEN; the gate of the fifth NMOS transistor M5 is a third input terminal of the P-terminal control transmission gate unit 130, and is controlled by an inverted signal CCNH of the CCNB signal (i.e., an in-phase signal with the constant current control enable signal CCEN), and the gate of the fourth PMOS transistor M3 is a fourth input terminal of the P-terminal control transmission gate unit 130, and is controlled by the CENH signal. The relationship between the constant current control enable signal CCEN and the CENB signal CENH signal is shown in fig. 5. The P-side slew rate inverter unit 140: the source electrode and the substrate of the seventh PMOS tube M6 are connected with the circuit power supply high potential end VDD, the drain electrode of the seventh PMOS tube M6 is connected with the source electrode of the eighth PMOS tube M7 and serves as a first output end of the P-end slew rate inverter unit 140, the substrate of the eighth PMOS tube M7 is connected with the circuit power supply high potential end VDD, the drain electrode of the eighth PMOS tube M7 is connected with the drain electrode of the seventh NMOS tube M8 and serves as a second output end of the P-end slew rate inverter unit 140, the source electrode of the seventh NMOS tube M8 is connected with the circuit low potential end VSS, the grid electrode of the eighth PMOS tube M7 is the first input end of the P-end slew rate inverter unit 140, the grid electrode of the seventh PMOS tube M6 is the second input end of the P-end slew rate inverter unit 140, and the grid electrode of the seventh NMOS tube M8 is the third input end of the P-end slew rate inverter unit 140. In the P-side slew rate transmission gate unit 150: the gate of the tenth PMOS transistor M9 is the first input end of the P-side slew rate transmission gate unit 150, the substrate of the tenth PMOS transistor M9 is connected to the circuit power supply high potential end VDD, the gate of the tenth NMOS transistor M10 is the second input end of the P-side slew rate transmission gate unit 150, the source of the tenth PMOS transistor M9 is connected to the source of the tenth NMOS transistor M10 and is used as the third input end of the P-side slew rate transmission gate unit 150, and the drain of the tenth PMOS transistor M9 is connected to the drain of the tenth NMOS transistor M10 and is used as the fourth input end of the P-side slew rate transmission gate unit 150. One end of the first bias selection switch 160 is connected to the fourth input end of the P-side slew rate control transmission gate unit 150, and the first bias selection switch 160 is controlled by the CENH signal and is configured to transmit the first bias voltage signal VBP to the P-side slew rate transmission gate unit 150 according to the CENH signal. In this embodiment, the connection relationship of each device in the N-type analog driver is as follows: the second driving inverter 210 is connected to the circuit power high voltage terminal VDD and the circuit low voltage terminal VSS, respectively, and the second driving inverter 210 is configured to receive the second logic control signal. In the N-terminal inverter unit 220: the gate of the third PMOS transistor M12 is connected to the gate of the third NMOS transistor M13 as an input terminal of the N-terminal inverter unit, and is connected to the output terminal of the second driving inverter 210, the first input terminal of the N-terminal slew rate inverter unit 240, and the first input terminal of the N-terminal slew rate transmission gate unit 250, respectively, the source of the third PMOS transistor M12 is connected to the circuit power supply high potential terminal VDD, the drain of the third PMOS transistor M12 is connected to the drain of the third NMOS transistor M13, and is used as an output terminal of the N-terminal inverter unit 220, and is connected to the first input terminal of the N-terminal control transmission gate unit 230, the second input terminal of the N-terminal slew rate inverter unit 240, and the second input terminal of the N-terminal slew rate transmission gate unit 250, respectively, and the source of the third NMOS transistor M13 is connected to the circuit low potential terminal VSS. N-terminal control transmission gate unit 230: the drain electrode of the fifth PMOS tube M14 is connected with the drain electrode of the sixth NMOS tube M15 and is used as the first input end of the N-terminal slew rate control transmission gate unit 230, the substrate of the fifth PMOS tube M14 is connected with the circuit power supply high potential end VDD, the source electrode of the fifth PMOS tube M14 is respectively connected with the source electrode of the sixth NMOS tube M15 and the drain electrode of the sixth PMOS tube M16 and is used as the output end of the N-terminal slew rate control transmission gate unit 230 and is connected with the third input end of the N-terminal slew rate inverter unit 240; the gate of the sixth NMOS transistor M15 is a second input terminal of the N-terminal control transmission gate unit 230, and is controlled by the inverted signal CENB of the constant current control enable signal CCEN; the gate of the sixth PMOS transistor M16 is a third input terminal of the N-terminal control transmission gate unit 230, and is controlled by the signal CENB; the gate of the fifth PMOS transistor M14 is a fourth input terminal of the N-terminal control transmission gate unit 230, and is controlled by a signal CENH, wherein the relationship between the constant current control enable signal CCEN and CENB signals, CENH signals is shown in fig. 5. In the N-side slew rate inverter unit 240: the source electrode and the substrate of the ninth PMOS tube M17 are connected with a circuit power supply high potential end VDD, the drain electrode of the ninth PMOS tube M17 is connected with the drain electrode of the eighth NMOS tube M18, and is used as the first output end of the N-terminal slew rate inverter unit 240 and is connected with the third input end of the N-terminal slew rate transmission gate unit 250; the source electrode of the eighth NMOS transistor M18 is connected to the drain electrode of the ninth NMOS transistor M19, and is used as the second output end of the N-terminal slew rate inverter unit 240, and is respectively connected to the second input end of the IO driving power unit 100 and the fourth input end of the N-terminal slew rate transmission gate unit 250; the source electrode of the ninth NMOS tube M19 is connected with the low potential end VSS of the circuit; the gate of the eighth NMOS transistor M18 is the first input terminal of the N-side slew rate inverter unit 240, the gate of the ninth NMOS transistor M19 is the second input terminal of the N-side slew rate inverter unit 240, and the gate of the ninth PMOS transistor M17 is the third input terminal of the N-side slew rate inverter unit 240. In the N-terminal slew rate transmission gate unit 250: the substrate of the eleventh PMOS tube M20 is connected with the circuit power supply high potential end VDD, and the drain electrode of the eleventh PMOS tube M20 is connected with the drain electrode of the eleventh NMOS tube M21 and is used as the third input end of the N-terminal slew rate transmission gate unit 250; the source electrode of the eleventh PMOS transistor M20 is connected to the source electrode of the eleventh NMOS transistor M21, and is used as the fourth input end of the N-terminal slew rate transmission gate unit 250; the gate of the eleventh NMOS transistor M21 is a first input terminal of the N-terminal slew rate transmission gate unit 250, and the gate of the eleventh PMOS transistor M20 is a second input terminal of the N-terminal slew rate transmission gate unit 250. One end of the second bias selection switch 260 is connected to the third input end of the N-terminal slew rate transmission gate unit 250, and the second bias selection switch 260 is controlled by the CENH signal and is configured to transmit the second bias voltage signal VBN to the N-terminal slew rate transmission gate unit 250 according to the CENH signal.
Referring to fig. 4, based on the implementation manner of the specific circuit, when the constant current driving IO circuit according to the embodiment of the present invention needs to drive the IO port in the constant current high current mode, the working states of each device are as follows: the constant current control enable signal CCEN outputs a high level signal, the CENB signal is a low level signal, the CENH signal is a high level signal, and the P end controls the fourth PMOS transistor M3, the fourth NMOS transistor M4, and the fifth NMOS transistor M5 of the transmission gate unit 130 to be turned off, and the N end controls the fifth PMOS transistor M14, the sixth PMOS transistor M16, and the sixth NMOS transistor M15 of the transmission gate unit 230 to be turned off. After the first logic control signal passes through the first driving inverter 110, the first driving inverter 110 outputs a low level signal, and at this time, the second PMOS transistor M1 is turned on, the eighth PMOS transistor M7 is turned on, the tenth PMOS transistor M9 is turned on, the P-terminal inverter unit 220 outputs a high level signal, and the seventh PMOS transistor M6 is turned off, the tenth NMOS transistor M10 is turned on, the seventh NMOS transistor M8 is turned off, the drain of the eighth PMOS transistor M7 outputs a high level signal, and the first bias selection switch 160 is turned on to receive the first bias voltage signal VBP. Similarly, after the second logic control signal passes through the second driving inverter 210, the second driving inverter 210 outputs a low level signal, at this time, the third PMOS transistor M12 is turned on, the third NMOS transistor M13 is turned off, the eighth NMOS transistor M18 is turned off, the eleventh NMOS transistor M21 is turned off, and the third PMOS transistor M12 is turned on and outputs a high level signal, so that the ninth NMOS transistor M19 is turned on, the eleventh PMOS transistor M20 is turned off, and the ninth PMOS transistor M17 is turned off because the sixth PMOS transistor M16 is turned on, and the drain voltage thereof is pulled low because the ninth NMOS transistor M19 is turned on, so that the first NMOS transistor M22 in the IO driving power unit 100 is turned off. At this time, the second bias selection switch 260 is turned on to receive the second bias voltage signal VBN. In order to realize constant-current high-current mode driving of the IO port, the first bias voltage signal VBP is a high-level signal, and the second bias voltage signal VBN is a low-level signal. The level of the gate of the first PMOS transistor M11 in the IO drive power unit 100 is pulled down (i.e., corresponding to the first constant current control signal) by the first bias voltage signal VBP input as the high level signal, so that the first PMOS transistor M11 works in the saturation region, and therefore, the current flowing to the PAD through the first PMOS transistor M11 is the high current constant current mode. When the IO port needs to be driven in the constant current low current mode, the on states of the devices in the P-terminal control transmission gate unit 130 and the N-terminal control transmission gate unit 230 are the same as those in the high current constant current mode. At this time, after the first driving inverter 110 receives the first logic control signal, a high level signal is output, and then the second PMOS transistor M1 is turned off, the second NMOS transistor M2 is turned on, the eighth PMOS transistor M7 is turned off, the tenth PMOS transistor M9 is turned off, after the second NMOS transistor M2 is turned on, the gate voltage of the seventh PMOS transistor M6 and the gate voltage of the tenth NMOS transistor M10 are pulled down, at this time, the seventh PMOS transistor M6 is turned on, the tenth NMOS transistor M10 is turned off, after the seventh PMOS transistor M6 is turned on, the drain voltage thereof is increased, and since the eighth PMOS transistor M7 is turned off, the gate voltage of the first PMOS transistor M11 is increased, the first PMOS transistor M11 is turned off, and the first bias selection switch 160 is turned on, to receive the first bias voltage signal VBP. Similarly, after receiving the second logic control signal, the second driving inverter outputs a high level signal, and then the third PMOS transistor M12 is turned off, the third NMOS transistor M13 is turned on, and the eighth NMOS transistor M18 is turned on. After the third NMOS transistor M13 is turned on, the gate voltage of the eleventh PMOS transistor M20 and the gate voltage of the ninth NMOS transistor M19 are pulled down, so that the eleventh PMOS transistor M20 is turned on and the ninth NMOS transistor M19 is turned off. Since the sixth PMOS transistor M16 is turned on, the gate voltage of the Gao Dijiu PMOS transistor M17 is pulled, and the ninth PMOS transistor M17 is turned off. After the eighth NMOS transistor M18 is turned on, the gate voltage of the first NMOS transistor M22 is pulled up, and at this time, the second bias selection switch 260 is turned on, and receives the second bias voltage signal VBN to the drain of the eighth NMOS transistor M18. In order to realize constant current low current mode driving of the IO port, the first bias voltage signal VBP is a low level signal, and the second bias voltage signal VBN is a high level signal. The gate of the first NMOS transistor M22 in the IO drive power unit is pulled high (i.e., corresponding to the second constant current control signal) by the second bias voltage signal VBN input as the high level signal, so that the first NMOS transistor M22 works in the saturation region, and therefore, the current flowing to the first NMOS transistor M22 through the PAD is the low current constant current mode.
Obviously, in some embodiments, the constant current driving IO circuit provided by the embodiment of the invention can realize common voltage driving IO ports. When driven at a non-constant current high voltage: the constant current control enable signal CCEN is a low level signal, the first driving inverter 110 receives the first logic control signal and outputs a low level signal, and the second driving inverter 210 receives the second logic control signal and outputs a low level signal; each device is in a corresponding working state according to the constant current control enabling signal, the low level signal output by the first driving inverter 110 and the low level signal output by the second driving inverter 210, at this time, the first PMOS transistor M11 in the IO driving power output unit is turned on, the first NMOS transistor M22 is turned off, and the first bias selection switch 160 is controlled by the CCNH signal and is in an off state, so that the first PMOS transistor M11 works in a non-saturated state, and the output of the PAD is a non-constant current high voltage driving signal output by VDD after passing through the first PMOS transistor M11. When driven at a non-constant low voltage: the constant current control enable signal CCEN is a low level signal, the first driving inverter 110 receives the first logic control signal and outputs a high level signal, and the second driving inverter 210 receives the second logic control signal and outputs a high level signal; each device is in a corresponding working state according to the constant current control enabling signal, the low level signal output by the first driving inverter 110 and the low level signal output by the second driving inverter 210, at this time, the first PMOS transistor M11 in the IO driving power output unit is turned off, the first NMOS transistor M22 is turned on, and the second bias selection switch 260 is controlled by the CCNH signal and is in an off state, so that the first NMOS transistor M22 works in a non-saturated state, and the output of the PAD is a non-constant current low voltage driving signal input from VDD to the first NMOS transistor M22 through PAD.
The embodiment of the invention also provides a constant current driving IO chip, which comprises a chip main body and the constant current driving IO circuit in any embodiment. The chip main body outputs a first logic control signal, a second logic control signal and a constant current control enabling signal to the constant current driving IO circuit, and adjusts the first bias voltage signal and the second bias voltage signal to be in a high level state or a low level state according to the current driving mode. The constant current driving IO circuit outputs an IO driving signal according to the received constant current control enabling signal, the first logic control signal, the second logic control signal, the first bias voltage signal and the second bias voltage signal, so that the IO port is driven in a constant current driving mode. In this embodiment, the specific operation implementation process of the constant current driving IO circuit corresponds to the above embodiment by cross reference, and is not described herein.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present invention. Furthermore, embodiments of the invention and features of the embodiments may be combined with each other without conflict.

Claims (9)

1. A constant current drive IO circuit, comprising:
the P-type analog driver is used for receiving a constant current control enabling signal and a first logic control signal, receiving a first bias voltage signal according to the constant current control enabling signal, and outputting a first constant current control signal according to the constant current control enabling signal, the first bias voltage signal and the first logic control signal;
the N-type analog driver is used for receiving the constant current control enabling signal and the second logic control signal, receiving a second bias voltage signal according to the constant current control enabling signal, and outputting a second constant current control signal according to the constant current control enabling signal, the second bias voltage signal and the second logic control signal;
the IO driving power unit is used for receiving the first constant current control signal and the second constant current control signal and outputting an IO driving signal;
the P-type analog driver comprises a first driving inverter, a P-end inverter unit, a P-end control transmission gate unit, a P-end slew rate inverter unit, a P-end slew rate transmission gate unit and a first bias selection switch unit;
the first drive inverter is configured to receive the first logic control signal;
The output end of the first driving inverter is respectively connected with the input end of the P-end inverter unit, the first input end of the P-end slew rate transmission gate unit and the first input end of the P-end slew rate inverter unit, the output end of the P-end inverter unit is respectively connected with the first input end of the P-end control transmission gate unit, the second input end of the P-end slew rate inverter unit and the second input end of the P-end slew rate transmission gate unit, the second input end, the third input end and the fourth input end of the P-end control transmission gate unit are controlled by the constant current control enabling signal, the output end of the P-end control transmission gate unit is connected with the third input end of the P-end slew rate inverter unit, the first output end of the P-end slew rate inverter unit is respectively connected with the first input end of the IO driving power unit and the third input end of the P-end slew rate transmission gate unit, and the second output end of the P-end control transmission gate unit is connected with the fourth input end of the P-end slew rate transmission gate unit;
the first bias selection switch is connected with a fourth input end of the P-end slew rate transmission gate unit and is used for sending the first bias voltage signal to the P-end slew rate transmission gate unit according to the constant current control enabling signal.
2. The constant current drive IO circuit of claim 1 wherein the IO drive power unit comprises a first PMOS tube and a first NMOS tube;
the drain electrode of the first PMOS tube is respectively connected with the drain electrode of the first NMOS tube and the output end of the IO drive power unit, the grid electrode of the first PMOS tube receives the first constant current control signal, the grid electrode of the first NMOS tube is used for receiving the second constant current control signal, the source electrode of the first PMOS tube is connected with the circuit power supply high potential end VDD, and the source electrode of the first NMOS tube is connected with the circuit low potential end VSS;
the first PMOS tube and the first NMOS tube are respectively controlled by the first constant current control signal and the second constant current control signal and used for outputting the IO driving signal.
3. The constant current driving IO circuit of claim 1 wherein the N-type analog driver includes a second driving inverter, an N-terminal inverter unit, an N-terminal control transmission gate unit, an N-terminal slew rate inverter unit, an N-terminal slew rate transmission gate unit, and a second bias selection switch unit;
the second drive inverter is configured to receive the second logic control signal;
the output end of the second driving inverter is respectively connected with the input end of the N-end inverter unit, the first input end of the N-end slew rate inverter unit and the first input end of the N-end slew rate transmission gate unit, the output end of the N-end inverter unit is respectively connected with the first input end of the N-end control transmission gate unit, the second input end of the N-end slew rate inverter unit and the second input end of the N-end slew rate transmission gate unit, the second input end, the third input end and the fourth input end of the N-end control transmission gate unit are controlled by the constant current control enabling signal, the output end of the N-end control transmission gate unit is connected with the third input end of the N-end slew rate inverter unit, the first output end of the N-end slew rate inverter unit is connected with the third input end of the N-end slew rate transmission gate unit, and the second output end of the N-end slew rate inverter unit is respectively connected with the second input end of the IO driving power unit and the fourth input end of the N-end slew rate transmission gate unit;
The second bias selection switch is connected with a third input end of the N-end slew rate control transmission gate unit and is used for sending the second bias voltage signal to the N-end slew rate control transmission gate unit according to the constant current control enabling signal.
4. The constant current driving IO circuit of claim 3 wherein the P-terminal inverter unit comprises a second PMOS transistor and a second NMOS transistor, and the N-terminal inverter unit comprises a third PMOS transistor and a third NMOS transistor;
the grid electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the second PMOS tube is connected with the circuit power supply high potential end VDD, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is connected with the circuit low potential end VSS, the grid electrode of the second PMOS tube is the input end of the P-end inverter unit, and the drain electrode of the second PMOS tube is the output end of the P-end inverter unit;
the grid electrode of the third PMOS tube is connected with the grid electrode of the third NMOS tube, the source electrode of the third PMOS tube is connected with the circuit power supply high potential end VDD, the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, the source electrode of the third NMOS tube is connected with the circuit low potential end VSS, the grid electrode of the third PMOS tube is the input end of the N-terminal inverter unit, and the drain electrode of the third PMOS tube is the output end of the N-terminal inverter unit.
5. The constant current driving IO circuit of claim 4 wherein the P-terminal control transmission gate unit comprises a fourth PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor, and the N-terminal control transmission gate unit comprises a fifth PMOS transistor, a sixth PMOS transistor, and a sixth NMOS transistor;
the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is respectively connected with the source electrode of the fourth PMOS tube and the drain electrode of the fifth NMOS tube, the source electrode of the fifth NMOS tube is connected with the circuit low potential end VSS, the drain electrode of the fourth NMOS tube is the first input end of the P-end control transmission gate unit, and the source electrode of the fourth NMOS tube is the output end of the P-end control transmission gate unit; the grid of the fourth NMOS tube is a second input end of the P-end control transmission gate unit and is controlled by an inversion signal of the constant current control enabling signal; the gate of the fifth NMOS tube is a third input end of the P-end control transmission gate unit and is controlled by the constant current control enabling signal; the grid of the fourth PMOS tube is a fourth input end of the P-end control transmission gate unit and is controlled by the constant current control enabling signal;
The drain electrode of the fifth PMOS tube is connected with the drain electrode of the sixth NMOS tube, the source electrode of the sixth NMOS tube is respectively connected with the source electrode of the fifth PMOS tube and the drain electrode of the sixth PMOS tube, the source electrode of the sixth PMOS tube is connected with the circuit power supply high potential end VDD, and the drain electrode of the sixth NMOS tube is the first input end of the N-end control transmission gate unit; the grid of the sixth NMOS tube is a second input end of the N-terminal control transmission gate unit and is controlled by an inversion signal of the constant current control enabling signal; the grid of the sixth PMOS tube is a third input end of the N-end control transmission gate unit and is controlled by an inversion signal of the constant current control enabling signal; the grid of the fifth PMOS tube is a fourth input end of the N-end control transmission gate unit and is controlled by the constant current control enabling signal; and the source of the sixth NMOS tube is the output end of the N-terminal control transmission gate unit.
6. The constant current driving IO circuit of claim 4 or 5 wherein the P-side slew rate inverter unit comprises a seventh PMOS transistor, an eighth PMOS transistor, and a seventh NMOS transistor, and the N-side slew rate inverter unit comprises a ninth PMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor;
The source electrode and the substrate of the seventh PMOS tube are connected with a circuit power supply high-potential end VDD, the drain electrode of the seventh PMOS tube is connected with the source electrode of the eighth PMOS tube, the substrate of the eighth PMOS tube is connected with the circuit power supply high-potential end VDD, the drain electrode of the eighth PMOS tube is connected with the drain electrode of the seventh NMOS tube, the source electrode of the seventh NMOS tube is connected with a circuit low-potential end VSS, the gate electrode of the eighth PMOS tube is a first input end of the P-end slew rate inverter unit, the gate electrode of the seventh PMOS tube is a second input end of the P-end slew rate inverter unit, the gate electrode of the seventh NMOS tube is a third input end of the P-end slew rate inverter unit, the drain electrode of the seventh PMOS tube is a first output end of the P-end slew rate inverter unit, and the drain electrode of the eighth PMOS tube is a second output end of the P-end slew rate inverter unit;
the source electrode and the substrate of the ninth PMOS tube are connected with a circuit power supply high potential end VDD, the drain electrode of the ninth PMOS tube is connected with the drain electrode of the eighth NMOS tube, the source electrode of the eighth NMOS tube is connected with a circuit low potential end VSS, the gate electrode of the eighth NMOS tube is a first input end of the N-end slew rate inverter unit, the gate electrode of the ninth NMOS tube is a second input end of the N-end slew rate inverter unit, the gate electrode of the ninth PMOS tube is a third input end of the N-end slew rate inverter unit, the drain electrode of the ninth PMOS tube is a first output end of the N-end slew rate inverter unit, and the drain electrode of the ninth NMOS tube is a second output end of the N-end slew rate inverter unit.
7. The constant current driving IO circuit of claim 6 wherein the P-side slew rate transmission gate unit comprises a tenth PMOS transistor and a tenth NMOS transistor, and the N-side slew rate transmission gate unit comprises an eleventh PMOS transistor and an eleventh NMOS transistor;
the drain electrode of the tenth PMOS tube is connected with the drain electrode of the tenth NMOS tube, the substrate of the tenth PMOS tube is connected with the circuit power supply high potential end VDD, the source electrode of the tenth PMOS tube is connected with the source electrode of the tenth NMOS tube, the gate electrode of the tenth PMOS tube is the first input end of the P-end slew rate transmission gate unit, the gate electrode of the tenth NMOS tube is the second input end of the P-end slew rate transmission gate unit, the source electrode of the tenth PMOS tube is the third input end of the P-end slew rate transmission gate unit, and the drain electrode of the tenth PMOS tube is the fourth input end of the P-end slew rate transmission gate unit;
the drain electrode of the eleventh PMOS tube is connected with the drain electrode of the eleventh NMOS tube, the substrate of the eleventh PMOS tube is connected with the circuit power supply high potential end VDD, the source electrode of the eleventh PMOS tube is connected with the source electrode of the eleventh NMOS tube, the gate electrode of the eleventh NMOS tube is the first input end of the N-end slew rate transmission gate unit, the gate electrode of the eleventh PMOS tube is the second input end of the N-end slew rate transmission gate unit, the drain electrode of the eleventh PMOS tube is the third input end of the N-end slew rate transmission gate unit, and the source electrode of the eleventh PMOS tube is the fourth input end of the N-end slew rate transmission gate unit.
8. The constant current drive IO circuit according to claim 1 or 2, wherein the constant current drive IO circuit further comprises a bias voltage generating circuit;
the bias voltage generating circuit is used for outputting a first bias voltage signal and a second bias voltage signal.
9. A constant current driving IO chip comprising a chip body and the constant current driving IO circuit according to any one of claims 1 to 8;
the chip main body is connected with the constant current driving IO circuit, and outputs a first logic control signal, a second logic control signal and a constant current control enabling signal to the constant current driving IO circuit.
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