CN115941179B - Method for realizing password conversion on ASIC chip - Google Patents
Method for realizing password conversion on ASIC chip Download PDFInfo
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Abstract
The invention relates to the technical field of password conversion, in particular to a method for realizing password conversion on an ASIC chip. The method comprises the steps of setting a password change overall flow, storing password transformation rules, constructing a password transformation model, realizing a password rule command transformation function according to the password transformation model and realizing a plurality of rule command continuous transformation functions by using a multi-stage pipeline. The invention effectively reduces the huge difference between the password transmission speed and the calculation speed by using rule transformation; under the condition of the same calculated amount, the bandwidth occupied by password input is greatly reduced, and the communication pressure in the working process of the chip can be effectively relieved; meanwhile, the flexibility of using the password dictionary is improved, and the success rate of password decoding can be remarkably improved.
Description
Technical Field
The invention relates to the technical field of password conversion, in particular to a method for realizing password conversion on an ASIC chip.
Background
The password decoding is an important group branch of password decoding, most of encryption keys are obtained by directly or indirectly calculating the password at present, and an ASIC chip is used for realizing the password decoding function, so that the method has a series of advantages of high integration level, high decoding speed, low power consumption and the like; but is limited by the limitations of chip area, power consumption, design complexity and the like, and the problems of insufficient flexibility of using passwords, overlarge gap between password transmission speed and calculation speed and the like exist in the chip.
In the software layer, the input passwords are subjected to programmable rule transformation, and assuming that the number of rules is N, each input password can generate N new passwords which have the same basic information but play an important role in actual password decoding: the password decoding rate is effectively improved under the condition of increasing a certain calculated amount.
The rule conversion function is realized on the ASIC password decoding chip, firstly, the gap between password transmission and calculation speed is relieved; secondly, the flexibility of password decoding application is expanded; thirdly, the bandwidth required by password transmission is reduced, and the actually generated password quantity is N times of the password transmission quantity assuming that N rules are transmitted.
Disclosure of Invention
The present invention is directed to a method for implementing password transformation on an ASIC chip to solve the above-mentioned problems set forth in the background art.
To achieve the above object, there is provided a method for implementing password conversion on an ASIC chip, including the steps of:
s1, making a password change overall flow;
s2, storing password transformation rules;
s3, constructing a password transformation model;
s4, realizing a password rule command conversion function according to the password conversion model;
s5, a multi-stage pipeline is used for realizing a plurality of rule command continuous conversion functions.
As a further improvement of the present technical solution, the method for making a procedure in S1 includes the following steps:
s1.1, inputting the number of rules and storing the input rules;
s1.2, inputting an initial password, and carrying out password change according to an input rule;
s1.3, judging whether the password is processed or not, and generating a transformation password after the initial password is processed;
s1.4, judging whether the rule is changed, forming a new rule after the change is completed, and changing the initial password according to the new rule.
As a further improvement of the present technical solution, the storage method for storing the password transformation rule in S2 is as follows:
s2.1, formulating corresponding rules;
s2.2, the chip formulates a corresponding register for storing a corresponding rule.
As a further improvement of the technical scheme, the S3 construction password transformation model construction method comprises the following steps:
s3.1, defining a password conversion command;
s3.2, combining password conversion commands to generate new rules.
As a further improvement of the present technical solution, the step of defining the password transformation command definition rule in S3.1 is as follows:
s3.1.1 naming the command of password transformation;
s3.1.2, formulating a corresponding password conversion command format;
s3.1.3, formulating a corresponding input password;
s3.1.4, formulating a corresponding output password.
As a further improvement of the technical scheme, the implementation method for realizing the password rule command conversion function according to the password conversion model in the S4 comprises the following steps:
s4.1, determining a corresponding logic module according to each rule;
s4.2, storing an input password, outputting the password to a register, and storing rules to another register;
s4.3, determining the upper limit of the number of commands supported by each rule according to the requirement.
As a further improvement of the present technical solution, the logic module in S4.1 includes command selection logic, password tail appended character logic, password tail deleted character logic, password head inserted character logic, password head deleted character logic, letter case conversion logic, designated character replacement logic, and password overall repeat logic.
As a further improvement of the technical scheme, the step of the rule command continuous transformation method in S5 is as follows:
s5.1, determining a rule transformation amount according to a command combination mode;
s5.2, removing rules with poor effects according to the instruction using effects, and adding new rules.
Compared with the prior art, the invention has the beneficial effects that:
1. in the method for realizing password conversion on the ASIC chip, the huge gap between the password transmission speed and the calculation speed is effectively reduced by using rule conversion; under the condition of the same calculated amount, the bandwidth occupied by password input is greatly reduced, and the communication pressure in the working process of the chip can be effectively relieved; meanwhile, the flexibility of using the password dictionary is improved, and the success rate of password decoding can be remarkably improved.
2. In the method for realizing password conversion on the ASIC chip, the corresponding rules are formulated, the input rules are specially stored by using the register in the chip, the rules are used for password conversion, and the rules can be updated at any time according to the scheduling requirement, so that the flexibility requirement is met; all the passwords can be kept unchanged before being processed, and the requirement of reducing the password transmission bandwidth is met.
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FIG. 1 is a flowchart illustrating the overall steps of the present invention;
FIG. 2 is a flow chart of a flow formulation method of the present invention;
FIG. 3 is a flow chart of a storage method of the present invention;
FIG. 4 is a flow chart of a method of constructing a password transformation model in accordance with the present invention;
FIG. 5 is a flowchart illustrating the steps of defining rules according to the present invention;
FIG. 6 is a flow chart of an implementation method of the present invention;
FIG. 7 is a flowchart illustrating steps of a rule command continuous conversion method according to the present invention;
FIG. 8 is an overall flow chart of the password transformation of the present invention.
Description of the embodiments
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-8, a method for implementing password transformation on an ASIC chip is provided, including the steps of:
s1, making a password change overall flow;
s2, storing password transformation rules;
s3, constructing a password transformation model;
s4, realizing a password rule command conversion function according to the password conversion model;
s5, a multi-stage pipeline is used for realizing a plurality of rule command continuous conversion functions.
When the method is specifically used, the whole process of password change is firstly formulated, batch rule change processing is carried out on batches of passwords through password change, new passwords are generated and provided for a computing core to use, a group of rules (supposing N) are input to a chip, the group of changes are completed for each input password, namely N new passwords are generated, password change rules are stored, a group of rules (supposing M) are input to the chip before the password change, and M rule change is carried out for each password, namely M times N new instructions are generated, meanwhile, M rules are stored through the chip, then a password change model is constructed, the password change is a process of carrying out one or more changes on the input passwords through programmable commands to generate new passwords, the commonly used password change commands are defined in advance, the rule change model can be directly called in the rule formulation process, the rule command change function is realized according to the password change model, each rule command corresponds to a logic module, the continuous change function of a plurality of rule commands is realized by using a multistage pipeline, the logic of circuit design can be simplified, the complex function is realized, and the frequency of circuit operation is improved.
The invention effectively reduces the huge difference between the password transmission speed and the calculation speed by using rule transformation; under the condition of the same calculated amount, the bandwidth occupied by password input is greatly reduced, and the communication pressure in the working process of the chip can be effectively relieved; meanwhile, the flexibility of using the password dictionary is improved, and the success rate of password decoding can be remarkably improved.
In addition, the method for making the procedure in S1 includes the following steps:
s1.1, inputting the number of rules and storing the input rules;
s1.2, inputting an initial password, and carrying out password change according to an input rule;
s1.3, judging whether the password is processed or not, and generating a transformation password after the initial password is processed;
s1.4, judging whether the rule is changed, forming a new rule after the change is completed, and changing the initial password according to the new rule.
When the method is specifically used, the number of rules is firstly formulated, an initial password is input, one rule change is carried out on each initial password, then whether the password is processed is judged, a new password is output after the processing is finished, rules are then changed, and rule change is carried out on the initial passwords until all the passwords are subjected to all the rule change.
Further, the storage method for storing the password conversion rule in S2 is as follows:
s2.1, formulating corresponding rules;
s2.2, the chip formulates a corresponding register for storing a corresponding rule.
When the device is specifically used, the register is used in the chip to specially store the input rules, and the rules are used for password conversion, can be updated at any time according to the scheduling requirement, and meet the flexibility requirement; all the passwords can be kept unchanged before being processed, and the requirement of reducing the password transmission bandwidth is met.
Still further, the S3 construction password transformation model construction method comprises the following steps:
s3.1, defining a password conversion command;
s3.2, combining password conversion commands to generate new rules.
The password transformation is a process of generating a new password by carrying out one or more changes on an input password through a programmable command, defining a group of common and good-effect password transformation commands by combining practical experience, storing the common password transformation commands, and directly calling rules only by inputting a single password transformation command or a plurality of password transformation commands in the programming process at the later stage, wherein in order to realize more complex rule transformation, the plurality of commands form a rule, all commands are sequentially executed in the execution process, and finally, transformation results, such as commands, are output: the transformation function of the additional character 'abcde' after the password is input is realized, and the model can realize complex rule transformation due to flexible and various combinations of command quantity and rules.
Specifically, the step of defining the password transformation command definition rule in S3.1 is as follows:
s3.1.1 naming the command of password transformation;
s3.1.2, formulating a corresponding password conversion command format;
s3.1.3, formulating a corresponding input password;
s3.1.4, formulating a corresponding output password.
In the process of defining the password conversion commands, firstly distinguishing each password conversion command, formulating a corresponding password conversion command format for the password conversion command, wherein each password conversion command is matched with one password conversion command format, the matched password conversion command can be called by inputting the password conversion command format, and then determining the input password and the output password according to the password conversion command, and storing and calling.
In addition, the implementation method for implementing the password rule command conversion function according to the password conversion model in S4 comprises the following steps:
s4.1, determining a corresponding logic module according to each rule;
s4.2, storing an input password, outputting the password to a register, and storing rules to another register;
s4.3, determining the upper limit of the number of commands supported by each rule according to the requirement.
In ASIC design, each rule command corresponds to a logic module, and the input password and the output port command are stored in a register; rules are stored in a set of registers, and the upper limit of the number of commands supported by each rule is determined as required.
Further, the logic modules in S4.1 include command select logic, password tail append character logic, password tail delete character logic, password head insert character logic, password head character delete logic, letter case conversion logic, replace specified character logic, and password whole repeat logic. Wherein:
command selection logic: selecting a corresponding logic module according to a command ($ [ ] ultsd) using a multiplexer (10 select 1);
password tail append character logic: shifting the character to be added according to the length of the input password (using a shift register), adding a designated character at the tail of the data by using a logic OR gate, and discarding the tail character when the result length reaches the upper limit;
deleting password tail character logic: according to the length of the input password, a logic AND gate is used for deleting the tail characters of the decoration data;
password first insert character logic: inserting characters in the password by using a shift register, and discarding the last character when the result length exceeds the limit;
deletion of password first character logic: implementing a command to delete the first character of the password using a shift register;
letter case conversion logic: for each input character, firstly judging whether the character is Latin letters or not, and then carrying out case-to-case conversion according to the command;
substitution of specified character logic: judging whether each character is a character to be replaced or not, if so, replacing the character with a new character, and using a comparator and a selector;
password overall repetition logic: the password is repeated in its entirety using a shift register and a logical OR gate, and when the result length exceeds the limit, the excess characters are discarded.
The password change command contrast is shown in the following table:
| command | Format of the form | Example | Entering a password | Outputting a password |
| Keeping the password unchanged | : | : | Abc1#Db | Abc1#Db |
| Appended character of password tail | Character $ | $a | Abc1#Db | Abc1#Dba |
| Deleting password tail characters | ] | ] | Abc1#Db | Abc1#D |
| Character insertion for password | Character of the letter | Character of the letter | Abc1#Db | aAbc1#Db |
| Deleting the first character of the password | [ | [ | Abc1#Db | bc1#Db |
| All letters becoming uppercase | u | u | Abc1#Db | ABC1#DB |
| All letters are lower case | l | l | Abc1#Db | abc1#db |
| All letter cases interconversion | t | t | Abc1#Db | aBC1#dB |
| Replacing specified characters | s old character and new character | sbX | Abc1#Db | AXc1#DX |
| Password overall repetition | d | d | Abc1#DbAbc1#DbAbc1#Db |
Password conversion command comparison table
Still further, the step of the rule command continuous conversion method in S5 is as follows:
s5.1, determining a rule transformation amount according to a command combination mode;
s5.2, removing rules with poor effects according to the instruction using effects, and adding new rules.
When the pipeline is full, a new password can be generated every clock cycle, while externally entering a password requires at least 300 clock cycles,in order to realize more complex rule transformation, a multi-stage pipeline is used in ASIC password rule transformation design, each stage pipeline can execute one rule command, when a 6-stage pipeline is used, 6 commands can be executed, namely each rule is formed by combining 6 commands at most, in the method, 6 commands are combined, 10 commands are combined, wherein the inserting and replacing commands imply more transformation cases (inserting different characters and combining replaced characters), and the realized password transformation rule exceeds 2 78 And the input rules are programmable, so that new rules can be continuously added and rules with poor effects can be deleted in the application process, and the method is convenient and flexible.
The foregoing has shown and described the basic principles, principal features and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments, and that the above-described embodiments and descriptions are only preferred embodiments of the present invention, and are not intended to limit the invention, and that various changes and modifications may be made therein without departing from the spirit and scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (5)
1. A method for implementing password transformation on an ASIC chip, comprising the steps of:
s1, making a password change overall flow;
s2, storing password transformation rules;
s3, constructing a password transformation model;
s4, realizing a password rule command conversion function according to the password conversion model;
s5, realizing a plurality of rule command continuous conversion functions by using a multi-stage pipeline;
the flow formulation method in S1 comprises the following steps:
s1.1, inputting the number of rules and storing the input rules;
s1.2, inputting an initial password, and carrying out password change according to an input rule;
s1.3, judging whether the password is processed or not, and generating a transformation password after the initial password is processed;
s1.4, judging whether the rule is changed, forming a new rule after the change is completed, and changing the initial password according to the new rule;
the storage method for storing the password conversion rule in the S2 is as follows:
s2.1, formulating corresponding rules;
s2.2, the chip formulates a corresponding register for storing a corresponding rule;
the implementation method for realizing the command conversion function of the password rule according to the password conversion model in the S4 comprises the following steps:
s4.1, determining a corresponding logic module according to each rule;
s4.2, storing an input password, outputting the password to a register, and storing rules to another register;
s4.3, determining the upper limit of the number of commands supported by each rule according to the requirement.
2. The method of implementing password transformation on an ASIC chip as recited in claim 1, wherein: the S3 construction password transformation model construction method comprises the following steps:
s3.1, defining a password conversion command;
s3.2, combining password conversion commands to generate new rules.
3. The method of implementing password transformation on an ASIC chip as recited in claim 2, wherein: the step of defining the password transformation command definition rule in the step S3.1 is as follows:
s3.1.1 naming the command of password transformation;
s3.1.2, formulating a corresponding password conversion command format;
s3.1.3, formulating a corresponding input password;
s3.1.4, formulating a corresponding output password.
4. The method of implementing password transformation on an ASIC chip as recited in claim 1, wherein: the logic module in S4.1 includes command selection logic, password tail append character logic, password tail character deletion logic, password head insert character logic, password head character deletion logic, letter case conversion logic, specified character replacement logic, and password overall repeat logic.
5. The method of implementing password transformation on an ASIC chip as recited in claim 1, wherein: the step of the rule command continuous conversion method in the S5 is as follows:
s5.1, determining a rule transformation amount according to a command combination mode;
s5.2, removing rules with poor effects according to the instruction using effects, and adding new rules.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101102192A (en) * | 2007-07-18 | 2008-01-09 | 北京飞天诚信科技有限公司 | Authentication device, method and system |
| CN106559222A (en) * | 2016-11-28 | 2017-04-05 | 广东省信息安全测评中心 | Target password rule set acquisition methods and system in method of exhaustion decryption |
| CN111786796A (en) * | 2020-07-02 | 2020-10-16 | 南开大学 | Password strength evaluation method based on password reuse, character jump and separation |
| CN115242450A (en) * | 2022-06-23 | 2022-10-25 | 北卡科技有限公司 | Password data input method, device and storage medium |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6397337B1 (en) * | 1998-04-30 | 2002-05-28 | Compaq Computer Corporation | Unified password prompt of a computer system |
| CA2490873C (en) * | 2003-12-29 | 2009-02-17 | Bruno Lambert | Enhanced pin and password protection system and method |
| CN107154851B (en) * | 2017-06-30 | 2020-09-08 | 上海众人网络安全技术有限公司 | Data encryption and decryption method and device |
| CN112016083B (en) * | 2020-10-30 | 2021-01-12 | 之江实验室 | Password transformation rule induction method based on intelligent clustering |
| CN115114613B (en) * | 2022-08-26 | 2022-11-29 | 大有信创(北京)科技有限公司 | System for password cracking by using ASIC and GPU heterogeneous type resources |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101102192A (en) * | 2007-07-18 | 2008-01-09 | 北京飞天诚信科技有限公司 | Authentication device, method and system |
| CN106559222A (en) * | 2016-11-28 | 2017-04-05 | 广东省信息安全测评中心 | Target password rule set acquisition methods and system in method of exhaustion decryption |
| CN111786796A (en) * | 2020-07-02 | 2020-10-16 | 南开大学 | Password strength evaluation method based on password reuse, character jump and separation |
| CN115242450A (en) * | 2022-06-23 | 2022-10-25 | 北卡科技有限公司 | Password data input method, device and storage medium |
Non-Patent Citations (1)
| Title |
|---|
| 安全口令生成器的设计与实现;马刚勇;权建校;韩文报;;信息安全与通信保密(10);103-104 * |
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Denomination of invention: A Method for Implementing Password Transformation on ASIC Chips Effective date of registration: 20231008 Granted publication date: 20230516 Pledgee: Ji'nan finance Company limited by guarantee Pledgor: Shandong Rongan Intelligent Technology Co.,Ltd. Registration number: Y2023980060284 |