CN115940902A

CN115940902A - Switching circuit

Info

Publication number: CN115940902A
Application number: CN202211741133.5A
Authority: CN
Inventors: 张鑫; 翟源宏
Original assignee: Guangzhou Huizhi Microelectronics Co ltd
Current assignee: Guangzhou Huizhi Microelectronics Co ltd
Priority date: 2022-12-31
Filing date: 2022-12-31
Publication date: 2023-04-07

Abstract

The application provides a switching circuit, which comprises a switching module; the switch module comprises a first transistor and a second transistor which are cascaded, wherein a source electrode or an emitter electrode of the first transistor is used for being connected with a power supply, and a drain electrode or a collector electrode of the first transistor is connected with a source electrode or an emitter electrode of the second transistor; when the first transistor is closed and opened, providing a first bias signal to a grid electrode or a base electrode of the second transistor so as to limit the voltage of a drain electrode or a collector electrode of the first transistor; and after the first transistor is started, providing a second bias signal to a grid electrode or a base electrode of the second transistor so as to enable the second transistor to work in a linear region or a saturation region.

Description

Switching circuit

Technical Field

The present application relates to the field of integrated circuits, and relates to, but is not limited to, a switching circuit.

Background

In the field of integrated circuits, switching circuits are often required for controlling the current path. For example, in a Radio Frequency Front-End (RFFE) circuit, a path of current is used to bias a plurality of modules, and the flow direction of the bias current is controlled by switching a switch circuit. In mobile device battery systems, the supply Voltage (VBAT) is typically 3.1-4.8V, while the withstand voltage of the transistor is typically 2.5V. Since the voltage at the input of the switching circuit may be as high as the supply voltage VBAT and the voltage at the output may be as low as ground (VSS), there may be a risk of overvoltage if only one transistor M1 is used as the switching tube. Therefore, in the related art, in order to prevent the device from being over-pressurized, a transistor M2 is added to prevent the over-pressurization.

However, as the power supply voltage changes, the operating states of M1 and M2 may change, and M2 may even change between the linear region and the saturation region, so that the impedance seen from the output terminal may change significantly. This is unacceptable in many cases, such as in rf front end applications, where impedance variations at the switching circuit can significantly affect rf performance.

Disclosure of Invention

In order to solve the above problems in the prior art, an embodiment of the present application provides a switching circuit.

The embodiment of the application provides a switching circuit, which comprises a switching module, wherein the switching module comprises a first transistor and a second transistor which are cascaded, a source electrode or an emitter electrode of the first transistor is used for being connected with a power supply, and a drain electrode or a collector electrode of the first transistor is connected with a source electrode or an emitter electrode of the second transistor; when the first transistor is closed and opened, providing a first bias signal to a grid electrode or a base electrode of the second transistor so as to limit the voltage of a drain electrode or a collector electrode of the first transistor; and after the first transistor is started, providing a second bias signal to a grid electrode or a base electrode of the second transistor so as to enable the second transistor to work in a linear region or a saturation region.

The technical scheme provided by the application at least has the following technical effects and advantages:

the switching circuit provided by the embodiment of the application comprises a switching module, wherein the switching module comprises a first transistor and a second transistor which are cascaded, a source electrode or an emitter electrode of the first transistor is used for being connected with a power supply, and a drain electrode or a collector electrode of the first transistor is connected with a source electrode or an emitter electrode of the second transistor; when the first transistor is closed and opened, providing a first bias signal to a grid electrode or a base electrode of the second transistor so as to limit the voltage of a drain electrode or a collector electrode of the first transistor; after the first transistor is started, providing a second bias signal to a grid electrode or a base electrode of the second transistor so as to enable the second transistor to work in a linear region or a saturation region; therefore, on one hand, the first transistor is protected by introducing the cascaded second transistor, and the overvoltage effect of the first transistor is avoided; on the other hand, the base voltage or the grid voltage of the second transistor is adjusted through the second bias signal, so that the impedance seen from two ends of the switch circuit is insensitive to the change of the power supply voltage, and the radio frequency performance reduction caused by the change of the impedance of the switch circuit is reduced.

Drawings

Fig. 1A is a schematic diagram of a basic principle of a current switch provided in the related art;

fig. 1B is a schematic circuit diagram of a current switch provided in the related art;

fig. 2 is an alternative structural schematic diagram of a switching circuit provided in an embodiment of the present application;

fig. 3 is an alternative structural schematic diagram of a switching circuit provided in an embodiment of the present application;

fig. 4A is an alternative schematic structure diagram of a switch circuit according to an embodiment of the present disclosure

Fig. 4B is an alternative structural schematic diagram of a switch circuit provided in an embodiment of the present application

Fig. 5 is an alternative circuit configuration diagram of a switching circuit provided in an embodiment of the present application;

FIG. 6A is a timing diagram of logic signals of the switch circuit according to the present application;

fig. 6B is a timing diagram of another logic signal of the switch circuit according to the embodiment of the present disclosure.

Detailed Description

In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

In the field of integrated circuits, current switches are often required for controlling the current path. For example, in an rf front end circuit, a current is used to bias a plurality of modules, and the current switch is switched to control the flow direction of the bias current. As shown in fig. 1A, the basic principle of the current switch is: the control signal (CTRL) controls the on or off of the switch circuit connected with the input end (Iin end) and the output end (Iout end), so that the passage is opened or closed. The current switch should effectively break the path when closed, while not changing the circuit characteristics seen across when open.

In a mobile device battery system, the power supply Voltage (VBAT) is typically 3.1-4.8V, while the withstand voltage of the MOS transistor is typically 2.5V. As shown in fig. 1B, since the voltage at the input terminal (Iin terminal) of the current switch may be as high as the power voltage, and the voltage at the output terminal (Iout terminal) may be as low as ground (VSS), if there is only one MOS transistor, i.e. M1, there is a risk of over-voltage, because the source-drain voltage difference is greater than 2.5V.

Therefore, in order to prevent the device from being over-voltage, a MOS transistor, i.e. M2, is usually added to prevent the over-voltage, in this case, the transistor M1 is a switching transistor, and M2 is an anti-overvoltage transistor, which is used to limit the voltage Va at the point a, and Va = VB + Vth (the turn-on voltage of M2). A voltage VB is generated within VBAT to bias the GATE voltage of the M2 device (M2 _ GATE).

Take a circuit for biasing a Heterojunction Bipolar Transistor (HBT) stage in an rf front end as an example. In a conventional current switch, as shown in fig. 1B, M1 is turned on and off by the CTRL signal, and operates in a switching state. When CTRL is "1", M1_ GATE = VBAT, M1 is off, and when CTRL is "0", M1_ GATE = VB, M1 is on. Due to the existence of M2, the voltage at the point A can be kept near VB, and further, the M1, the M2 and the M3 can be ensured not to be over-voltage. In fig. 1B, M3 and M4 are current mirrors providing inputs to Iin, which can also be understood as a current source. The Iout terminal is used for providing bias current for the amplifier.

However, as the power supply voltage VBAT changes, the operating states of M1 and M2 may change, and M2 may even change between the linear region and the saturation region, so that the impedance seen from the Iout terminal changes significantly. This is unacceptable in many cases, such as in rf front end applications, where impedance variations at the current switch can significantly affect rf performance.

Fig. 2 is an alternative structural schematic diagram of a switching circuit provided in an embodiment of the present application, as shown in fig. 2, the switching circuit includes a switching module SW,

the switch module SW comprises a first transistor T1 and a second transistor T2 which are cascaded, wherein a source or an emitter of the first transistor T1 is used for connecting a power supply VBAT, and a drain or a collector is connected with a source or an emitter of the second transistor T2;

when the first transistor T1 is turned off and on, a first bias signal bias1 is provided to the gate or base of the second transistor T2 to limit the voltage of the drain or collector of the first transistor T1;

after the first transistor T1 is turned on, a second bias signal bias2 is provided to the gate or the base of the second transistor T2, so that the second transistor T2 operates in a linear region or a saturation region.

In the embodiment of the present application, the first transistor T1 and the second transistor T2 may be both bipolar transistors; or may be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and the embodiments of the present application are not limited thereto.

When the first transistor T1 and the second transistor T2 are bipolar transistors, the second bias signal is used for keeping the second transistor T2 operating in a saturation region; when the first transistor T1 and the second transistor T2 are field effect transistors, the second bias signal is used to keep the second transistor T2 operating in a linear region.

In the embodiment of the present application, the first bias signal may be a voltage signal or a current signal related to the power supply voltage, for example, the power supply voltage minus the maximum withstand voltage of the first transistor of 2.5V or half of the power supply voltage. The second bias signal is a voltage signal or a current signal independent of the power supply voltage, for example 0V or 1V or the like. Since the second bias signal is not related to the supply voltage, the second transistor remains in the linear region or the saturation region, and since the first transistor remains in the linear region after being turned on, the impedance seen across the current switch is constantly a small resistance of the two switches connected in series.

Aiming at the condition that the second transistor T2 is an MOS transistor, after the T1 is started, a second bias signal bias2 is provided to the grid electrode of the MOS transistor T2, so that the MOS transistor T2 works in a linear region; for the case that the second transistor T2 is a triode, after T1 is turned on, a second bias signal bias2 is provided to the base of the second transistor T2, so that the triode T2 operates in a saturation region.

On one hand, the first transistor is protected by introducing the cascaded second transistor, and the overvoltage effect of the first transistor is avoided; on the other hand, the base voltage or the grid voltage of the second transistor is adjusted through the second bias signal, so that the impedance seen from two ends of the switch circuit is insensitive to the change of the power supply voltage, and the radio frequency performance reduction caused by the impedance change of the switch circuit is reduced.

In some embodiments of the present application, when the second transistor is a P-type transistor, that is, a P-type MOS transistor or a PNP transistor, the first bias signal is greater than the second bias signal; when the second transistor is an N-type transistor, i.e., an N-type MOS transistor or an NPN transistor, the first bias signal is smaller than the second bias signal.

In some embodiments of the present application, after the first transistor is turned on, a third bias signal is provided to a gate or a base of the first transistor, so that the first transistor keeps operating in a linear region or a saturation region. In some embodiments, the third bias signal is the same as the second bias signal, for example, a ground voltage VSS or a fixed voltage less than a certain value, such as 1V.

In some embodiments of the present application, the switching circuit further comprises a first current mirror and/or a second current mirror, wherein: the first current mirror is respectively connected with the power supply and the input end of the switch module and is used for providing current input for the switch module; and the second current mirror is connected with the output end of the switch module and used for outputting bias current. In some embodiments, the first current mirror may be formed by a pair of transistors T3 and T4, which may also be understood as a current source. In some embodiments, the Iout terminal of the switch circuit is used to provide a bias current for the amplifier, wherein the bias current for the amplifier can be provided directly or can be provided to the amplifier through a bias Heterojunction Bipolar Transistor (HBT) to form a second current mirror.

In some embodiments of the present application, as shown in fig. 3, the switch module SW further includes a first branch X1 and a second branch X2 connected to a gate or a base of the second transistor T2, and when the gate or the base of the second transistor is connected to the first branch X1, the gate or the base of the second transistor T2 obtains the first Bias signal Bias1; when the gate or the base of the second transistor is connected to the second branch X2, the gate or the base of the second transistor T2 obtains the second Bias signal Bias2.

In the above embodiment, the first branch X1 and the second branch X2 may be implemented by a single-pole double-throw switch, or may be implemented by two switches, and at this time, the switching between the first branch X1 and the second branch X2 may be implemented by controlling by other possible control circuits, which is not limited in this embodiment of the present application.

In some embodiments, the first branch X1 comprises a second switch connected in series in the first branch X1, and the second branch X2 comprises a fourth switch connected in series in the second branch X2; when the second switch is closed and the fourth switch is opened, the gate or the base of the second transistor T2 obtains the first Bias signal Bias1; when the second switch is turned off and the fourth switch is turned off, the gate or the base of the second transistor T2 obtains the second Bias signal Bias2.

In some embodiments of the present application, as shown in fig. 3, the switch module SW further includes a third branch X3 and a fourth branch X4 connected to the base or gate of the first transistor T1, and when the gate or base of the first transistor T1 is connected to the third branch X3, the gate or base of the first transistor T1 obtains the third Bias signal Bias3; when the gate or the base of the first transistor T1 is connected to the fourth branch X4, the gate or the base of the first transistor T1 obtains a fourth Bias signal Bias4. The first branch X1 and the second branch X2 may be implemented by a single-pole double-throw switch, or may be implemented by two switches, and at this time, the switching between the first branch X1 and the second branch X2 may be implemented by other possible control circuits, which is not limited in this embodiment of the application.

In some embodiments, the third branch X3 includes a third switch connected in series in the third branch X3, and the fourth branch X4 includes a first switch connected in series in the fourth branch X4; when the first switch is closed and the third switch is opened, the gate or the base of the first transistor T1 obtains the fourth Bias signal Bias4; when the first switch is turned off and the third switch is turned off, the gate or the base of the first transistor acquires the third Bias signal Bias3.

It should be noted that, when the first transistor T1 is turned off, the gate or the base of the first transistor T1 is connected to the fourth branch X4, and the gate of the second transistor T2 is connected to the second branch X2, at this time, the entire switching circuit is in an off state, and the voltage passing through the first transistor is limited by the second transistor T2; after the first transistor T1 is turned on and the normal operation of the switch circuit is detected, the grid or the base of the first transistor T1 is switched to be connected to the third branch X3, the grid of the second transistor T2 is connected to the first branch X1, and the switch circuit is kept in an on state. At this time, since the third bias signal and the second bias signal are not related to VBat, the first transistor T1 and the second transistor T2 are both kept in a linear region, and thus the impedance seen from both ends of the current switch is constantly a small resistance of two switches connected in series.

In some embodiments of the present application, the switching circuit further comprises a control circuit that controls the switching branch; and/or the control circuit further comprises a logic detection circuit connected with the switch module and used for detecting the working voltage of the output end of the switch module so as to enable the control circuit to switch the branch of the switch module according to the working voltage. In some embodiments, the control circuit comprises at least one of an or gate, an and gate, a not gate, a nand gate, and a nor gate, different enable signals are generated by the system control signal, the gate or base of the first transistor is switched to be connected to different branches, and the gate or base of the first transistor and the second transistor is connected to corresponding bias signals; in some embodiments, the control circuit is connected with a detection circuit, and the detection circuit detects the operating voltage at the output end of the switch module and feeds the operating voltage back to the control circuit, so as to switch the branches of the switch module by using the control circuit. The detection circuit may be implemented using a schmitt trigger (schmitt trigger). When the voltage at the output end Iout reaches a set value, a V _ detect signal is output and is juxtaposed to be 1.

In some embodiments of the present application, the switch module further comprises a level shifting circuit located within the first branch: the level shift circuit is connected with the grid electrode or the base electrode of the first transistor through the first switch, and is used for providing the fourth bias signal for the grid electrode or the base electrode of the first transistor when the first transistor is closed and also used for providing the fifth bias signal for the grid electrode or the base electrode of the first transistor when the first transistor is opened; the fifth bias signal is lower than the fourth bias signal.

The circuit shifting circuit may be a level shifter (level shifter), and may receive a system control signal CTRL and generate a control signal between a power supply voltage and a certain bias voltage based on the control signal. Generating a fourth bias signal if the control signal CTRL is in a first level state; if the control signal CTRL is in the second level state, a fifth bias signal is generated. Here, the first level state may be understood as a high level "1", and the corresponding level is VBAT or near VBAT, and the second level state may be understood as a low level "0", and the corresponding level is a specific bias voltage VB.

In some embodiments of the present application, the fourth bias signal is a supply voltage, and the fifth bias signal is the same as the first bias signal. Therefore, when the first transistor is turned off, the grid voltage or the base voltage of the first transistor is pulled up to the power supply voltage, and after the first transistor is turned on, the grid voltage or the base voltage of the first transistor is pulled down to a certain bias voltage, so that the first transistor and the second transistor work in a linear region.

In some embodiments of the present application, the fourth bias signal is a power supply voltage, and the fifth bias signal slowly decreases with an on-time. The fifth bias signal slowly decreases with the turn-on time, so that the pull-down speed of the gate voltage or the base voltage of the first transistor can be reduced.

In some embodiments of the present application, the switch module further comprises a first bias circuit, a second bias circuit and a third bias circuit connected to a gate or a base of the first transistor, the first bias circuit for providing the first bias signal to the first transistor; the second bias circuit is used for acquiring the first bias signal and controlling the state of the third bias circuit; the third bias circuit is configured to provide a power supply voltage or the second bias signal to the first transistor.

The first bias circuit comprises at least one resistor and at least one transistor which are cascaded, and a first bias signal related to the power supply voltage can be obtained by setting a proper resistance value and a proper transistor size, for example, the voltage of the first bias signal is half of the power supply voltage. The second bias circuit is similar to the first bias circuit,

in some embodiments, the first bias circuit, the second bias circuit, and the third bias circuit have respective input terminals connected to a power supply voltage and respective output terminals connected to a ground voltage. The first bias circuit is used for generating a first bias signal according to the power supply voltage.

In some embodiments, by designing the transistor size to be proper, the transistor in the second bias circuit and the transistor in the first bias circuit are symmetric two by two, and under the condition that the second bias circuit is turned on and the third bias circuit is turned off, the second bias circuit can obtain the first bias signal generated by the first bias circuit.

In some embodiments, the third bias circuit includes at least two transistors connected in series, a gate or a base of each transistor is used for receiving a corresponding enable signal, and each enable signal is controlled to be at a high level or a low level to control the corresponding transistor to be turned off or turned on, so that the third bias circuit pulls up a gate voltage or a base voltage of the first transistor to the power supply voltage or pulls down the gate voltage or the base voltage to a voltage corresponding to the second bias signal under different conditions.

Fig. 4A is an alternative structural schematic diagram of the switch circuit provided in the embodiment of the present application, and as shown in fig. 4A, the first bias circuit 41 includes a third resistor R3, a fifth transistor (M5), a sixth transistor (M6), a seventh transistor (M7), an eighth transistor (M8), and a second resistor R2, which are sequentially cascaded; the second bias circuit 42 comprises a ninth transistor (M9), a tenth transistor (M10), an eleventh transistor (M11), a twelfth transistor (M12), a thirteenth transistor (M13) and a fourteenth transistor (M14) which are connected in series; the third bias circuit 43 comprises a fifteenth transistor (M15), a sixteenth transistor (M16), a seventeenth transistor (M17) and an eighteenth transistor (M18) which are connected in series in sequence; a first terminal of the third resistor (R3), a first terminal of the ninth transistor (M9), and a first terminal of the fifteenth transistor (M15) are all connected to the supply voltage; a second terminal of the second resistor (R2), a second terminal of the fourteenth transistor (M14), and a second terminal of the eighteenth transistor (M18) are all connected to ground (VSS); a second terminal of the eleventh transistor (M11) is connected to a first terminal of the twelfth transistor (M12) and to a gate terminal of the first transistor (M1); a second terminal of the sixteenth transistor (M16) and a first terminal of the seventeenth transistor (M17) are connected and connected to the GATE terminal M1_ GATE of the first transistor (M1);

a gate terminal of the tenth transistor (M10), a gate terminal of the sixteenth transistor (M16), a gate terminal of the thirteenth transistor (M13), a gate terminal of the seventeenth transistor (M17) are all connected to the first Bias signal Bias1; a gate terminal of the ninth transistor (M9) is configured to receive a third enable signal en2_ n; a gate terminal of the fourteenth transistor (M14) is configured to receive the second enable signal en2; a gate terminal of the fifteenth transistor (M15) is configured to receive a second control signal CTRL _ n; a gate terminal of the eighteenth transistor (M18) is for receiving a first enable signal en1; the gate terminal of the fifth transistor (M5) is connected with the gate terminal of the sixth transistor (M6); a gate terminal of the seventh transistor (M7) is connected to a gate terminal of the eighth transistor (M8); a gate terminal of the sixth transistor (M6) is connected with a gate terminal of the eleventh transistor (M11); a gate terminal of the seventh transistor (M7) is connected to a gate terminal of the twelfth transistor (M12).

It should be noted that the "first terminal" of the transistor described in the embodiments of the present application may be a source terminal or an emitter terminal, and correspondingly, the "second terminal" of the transistor may be a drain terminal or a collector terminal.

In some embodiments of the present application, the switch module further comprises a first bias circuit and a delay module connected to a base or a gate of the first transistor, the third bias circuit for providing the first bias signal to the first transistor; the delay module is used for controlling the grid voltage or the base voltage of the first transistor to slowly change from the power supply voltage to the voltage corresponding to the second bias signal.

In some embodiments of the present application, the delay module includes a first resistor and a parasitic capacitor. In some embodiments, a resistor R1 is added to the pull-down path of the third bias circuit, and an RC delay is formed by the resistor R1 and a parasitic capacitance of the gate or base node of the first transistor, so as to reduce the pull-down speed of the gate voltage or the base voltage. By setting the appropriate RC value, the gate voltage or the base voltage of the first transistor is pulled down to VSS after the Iout terminal voltage is built up.

Fig. 4B is an optional structural schematic diagram of the switching circuit provided in the embodiment of the present application, and as shown in fig. 4B, the third bias circuit includes a fifteenth transistor (M15), a sixteenth transistor (M16), a first resistor R1, a seventeenth transistor (M17), and an eighteenth transistor (M18) that are sequentially cascaded; a first terminal of the fifteenth transistor (M15) is connected to the power supply voltage VBAT and a second terminal of the eighteenth transistor (M18) is connected to a ground voltage VSS; a gate terminal of the fifteenth transistor (M15) is configured to receive the second control signal CTRL _ n, a gate terminal of the sixteenth transistor (M16) and a gate terminal of the seventeenth transistor (M17) are both configured to receive the first Bias signal Bias1, and a gate terminal of the eighteenth transistor (M18) is configured to receive the second enable signal en2; a second terminal of the sixteenth transistor (M16) is connected to a gate terminal of the first transistor (M1). Here, the first resistor R1 is used as a pull-down resistor and a parasitic capacitance of the gate terminal of the first transistor (M1) forms an RC circuit to reduce the pull-down speed of the gate voltage of the first transistor.

The following describes an application of the switching circuit provided in the embodiment of the present application in a practical scenario, taking a transistor as a MOS transistor, a first bias signal being VB, a second bias signal and a third bias signal both being VSS, and a fourth bias signal being VBAT as an example.

Fig. 5 is an alternative circuit structure diagram of the constant impedance switch circuit provided in the embodiment of the present application, as shown in fig. 5, a control terminal of the first switch S1 and a control terminal of the third switch S3 are both connected to the output terminal of the detection circuit 23, a first terminal of the first switch S1 and a first terminal of the third switch S3 are both connected to the gate terminal of the first MOS transistor (M1), a second terminal of the first switch S1 is configured to receive an initial voltage, and a second terminal of the third switch S3 is configured to be grounded; the initial voltage is the power supply voltage VBAT or a bias voltage VB related to the power supply voltage VBAT; the control end of the second switch S2 and the control end of the fourth switch S4 are both connected to the output end of the detection circuit 23, the first end of the second switch S2 and the first end of the fourth switch S4 are both connected to the gate end of the second MOS transistor (M2), the second end of the second switch S2 is used for receiving the bias voltage VB, and the second end of the fourth switch S4 is used for grounding. In an implementation VB may be generated within VBAT by level shifter 31 (level shifter), e.g. VB = VBAT-2.5V or VB = VBAT/2.

In some embodiments, if the first switch S1 and the second switch S2 are both in a closed state and the third switch S3 and the fourth switch S4 are both in an open state, it is determined that the gate voltage of the first MOS transistor (M1) is the initial voltage and the gate voltage of the second MOS transistor (M2) is the bias voltage; or if the first switch S1 and the second switch S2 are both in an open state and the third switch S3 and the fourth switch S4 are both in a closed state, determining that the gate voltage of the first MOS transistor (M1) and the gate voltage of the second MOS transistor (M2) are both the ground voltage. At this time, since the gate voltages of M1 and M2 are not related to VBAM, M1 and M2 will remain in the linear region, so the impedance seen across the current switch is constantly the small resistance of the two cascaded switches.

It can be understood that, when the switches S1 and S2 are in the closed state and the switches S3 and S4 are in the open state, the M1 tube is in the open state, that is, the current switch is turned off, and at this time, the initial voltage is the power voltage, that is, the gate voltage of the M1 tube is the power voltage, that is, M1_ GAME = VBAM; under the condition that the switches S1 and S2 are in an open state and the switches S3 and S4 are in a closed state, the M1 tube is opened and the initial voltage is bias voltage; under the condition that the logic detection circuit detects that the working voltage does not reach the set voltage, determining the grid voltage of the M1 tube as the bias voltage; when the operating voltage is detected to reach the set voltage, the GATE voltage of the M1 tube and the GATE voltage of the M2 tube are both determined to be the ground voltage, namely M1_ GATE = VSS, and M2_ GATE = VSS. Here, the ground voltage may be 0V or a voltage less than a specific value, for example, 1V, and the ground voltage is not limited in the embodiments of the present application.

In implementation, the gate voltages of M1 and M2 are adjusted by detecting the operating state of the output terminal Iout of the current Switch (SW), and the method specifically includes the following four processes:

the first process is as follows: when the control signal CTRL =1 and M1_ GATE = VBAT, that is, M1 is in the open state, the switches S1 and S2 are closed while the switches S3 and S4 are opened, the entire current switch is turned off, and the voltage Va at the point a is limited by M2.

And a second process: when the control signal CTRL =0 and M1_ GATE = VB, i.e., M1 is on, the switches S1, S2 are closed while the switches S3, S4 are open. At the initial stage of starting, the output current Iout of the current switch does not reach the set voltage, and the states of the switches S1, S2, S3 and S4 are kept unchanged. The M2 GATE voltage M2_ GATE is biased to VB to prevent device overvoltage.

The third process: when the circuit switching circuit is judged to normally work by detecting Iout, the grids of the switch tube M1 and the common grid tube M2 are connected to the ground (VSS), namely the switches S3 and S4 are opened while the S1S 2 is opened, and the opening state of the current switch is kept, at the moment, because the grid voltages of the M1 and the M2 are not related to the power supply Voltage (VBAT), the M1 and the M2 can be kept in a linear region, and therefore the impedance seen from the two ends of the current switch is constantly two cascaded switch small resistors. In some embodiments, if M1 and M2 are not grounded, a constant voltage of about 1V may be applied to ensure the operating state of M2. In some embodiments, in a radio frequency front end application, when the HBT is operating normally, the voltage at the Iout end of the current switch can rise rapidly to above 2.3V.

The process four is as follows: when M1 is turned off again (CTRL =1, M1_ GATE = VBAT), S1, S2 are closed, S3, S4 are opened, and the current switch is turned off. The M2 grid electrode is biased to VB, and the device is prevented from being over-voltage. It can be understood that the gate voltage of normally on M1 is pulled to VBAT again. In some embodiments, VB needs to be associated with VBAT since VBAT is to power M1. In some embodiments, after the M1M2 gate is grounded, when it is detected that the output of the Iout terminal is abnormal again, the process returns to the second process, and after the Iout terminal is stably output, the process enters the third process again or directly enters the first process, and the process is restarted from the off state.

It should be noted that, in the second process, since the output voltage is not stable, if the gates of M1 and M2 are grounded at this time, the damage of the transistor may be caused, and therefore, in the third process, both are grounded again. Although M2 will usually swing between the saturation region and the linear region, and M1 will not usually have this phenomenon, if M2 gate is grounded alone, M1 gate is not grounded, M2 will be equivalent to be absent, and cannot protect M1 from overvoltage. In some embodiments, M1M2 may also be directly grounded during the turn-on process, and the unstable resistance of M2 may also be solved, but M1 and M2 may be damaged during the stabilization process.

As can be seen from the timing diagram of the key signals provided in fig. 6A, the operation logic of the constant impedance switching circuit provided in the embodiment of the present application is as follows:

in the period from t0 to t1, when the CTRL signal is "1", the third bias circuit pulls up M1_ GATE to VBAT, the current switch is turned off, and the voltage at the output terminal Iout keeps the lowest value. V detect is "0" and the second bias circuit is off. And M2_ GATE is connected with VB.

In the period from t1 to t3, when the CTRL signal is just switched to '0', the third bias circuit is closed, the second bias circuit is opened, the M1_ GATE voltage is VB, the current switch is opened, and the voltage of the output end gradually rises. M2_ GATE is connected with VB.

During the period from t3 to t5, when the CTRL signal is "0" and V _ detect is "1" (indicating that the output current Iout is normal), the third bias circuit pulls M1_ GATE down to VSS, and the current switch is kept on and the second bias circuit is closed. While M2_ GATE is connected to VSS.

Because the HBT is higher in voltage during working, each device cannot be over-voltage, and the circuit can work stably. The output resistance of the current switch is constant, and the two transistors are in a switching state and are small switching resistance, so that the current switch is insensitive to VBAT.

As shown in FIG. 4B, when the current switch is on, M1_ GATE is pulled slowly from VBAT to VSS, and the VB voltage level is not set. Correspondingly, the resistor R1 is added on the pull-down path, RC time delay is formed by the resistor R1 and the parasitic capacitance of the M1_ GATE node, and the M1_ GATE pull-down speed is reduced. Setting the appropriate RC value can make M1_ GATE pull down to VSS after the Iout terminal voltage is built up.

The CTRL signal generates an en2 signal through an inverter, and the en2 signal generates a control signal CTRL _ n in a VB-VBAT voltage domain through a level shifter (level shifter). For the logic signals CTRL and V _ detect, VB is the level corresponding to "1", and VSS is the level corresponding to "0". For the logic signal CTRL _ n, VBAT corresponds to "1" and VB corresponds to "0". As can be seen from the timing diagram of the key signals provided in fig. 6B, the operation logic of the switching circuit provided in the embodiment of the present application is as follows:

in the period from t0 to t1, when the CTRL signal is 1, M1_ GATE is pulled up to VBAT, the current switch is turned off, and the voltage of the output end voltage Iout keeps the lowest value. While M2_ GATE is connected to VB.

During the period from t1 to t5, when the CTRL signal is just switched to "0", M1_ GATE is pulled down and the current switch is opened. M1_ GATE is slowly pulled down to VSS due to RC delay in the pull-down path. In the process of pulling down the M1_ GATE, the voltage of the output end gradually reaches a stable value, namely the establishment of the Iout end is basically completed, and meanwhile, the M2_ GATE is pulled down to VSS.

The output resistance of the current switch is constant, and the two transistors in the switch state are small switch resistances, so that the current switch is insensitive to VBAT.

The constant-impedance switching circuit can prevent overvoltage of a current switch device and enables impedance seen by the input end and the output end of a current switch to be insensitive to power supply voltage change. For example, when the circuit is applied to a radio frequency front end circuit, the radio frequency bias circuit still has a stable impedance value when the power supply voltage changes, and radio frequency performance reduction caused by the impedance change of the bias circuit is avoided.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the above-described units is only one type of logical functional division, and other divisions may be realized in practice, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application.

Claims

1. A switch circuit is characterized by comprising a switch module _，

The switch module comprises a first transistor and a second transistor which are cascaded, wherein a source electrode or an emitter electrode of the first transistor is used for being connected with a power supply, and a drain electrode or a collector electrode of the first transistor is connected with a source electrode or an emitter electrode of the second transistor;

when the first transistor is closed and opened, providing a first bias signal to a grid electrode or a base electrode of the second transistor so as to limit the voltage of a drain electrode or a collector electrode of the first transistor;

and after the first transistor is started, providing a second bias signal to a grid electrode or a base electrode of the second transistor so as to enable the second transistor to work in a linear region or a saturation region.

2. The switch circuit of claim 1, wherein the first bias signal is greater than the second bias signal when the second transistor is a P-type transistor; when the second transistor is an N-type transistor, the first bias signal is smaller than the second bias signal.

3. The switch circuit of claim 1, wherein after the first transistor is turned on, a third bias signal is provided to a gate or a base of the first transistor, so that the first transistor keeps operating in a linear region or a saturation region.

4. The switch circuit of claim 3, wherein the third bias signal is the same as the second bias signal.

5. The switching circuit according to any of claims 1 to 4, further comprising a first current mirror and/or a second current mirror, wherein:

the first current mirror is respectively connected with the power supply and the input end of the switch module and is used for providing current input for the switch module;

and the second current mirror is connected with the output end of the switch module and used for outputting bias current.

6. The switch circuit of claim 3, wherein the switch module further comprises a first branch, a second branch connected to a gate or a base of the second transistor,

when the grid electrode or the base electrode of the second transistor is connected to the first branch circuit, the grid electrode or the base electrode of the second transistor obtains the first bias signal;

when the grid electrode or the base electrode of the second transistor is connected to the second branch circuit, the grid electrode or the base electrode of the second transistor obtains the second bias signal.

7. The switch circuit of claim 6, wherein the first branch comprises a second switch connected in series in the first branch, and wherein the second branch comprises a fourth switch connected in series in the second branch;

when the second switch is closed and the fourth switch is opened, the grid or the base of the second transistor acquires the first bias signal;

when the second switch is turned off and the fourth switch is turned off, the gate or the base of the second transistor acquires the second bias signal.

8. The switching circuit of claim 1,

the switching module further comprises a third branch and a fourth branch connected to the base or gate of the first transistor,

when the grid electrode or the base electrode of the first transistor is connected to the third branch circuit, the grid electrode or the base electrode of the first transistor obtains the third bias signal;

when the grid electrode or the base electrode of the first transistor is connected to the fourth branch circuit, the grid electrode or the base electrode of the first transistor acquires a fourth bias signal.

9. The switching circuit of claim 8, wherein the third branch comprises a third switch connected in series in the third branch, and the fourth branch comprises a first switch connected in series in the fourth branch;

when the first switch is closed and the third switch is opened, the grid or the base of the first transistor acquires the fourth bias signal;

when the first switch is turned off and the third switch is turned off, the gate or the base of the first transistor acquires the third bias signal.

10. The switching circuit of claim 6, further comprising: a control circuit for controlling the switching branch;

and/or the control circuit also comprises a detection circuit connected with the switch module and used for detecting the working voltage of the output end of the switch module so as to enable the control circuit to switch the branch of the switch module according to the working voltage.

11. The switching circuit of claim 9, wherein the switching module further comprises a level shifting circuit located within the first branch:

the level shift circuit is connected with the grid electrode or the base electrode of the first transistor through the first switch, and is used for providing the fourth bias signal for the grid electrode or the base electrode of the first transistor when the first transistor is closed and also used for providing the fifth bias signal for the grid electrode or the base electrode of the first transistor when the first transistor is opened; the fifth bias signal is lower than the fourth bias signal.

12. The switch circuit of claim 11, wherein the fourth bias signal is a supply voltage and the fifth bias signal is the same as the first bias signal.

13. The switch circuit of claim 7, wherein the fourth bias signal is a supply voltage and the fifth bias signal decreases slowly with on-time.

14. The switch circuit of claim 1, wherein the switch module further comprises a first bias circuit, a second bias circuit, and a third bias circuit connected to a gate or base of the first transistor,

the first bias circuit is used for providing the first bias signal for the first transistor;

the second bias circuit is used for acquiring the first bias signal and controlling the state of the third bias circuit;

the third bias circuit is used for providing a power supply voltage or the second bias signal for the first transistor.

15. The switch circuit of claim 1, wherein the switch module further comprises a first bias circuit and a delay module connected to a base or gate of the first transistor,

the third bias circuit is used for providing the first bias signal for the first transistor;

the delay module is used for controlling the grid voltage or the base voltage of the first transistor to slowly change from a power supply voltage to a voltage corresponding to the second bias signal.

16. The switch circuit of claim 15, wherein the delay module comprises a first resistor and a parasitic capacitor.