CN115938279A - Display panel, driving method thereof and display device - Google Patents

Abstract

The invention discloses a display panel, a driving method thereof and a display device, wherein the display panel comprises a grid driving circuit, the grid driving circuit comprises a plurality of cascaded shift registers, and each shift register is respectively connected with a grid line corresponding to the shift register of the stage; the scanning signal output by the shift register comprises a first pulse signal and a second pulse signal, and in a display frame, the second pulse signal of the scanning signal output by the Nth-stage shift register is overlapped with the first pulse signal of the scanning signal output by the (N + X) -th-stage shift register; wherein N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7. According to the scheme, the number of the spacing lines between two lines of pixels with mutually overlapped scanning signals is small, even if coupling is generated between two pulse signals with mutually overlapped scanning signals, dark lines generated due to inconsistent brightness can be eliminated in the brightness overlapping process, and therefore the display quality is improved.

Description

Display panel, driving method thereof and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel, a driving method thereof, and a display device.

Background

At present, display panels are widely applied to electronic devices such as mobile phones, flat panels and intelligent wearing devices, and with the development of display technologies, the requirements on the display quality of the display panels are higher and higher.

The existing display panel has bad phenomena such as display dark lines and the like, and the display quality and the user experience are seriously influenced.

Disclosure of Invention

The invention provides a display panel, a driving method thereof and a display device, which are used for improving the display quality of the display panel.

According to an aspect of the present invention, a display panel is provided, including a gate driving circuit, where the gate driving circuit includes a plurality of cascaded shift registers, and each shift register is connected to a gate line corresponding to the shift register of the current stage;

the scanning signals output by the shift register comprise a first pulse signal and a second pulse signal, and in a display frame, the second pulse signal of the scanning signals output by the shift register of the Nth stage and the first pulse signal of the scanning signals output by the shift register of the (N + X) th stage are overlapped;

wherein N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7.

Optionally, in a display frame, a second pulse signal of the scanning signal output by the shift register of the nth stage coincides with a first pulse signal of the scanning signal output by the shift register of the (N + X) th stage.

Alternatively, X is equal to 2.

Optionally, the display device further comprises a pixel circuit, wherein the pixel circuit comprises a data writing module, a compensation module, a driving module and a light emitting module, and the driving module and the light emitting module are connected between a first power line and a second power line;

the control end of the data writing module is connected with the grid line, the first end of the data writing module is connected with a data voltage, the second end of the data writing module is connected with the first end of the driving module, the compensation module is connected between the second end of the driving module and the control end, and the data writing module is used for conducting according to a first pulse signal of a scanning signal output by the shift register, transmitting the data voltage to the control end of the driving module, and conducting according to a second pulse signal of the scanning signal output by the shift register, resetting the first end of the driving module;

wherein N is less than the number of rows of the pixel circuit.

Optionally, each of the shift registers includes an input end and an output end, and the input end of the shift register of stage 1 accesses a trigger signal, and is configured to output, according to the trigger signal, a scan signal having a pulse width that is the same as a period of the trigger signal from the output end thereof, and transmit a shift signal to the input end of the shift register of the next stage;

the trigger signal is a double-pulse signal.

Optionally, the shift register includes a first input module, a second input module, a first output module, and a second output module;

the output end of the first input module is connected with the control end of the first output module, and the first input module is used for responding to a first clock signal and transmitting an input signal of the input end of the first input module to the control end of the first output module;

the input end of the second input module is used as the trigger signal input end of the shift register and is used for controlling the potential of the control end of the second output module;

the output end of the first output module and the output end of the second output module are both connected to the output end of the shift register, the first output module is used for outputting a first level signal according to the potential of the control end of the first output module, and the second output module is used for outputting a second level signal according to the potential of the control end of the second output module;

preferably, the first input module comprises a first transistor, the second input module comprises a second transistor, the first output module comprises a third transistor and a first capacitor, and the second output module comprises a fourth transistor and a second capacitor;

a gate of the first transistor is connected to the first clock signal, a first pole of the first transistor is used as an input terminal of the first input module, a second pole of the first transistor is connected to a gate of the third transistor, a first pole of the third transistor is connected to a first potential signal, a second pole of the third transistor is used as an output terminal of the first output module, and the first capacitor is connected between the first pole and the gate of the third transistor;

the gate of the second transistor is connected to the first clock signal, the first pole of the second transistor is used as the input terminal of the second input module, the second pole of the second transistor is connected to the gate of the fourth transistor, the first pole of the fourth transistor is connected to the second clock signal, the second pole of the fourth transistor is connected to the second pole of the third transistor, and the second capacitor is connected between the gate and the second pole of the fourth transistor.

Optionally, the shift register further includes a first output control module and a second output control module, an output end of the first output control module is connected to a control end of the first output module, and an output end of the second output control module is connected to a control end of the second output module;

preferably, the first output control module includes a fifth transistor, a gate of the fifth transistor is connected to the output end of the second input module, a first pole of the fifth transistor is connected to the first clock signal, and a second pole of the fifth transistor is the output end of the first output control module;

the second output control module comprises a sixth transistor and a seventh transistor, a gate of the sixth transistor is connected with the control end of the first output module, a first pole of the sixth transistor is connected to the first potential signal, a second pole of the sixth transistor is connected with a first pole of the seventh transistor, a second pole of the seventh transistor is an output end of the second output control module, and a gate of the seventh transistor is connected to the second clock signal.

Optionally, the shift register further includes a protection module, where the protection module is connected between the output end of the second input module and the control end of the second output module;

preferably, the protection module includes an eighth transistor, a gate of the eighth transistor is connected to the second potential signal, a first pole of the eighth transistor is connected to the output terminal of the second input module, and a second pole of the eighth transistor is connected to the control terminal of the second output module.

According to another aspect of the present invention, a driving method of a display panel is provided, where the display panel includes a gate driving circuit, the gate driving circuit includes a plurality of cascaded shift registers, and each shift register is connected to a gate line corresponding to the shift register of the current stage; the scanning signals output by the shift register comprise a first pulse signal and a second pulse signal;

the driving method of the display panel includes:

in a display frame, when the shift register of the Nth stage outputs a second pulse signal, controlling the shift register of the (N + X) th stage to output a first pulse signal;

wherein N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7.

According to another aspect of the present invention, there is provided a display device including the display panel provided in any of the embodiments of the present invention.

According to the technical scheme of the embodiment of the invention, in a display frame, a second pulse signal of a scanning signal output by an Nth-level shift register is overlapped with a first pulse signal of a scanning signal output by an N + X-level shift register, wherein N is a positive integer larger than or equal to 1, and X is a positive integer larger than or equal to 2 and smaller than or equal to 7, so that two adjacent rows of pixels are charged simultaneously.

It should be understood that the statements in this section are not intended to identify key or critical features of the embodiments of the present invention, nor are they intended to limit the scope of the invention. Other features of the present invention will become apparent from the following description.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 2 is a timing waveform diagram of a scan signal according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 5 is a timing waveform diagram of another scan signal according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating a shift register according to another embodiment of the present invention;

FIG. 9 is a diagram illustrating a shift register according to another embodiment of the present invention;

FIG. 10 is a waveform diagram illustrating timing control of a gate driving circuit according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and referring to fig. 1, a display panel 10 according to the embodiment includes a gate driving circuit 11, where the gate driving circuit 11 includes a plurality of cascaded shift registers 110, and each shift register 110 is connected to a gate line 20 corresponding to a shift register 100 of the current stage; the scanning signals output by the shift register 110 include a first pulse signal and a second pulse signal, and in a display frame, the second pulse signal of the scanning signal SN output by the nth stage shift register 110 overlaps with the first pulse signal of the scanning signal S (N + X) output by the N + X stage shift register 110; wherein N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7.

Specifically, the gate driving circuit 11 may be disposed in a side frame of the display panel 10, and the gate driving circuit 11 is configured to provide scanning signals to the gate lines 20, wherein the gate lines 20 extending along the X direction are sequentially arranged in the Y direction.

The gate driving circuit 11 includes a plurality of cascaded shift registers 110, each shift register 110 is correspondingly connected to a gate line 20, and the scanning signals output by each shift register 110 can be transmitted to the pixels through the gate lines for driving the pixels; while the scan signal is also used for the shift signal of the shift register 110 itself.

In this embodiment, the scan signal output by the shift register 110 is a double pulse signal. Referring to fig. 2, the scan signal output by the nth stage shift register 110 includes a first pulse signal and a second pulse signal, the scan signal output by the N +1 th stage shift register 110 shifts on the basis of the scan signal output by the nth stage shift register 110, and so on, thereby implementing the step-by-step shift output of the scan signal. A delay exists between the scanning signal output by the next stage of shift register 110 and the scanning signal output by the present stage of shift register 110, and the delay time can be set according to the pulse width of the scanning signal.

In the process of shifting and outputting the scan signals, a situation that two rows (non-adjacent) of scan signals overlap occurs, in this embodiment, by reducing the pulse width between the first pulse signal and the second pulse signal, so that the second pulse signal of the scan signal SN output by the nth stage shift register 110 overlaps with the first pulse signal of the scan signal S (N + X) output by the N + X stage shift register 110, the nth stage shift register 110 and the N + X stage shift register 110 output valid scan signals at the same time, where X is a positive integer greater than or equal to 2 and less than or equal to 7. That is, scan signal overlap occurs at intervals of 7 lines at most, and since the number of the interval lines is small, even if coupling occurs between two pulse signals overlapped with each other, dark lines due to brightness inconsistency can be eliminated during the brightness superimposition process, thereby improving display quality.

With continued reference to fig. 2, in a display frame, the second pulse signal of the scan signal SN output by the nth stage shift register 110 coincides with the first pulse signal of the scan signal S (N + X) output by the N + X stage shift register 110. That is, while the nth stage shift register 110 outputs the second pulse signal, the nth + X stage shift register 110 just outputs the nth stage pixel and the N + X stage pixel corresponding to the first pulse signal to be charged simultaneously. The purpose of setting up like this is favorable to the timing design, reduces the degree of difficulty.

In the display panel provided in the embodiment of the present invention, in a display frame, a second pulse signal of a scan signal output by an nth stage shift register is overlapped with a first pulse signal of a scan signal output by an N + X stage shift register, where N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7, so that two adjacent rows of pixels are charged simultaneously, and since the number of rows of the scan signals between two rows of pixels overlapped with each other is small, even if coupling occurs between two pulse signals overlapped with each other, a dark line caused by inconsistent brightness can be eliminated in a brightness overlapping process, thereby improving display quality.

Fig. 3 is a schematic structural diagram of another display panel according to an embodiment of the present invention, fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, and referring to fig. 3 and fig. 4, based on the above technical solutions, optionally, the display panel further includes a pixel circuit 30, the pixel circuit 30 includes a data writing module 302, a compensation module 303, a driving module 301 and a light emitting module 304, and the driving module 301 and the light emitting module 304 are connected between a first power line and a second power line; the control terminal of the data writing module 302 is connected to the gate line 20, the first terminal of the data writing module 302 is connected to the data voltage Vdata, the second terminal of the data writing module 302 is connected to the first terminal of the driving module 301, and the compensating module 303 is connected between the second terminal and the control terminal of the driving module 301.

The pixel circuits 30 are arranged in an array. In the display period of the display panel, for the adjacent two stages of shift registers 110, the shift register 110 at the previous stage corresponds to the end time of the first pulse signal of the scanning signal, and the shift register 110 at the next stage starts to output the first pulse signal corresponding to the scanning signal. In general, each stage of the shift register 110 is connected to one gate line 20, the gate line 20 is correspondingly connected to one row of pixel circuits 30, the shift register 110 outputs a scan signal to the gate line 20, and the scan signal on the gate line 20 controls the charging of one row of pixel circuits connected to the gate line 20.

Specifically, the gate line 20 is connected to a control terminal of the data writing block 302 in the pixel circuit 30. In the Data writing phase, the Data writing module 302 is turned on in response to the first pulse signal of the scan signal, and transmits the Data voltage Vdata on the Data line Data to the control terminal of the driving module 301 through the compensation module 303, where the compensation module 303 is used to compensate the threshold voltage of the driving module 301. In the reset stage, the Data writing module 302 is turned on in response to the second pulse signal of the scanning signal, transmits the Data voltage Vdata on the Data line Data to the first end of the driving module 301 (at this time, the compensation module 303 is turned off), and resets the potential at the first end of the driving module 301, so that the bias states of the driving module 301 are the same, the uniformity of the driving current output by the driving module 301 is ensured, and the display uniformity is improved. Here, N is smaller than the number of rows of the pixel circuits 30.

In the prior art, for a double-pulse scan signal, the second pulse signal of the scan signal S1 output by the first stage shift register 110 coincides with the first pulse signal of the scan signal S9 output by the ninth stage shift register 110, when the data writing module 302 of the first row pixel circuit 30 is turned on in response to the second pulse signal of the scan signal S1, the second pulse signal of the scan signal S1 couples to the first pulse signal of the scan signal S9 output by the ninth stage shift register 110, so as to pull down the first pulse signal of the scan signal S9 output by the ninth stage shift register 110, and further to make the data voltage Vdata writing of the ninth row pixel circuit 30 more sufficient (the data writing module 302 includes a P-type transistor), which results in insufficient opening of the driving module 301, affecting the driving current, and thus generating a dark line. For example, taking a smart watch as an example, the display panel of the smart watch is circular, and during the scanning process from bottom to top, the second pulse signal of the scanning signal S1 output by the first stage shift register 110 pulls down the first pulse signal of the scanning signal S9 output by the ninth stage shift register 110, so that a circular arc shaped dark line appears at the bottom of the display panel.

In order to eliminate the dark line, the embodiment of the present invention reduces the time interval between the first pulse signal and the second pulse signal of the scan signal, preferably, X =2. Fig. 5 is a timing waveform diagram of another scanning signal according to an embodiment of the present invention, and referring to fig. 5, based on the above technical solutions, taking N =1, x =2 as an example for a double-pulse scanning signal, in this embodiment, a second pulse signal of the scanning signal S1 output by the first-stage shift register 110 coincides with a first pulse signal of the scanning signal S3 output by the third-stage shift register 110, and when the data writing module 302 of the first row of pixel circuits 30 is turned on in response to the second pulse signal of the scanning signal S1, the second pulse signal of the scanning signal S1 is coupled with the first pulse signal of the scanning signal S3 output by the third-stage shift register 110. The scan signal S2 output by the second stage shift register 110 is a normal signal, and the scan signal S4 output by the fourth stage shift register 110 is coupled to the first pulse signal that does not pull down the scan signal S4 output by the fourth stage shift register 110, so that the subsequent picture can be displayed normally.

Here, since the first row pixels and the third row pixels are closely spaced, even if the second pulse signal of the first row scanning signal S1 couples and pulls down the first pulse signal of the third row scanning signal S3, so that the third row pixels are darker, in the case of normal display of the first row pixels, human eyes cannot perceive the phenomenon of inconsistent brightness in the process of brightness superimposition, so that dark lines caused by inconsistent brightness can be eliminated, thereby improving the display quality.

With continued reference to fig. 4, optionally, the pixel circuit 30 further includes a storage module 305, a first light-emitting control module 306, and a second light-emitting control module 307, where the storage module 305 is connected between a first power line and the control terminal of the driving module 301, the first light-emitting control module 306 is connected between the first power line and the first terminal of the driving module 101, the second light-emitting control module 307 is connected between the second terminal of the driving module 301 and the first terminal of the light-emitting module 304, and the second terminal of the light-emitting module 304 is connected to the second power line. The first power line is used for transmitting a first power voltage VDD, and the second power line is used for transmitting a second power voltage VSS. The storage module 305 is used for storing the voltage of the control terminal of the driving module 301. In the light emitting phase, the first light emitting control module 306 and the second light emitting control module 307 are turned on in response to a light emitting control signal (not shown), the first power voltage VDD is transmitted to the first terminal of the driving module 301, and the driving module 301 generates a driving current according to the voltages of the control terminal and the first terminal thereof, so as to drive the light emitting module 304 to emit light.

Optionally, the pixel circuit 30 further includes a first initialization module 308 and a second initialization module 309, where the first initialization module 308 is connected between the first initialization signal line and the control terminal of the driving module 301, and is configured to transmit a first initialization voltage Vref1 on the first initialization signal line to the control terminal of the driving module 301, so as to initialize the potential of the control terminal of the driving module 301; the second initializing module 309 is connected between the second initializing signal line and the first end of the light emitting module 304, and is configured to transmit a second initializing voltage Vref2 on the second initializing signal line to the first end of the light emitting module 304 to initialize the potential of the first end of the light emitting module 304.

It should be noted that the transistors included in each block in the pixel circuit 30 may be P-type transistors or N-type transistors, which is not limited in this embodiment, and detailed working principles thereof are not described herein again.

Fig. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention, and referring to fig. 6, based on the above technical solutions, optionally, the gate driving circuit includes a plurality of cascaded shift registers 110, each shift register 110 includes an input end IN and an output end OUT, the input end IN of the shift register 110 of the 1 st stage is connected to a trigger signal SIN, and is configured to output a scan signal with a pulse width same as a period of the trigger signal SIN from the output end OUT thereof according to the trigger signal SIN and transmit the shift signal to the input end IN of the shift register 110 of the next stage. Here, the trigger signal SIN is a double pulse signal, and thus the scanning signal output from the shift register 110 is also a double pulse signal.

The shift register 110 further includes a first clock signal input terminal SC1 and a second clock signal input terminal SC2. In the present embodiment, the first clock signal terminal SC1 of the odd shift register 110 and the second clock signal terminal SC2 of the even shift register 110 are both connected to the first clock signal line CLK1, and the second clock signal terminal SC2 of the odd shift register 110 and the first clock signal terminal SC1 of the even shift register 110 are both connected to the second clock signal line CLK2, so as to implement the shift output of the scan driving circuit 100.

Fig. 7 is a schematic structural diagram of a shift register according to an embodiment of the present invention, and referring to fig. 7, on the basis of the foregoing technical solutions, optionally, the shift register 110 includes a first input module 101, a second input module 102, a first output module 103, and a second output module 104; the output end of the first input module 101 is connected to the control end of the first output module 103, and the first input module 101 is configured to respond to the first clock signal SCK1 and transmit the input signal at the input end thereof to the control end of the first output module 103; the input terminal of the second input module 102 is used as the input terminal IN of the shift register 110, and is used for controlling the potential of the control terminal of the second output module 104; the output terminal of the first output module 103 and the output terminal of the second output module 104 are both connected to the output terminal OUT of the shift register 110, the first output module 103 is configured to output a first level signal VC1 according to the potential of the control terminal thereof, and the second output module 104 is configured to output a second level signal VC2 according to the potential of the control terminal thereof.

The input end of the second input module 102 in the first stage of shift register 110 inputs the start signal SIN, and the input ends of the second input modules 102 in the other stages of shift registers 110 are all connected to the output end OUT of the shift register 110 of the previous stage. The start signal SIN is a screen signal on the display panel.

Specifically, the first input module 101 is capable of responding to the first clock signal SCK1 to be turned on, and transmitting the input signal of the input terminal thereof to the control terminal of the first output module 103, so as to control the potential of the control terminal of the first output module 103, that is, control the potential at the first node N1. The second input module 102 can be turned on according to a signal of a control terminal (not shown in the figure), and transmits a signal of an input terminal (for example, an output signal of the previous stage shift register 110) to the control terminal of the second output module 104, so as to control a potential of the control terminal of the second output module 104, that is, control a potential at the second node N2.

The output end of the first output module 103 is connected to the output end OUT of the first stage shift register 110, and is configured to output the first level signal VC1 when being turned on according to the potential of the first node N1. The output terminal of the second output module 104 is also connected to the output terminal OUT of the first stage shift register 110, and is configured to output the second level signal VC2 when being turned on according to the potential of the second node N2. The first level signal is different from the second level signal, for example, the first level signal VC1 is a low level signal VGL, and the second level signal VC2 is a high level signal VGH; or the first level signal VC1 is a high level signal VGH, and the second level signal VC2 is a low level signal VGL.

Fig. 8 is a schematic structural diagram of another shift register according to an embodiment of the present invention, and referring to fig. 8, on the basis of the above technical solution, optionally, the shift register 110 further includes a first output control module 105 and a second output control module 106, an output end of the first output control module 105 is connected to a control end of the first output module 103, and an output end of the second output control module 106 is connected to a control end of the second output module 104. A control terminal of the first output control module 105 and an output terminal of the second input module 102 are connected to the third node N3.

In this embodiment, the input terminal of the first input module 101 may be connected to a low level signal VGL, the input terminal of the first output module 103 may be connected to a high level signal VGH, and the input terminal of the second output module 104 may be connected to the second clock signal SCK2.

Fig. 9 is a schematic structural diagram of another shift register according to an embodiment of the present invention, and with reference to fig. 9, on the basis of the foregoing technical solutions, optionally, the first input module 101 includes a first transistor M1, the second input module 102 includes a second transistor M2, the first output module 103 includes a third transistor M3 and a first capacitor C1, and the second output module 104 includes a fourth transistor M4 and a second capacitor C2; a gate of the first transistor M1 is connected to the first clock signal SCK1, a first pole of the first transistor M1 is used as an input terminal of the first input module 101, a second pole of the first transistor M1 is connected to a gate of the third transistor M3, a first pole of the third transistor M3 is connected to the high level signal VGH, a second pole of the third transistor M3 is used as an output terminal of the first output module 103, and the first capacitor C1 is connected between the first pole and the gate of the third transistor M3; a gate of the second transistor M2 is connected to the first clock signal SCK1, a first pole of the second transistor M2 is used as an input terminal of the second input module 102, a second pole of the second transistor M2 is connected to a gate of the fourth transistor M4, a first pole of the fourth transistor M4 is connected to the second clock signal SCK2, a second pole of the fourth transistor M4 is connected to a second pole of the third transistor M3, and the second capacitor C2 is connected between the gate and the second pole of the fourth transistor M4.

The first output control module 105 includes a fifth transistor M5, a gate of the fifth transistor M5 is connected to the output end of the second input module 102, a first pole of the fifth transistor M5 is connected to the first clock signal SCK1, and a second pole of the fifth transistor M5 is the output end of the first output control module 105; the second output control module 106 includes a sixth transistor M6 and a seventh transistor M7, a gate of the sixth transistor M6 is connected to the control end of the first output module 103, a first pole of the sixth transistor M6 is connected to the first potential signal V1, a second pole of the sixth transistor M6 is connected to the first pole of the seventh transistor M7, a second pole of the seventh transistor M7 is an output end of the second output control module 106, and a gate of the seventh transistor M7 is connected to the second clock signal SCK2.

The shift register 11 further comprises a protection module 107, wherein the protection module 107 is connected between the output terminal of the second input module 102 and the control terminal of the second output module 104. Specifically, the protection module 107 includes an eighth transistor M8, a gate of the eighth transistor M8 is connected to the low level signal VGL, a first pole of the eighth transistor M8 is connected to the output terminal of the second input module 102, and a second pole of the eighth transistor M8 is connected to the control terminal of the second output module 104. That is, the eighth transistor M8 is connected between the second node N2 and the third node N3, and the eighth transistor M8 may be in a normally-on state in response to the low level signal VGL.

Fig. 10 is a timing control waveform diagram of a gate driving circuit according to an embodiment of the present invention, which is suitable for the gate driving circuit shown in fig. 9, and with reference to fig. 9 and fig. 10, a working process of the gate driving circuit according to the embodiment at least includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, a sixth stage t6, a seventh stage t7, and an eighth stage t8. The start signal SIN may be provided by a start signal line, and the first clock signal SCK1 and the second clock signal SCK2 may be provided by corresponding clock signal lines, respectively.

In the first period t1, the start signal SIN is at a high level, the first clock signal SCK1 is at a low level, and the second clock signal SCK2 is at a high level, so that the first transistor M1 and the second transistor M2 are turned on, the low level signal VGL is transmitted to the gate of the third transistor M3 through the first transistor M1, the third transistor M3 is turned on, the high level signal VGH is transmitted to the output terminal OUT of the shift register 110 through the third transistor M3, and the output terminal OUT outputs a high level. The signal inputted from the input terminal of the second input module 102 is transmitted to the gate of the fourth transistor M4 through the second transistor M2, and when the shift register 110 is the first-stage shift register 110, the input terminal of the second input module 102 is inputted with the start signal SIN, and then the fourth transistor M4 is turned off. The shift register 110 outputs a high level signal VGH in the first stage t 1. When the shift register 110 is a shift register 110 of another stage except the first stage, the signal accessed by the input end of the second input module 102 is the output signal of the shift register 110 of the previous stage, and since the first clock signal SCK1 is at a low level, the first transistor M1 is in an on state, the output end OUT of the shift register 110 is at a high level, and the fourth transistor M4 is turned off, so the output end OUT still outputs the high level signal VGH.

It should be noted that the following stages are all described by taking the first stage shift register 11 as an example.

In the second stage t2, the start signal SIN is at a high level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a low level, so that the first transistor M1 and the second transistor M2 are turned off, and the seventh transistor M7 is turned on. The low level signal VGL stored in the first capacitor C1 makes the third transistor M3 and the sixth transistor M6 continuously turned on, and the high level signal VGH is transmitted to the second node N2 through the sixth transistor M6 and the seventh transistor M7, and the fourth transistor M4 maintains an off state. Meanwhile, the high level signal VGH is transmitted to the output terminal OUT of the shift register 110 through the third transistor M3, and the output terminal OUT outputs the high level signal VGH.

In the third stage t3, the start signal SIN is at a low level, the first clock signal SCK1 is at a low level, and the second clock signal SCK2 is at a high level, so that the first transistor M1 and the second transistor M2 are turned on, the potential of the first node N1 is the potential corresponding to the low level signal VGL, the third transistor M3 is turned on, and the high level signal VGH is transmitted to the output terminal OUT of the shift register 110. Since the start signal SIN is at a low level, the potentials of the second node N2 and the third node N3 are also at a low level, the fourth transistor M4 and the fifth transistor M5 are turned on, the low level of the first clock signal SCK1 is transmitted to the first node N1, and the on state of the third transistor M3 is maintained. Meanwhile, the high level of the second clock signal SCK2 is transmitted to the output terminal OUT of the shift register 110 through the fourth transistor M4. Accordingly, in the third stage t3, the third transistor M3 and the fourth transistor M4 are simultaneously turned on, so that the output terminal OUT of the shift register 110 outputs the high level signal VGH.

In the fourth phase t4, the start signal SIN is at a low level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a high level, so that the first transistor M1 and the second transistor M2 are turned off, the voltage stored in the second capacitor C2 (the low level signal VGL in the previous phase) turns on the fifth transistor M5 and the fourth transistor M4, the high level of the first clock signal SCK1 turns off the third transistor M3, the high level of the second clock signal SCK2 is transmitted to the output terminal OUT of the shift register 110 through the fourth transistor M4, and the output terminal OUT outputs the high level signal VGH.

In the fifth phase t5, the start signal SIN is at a high level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a low level. The third transistor M3 is kept in an off state by the voltage stored in the first capacitor C1 (corresponding to the high level signal VGH in the previous stage), the fourth transistor M4 is continuously turned on by the voltage stored in the second capacitor C2 (corresponding to the low level signal VGL in the previous stage), the low level of the second clock signal SCK2 is transmitted to the output terminal OUT of the shift register 110, and the output terminal OUT outputs the low level signal VGL. Since the second clock signal SCK2 transits from the high level to the low level, under the bootstrap action of the second capacitor C2, the potential of the gate (i.e., the second node N2) of the fourth transistor M4 is pulled lower, and the fourth transistor M4 is continuously turned on, so that the signal output by the output terminal OUT is the low level signal VGL.

In the fifth phase t5, the eighth transistor M8 is provided to prevent the extremely low potential at the gate of the fourth transistor M4 from being transmitted to the third node N3, which may affect the normal operation of the shift register 110.

In the sixth phase t6, the start signal SIN is at a high level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a high level. The voltage stored in the second capacitor C2 (the low level signal VGL of the previous stage) makes the fourth transistor M4 continuously turned on, the high level of the second clock signal SCK2 is transmitted to the output terminal OUT of the shift register 110, and the output terminal OUT outputs the high level signal VGH. Accordingly, the second transistor M2 and the third transistor M3 are turned on, and the output terminal OUT of the shift register 110 outputs the high level signal VGH.

The working process of the seventh stage t7 is the same as that of the second stage t2, and the working process of the eighth stage t8 is the same as that of the first stage t1, which are not described herein again.

And repeating the eight working stages subsequently, and outputting a second pulse signal of the scanning signal, wherein the specific working process is not repeated.

Through the above-mentioned working stages, the signal output of the first stage shift register 110 is realized. It should be noted that, because there are multiple stages of shift registers 110 in the gate driving circuit, the output signal of the previous stage shift register 110 can be used as the input signal (shift signal) of the next stage shift register 110, so that the step-by-step shift transmission of the output signal can be realized, and the working processes of the other stages of shift registers 110 can refer to the above description, and are not described herein again.

It should be noted that the structure of the shift register 110 in the above technical solution is only an optional structure provided in this embodiment, and in other embodiments, other structures may also be included.

The embodiment of the invention also provides a driving method of the display panel, which is used for driving the display panel provided by any embodiment of the invention. The driving method includes:

in a display frame, when the Nth-stage shift register outputs a second pulse signal, controlling the (N + X) -th-stage shift register to output a first pulse signal; wherein N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7.

In the driving method of the display panel provided by the embodiment of the invention, in a display frame, the second pulse signal of the scanning signal output by the nth stage shift register is overlapped with the first pulse signal of the scanning signal output by the N + X stage shift register, where N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7, so that two rows of pixels close to each other are charged simultaneously.

Optionally, an embodiment of the present invention further provides a display device, where the display device includes the display panel provided in any embodiment of the present invention, and therefore the display device also has the beneficial effects described in any embodiment. Fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention, where the display device may be the mobile phone shown in fig. 11, or any electronic product with a display function, including but not limited to the following categories: the touch screen display system comprises a television, a notebook computer, a desktop display, a tablet computer, a digital camera, an intelligent bracelet, intelligent glasses, a vehicle-mounted display, medical equipment, industrial control equipment, a touch interaction terminal and the like, and the embodiment of the invention is not particularly limited in this respect.

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired results of the technical solution of the present invention can be achieved.

The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. The display panel is characterized by comprising a grid driving circuit, wherein the grid driving circuit comprises a plurality of cascaded shift registers, and each shift register is respectively connected with a grid line corresponding to the shift register of the current stage;

the scanning signals output by the shift register comprise a first pulse signal and a second pulse signal, and in a display frame, the second pulse signal of the scanning signals output by the shift register of the Nth stage and the first pulse signal of the scanning signals output by the shift register of the (N + X) th stage are overlapped;

wherein N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7.

2. The display panel according to claim 1, wherein the second pulse signal of the scanning signal outputted from the shift register of the nth stage coincides with the first pulse signal of the scanning signal outputted from the shift register of the N + X th stage in a display frame.

3. The display panel of claim 1, wherein X is equal to 2.

4. The display panel according to claim 1, further comprising a pixel circuit including a data writing module, a compensation module, a driving module, and a light emitting module, wherein the driving module and the light emitting module are connected between a first power line and a second power line;

the control end of the data writing module is connected with the grid line, the first end of the data writing module is connected with a data voltage, the second end of the data writing module is connected with the first end of the driving module, the compensation module is connected between the second end of the driving module and the control end, and the data writing module is used for conducting according to a first pulse signal of a scanning signal output by the shift register, transmitting the data voltage to the control end of the driving module, and conducting according to a second pulse signal of the scanning signal output by the shift register, resetting the first end of the driving module;

wherein N is less than the number of rows of the pixel circuit.

5. The display panel according to claim 1, wherein each of the shift registers includes an input terminal and an output terminal, the input terminal of the shift register of stage 1 is connected to a trigger signal, and is configured to output a scan signal having a pulse width equal to a period of the trigger signal from the output terminal thereof according to the trigger signal, and transmit the shift signal to the input terminal of the shift register of a next stage;

wherein the trigger signal is a double-pulse signal.

6. The display panel according to claim 1, wherein the shift register comprises a first input module, a second input module, a first output module, and a second output module;

the output end of the first input module is connected with the control end of the first output module, and the first input module is used for responding to a first clock signal and transmitting an input signal of the input end of the first input module to the control end of the first output module;

the input end of the second input module is used as the trigger signal input end of the shift register and is used for controlling the potential of the control end of the second output module;

the output end of the first output module and the output end of the second output module are both connected to the output end of the shift register, the first output module is used for outputting a first level signal according to the potential of the control end of the first output module, and the second output module is used for outputting a second level signal according to the potential of the control end of the second output module;

preferably, the first input module comprises a first transistor, the second input module comprises a second transistor, the first output module comprises a third transistor and a first capacitor, and the second output module comprises a fourth transistor and a second capacitor;

the gate of the first transistor is connected to the first clock signal, the first pole of the first transistor is used as the input end of the first input module, the second pole of the first transistor is connected to the gate of the third transistor, the first pole of the third transistor is connected to the first potential signal, the second pole of the third transistor is used as the output end of the first output module, and the first capacitor is connected between the first pole and the gate of the third transistor;

the gate of the second transistor is connected to the first clock signal, the first pole of the second transistor is used as the input end of the second input module, the second pole of the second transistor is connected to the gate of the fourth transistor, the first pole of the fourth transistor is connected to the second clock signal, the second pole of the fourth transistor is connected to the second pole of the third transistor, and the second capacitor is connected between the gate and the second pole of the fourth transistor.

7. The display panel according to claim 6, wherein the shift register further comprises a first output control module and a second output control module, an output terminal of the first output control module is connected to a control terminal of the first output module, and an output terminal of the second output control module is connected to a control terminal of the second output module;

preferably, the first output control module includes a fifth transistor, a gate of the fifth transistor is connected to the output end of the second input module, a first pole of the fifth transistor is connected to the first clock signal, and a second pole of the fifth transistor is the output end of the first output control module;

the second output control module comprises a sixth transistor and a seventh transistor, a gate of the sixth transistor is connected with the control end of the first output module, a first pole of the sixth transistor is connected to the first potential signal, a second pole of the sixth transistor is connected with a first pole of the seventh transistor, a second pole of the seventh transistor is an output end of the second output control module, and a gate of the seventh transistor is connected to the second clock signal.

8. The display panel according to claim 7, wherein the shift register further comprises a protection module connected between the output terminal of the second input module and the control terminal of the second output module;

preferably, the protection module includes an eighth transistor, a gate of the eighth transistor is connected to the second potential signal, a first pole of the eighth transistor is connected to the output end of the second input module, and a second pole of the eighth transistor is connected to the control end of the second output module.

9. The driving method of the display panel is characterized in that the display panel comprises a grid driving circuit, the grid driving circuit comprises a plurality of cascaded shift registers, and each shift register is respectively connected with a grid line corresponding to the shift register of the current stage; the scanning signals output by the shift register comprise a first pulse signal and a second pulse signal;

the driving method of the display panel includes:

in a display frame, when the shift register of the Nth stage outputs a second pulse signal, controlling the shift register of the (N + X) th stage to output a first pulse signal;

wherein N is a positive integer greater than or equal to 1, and X is a positive integer greater than or equal to 2 and less than or equal to 7.

10. A display device characterized by comprising the display panel according to any one of claims 1 to 8.

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