CN115936347A - Method, device, equipment, storage medium and system for processing wafer - Google Patents

Abstract

The embodiment of the disclosure provides a method, a device, equipment, a storage medium and a system for processing a wafer, wherein the method comprises the following steps: obtaining a dispatching path of the current batch of wafers; the dispatching path comprises at least one dispatching station for processing the current batch of wafers and a dispatching sequence among the dispatching stations; determining a process program corresponding to each scheduling station; wherein, the corresponding process formulas of at least two scheduling stations with the same process conditions are the same; and sequentially scheduling each scheduling station to execute the process program corresponding to the scheduling station based on the scheduling sequence so as to perform process processing on the wafers of the current batch.

Description

Method, device, equipment, storage medium and system for processing wafer

Technical Field

The present disclosure relates to the field of semiconductor technology, and more particularly, but not exclusively, to a method, apparatus, device, storage medium, and system for processing a wafer.

Background

Semiconductor manufacturing processes involve various processes performed on wafers, such as photolithography, etching, ion implantation, thin film deposition, and chemical mechanical polishing. Each batch of wafers may be processed in as many as thousands of steps. Before the wafer is processed, the configuration of the process recipe is performed in advance according to the product requirement. In practical applications, the process recipe may be configured as a flow recipe (flow recipe) for processing a wafer, and the flow recipe is configured as a subroutine corresponding to each step of processing the wafer. The flow program may define each dispatch station through which a wafer is scheduled to pass, and the sub-program may define a process program, a test program, etc. executed by the wafer at each dispatch station.

However, when configuring the flow program, the number of scheduled dispatch sites through which a wafer is scheduled to pass is large, and the conditions of the sub-programs executed by each dispatch site are complicated. This results in higher cost for allocating process programs and larger amount of process programs, which results in more memory.

Disclosure of Invention

Embodiments of the present disclosure provide a method, apparatus, device, storage medium and system for processing a wafer, which at least reduce the memory usage of a process program.

The embodiment of the present disclosure provides a method for processing a wafer, including:

obtaining a dispatching path of the current batch of wafers; the dispatching path comprises at least one dispatching station for processing the current batch of wafers and a dispatching sequence among the dispatching stations;

determining a process program corresponding to each scheduling station; wherein, the corresponding process formulas of at least two dispatching stations with the same process condition are the same;

and sequentially dispatching each dispatching station to execute the process program corresponding to the dispatching station based on the dispatching sequence so as to carry out process treatment on the wafers of the current batch.

An embodiment of the present disclosure provides an apparatus for processing a wafer, the apparatus including:

the obtaining module is used for obtaining the dispatching path of the current batch of wafers; the dispatching path comprises at least one dispatching station for processing the current batch of wafers and a dispatching sequence among the dispatching stations;

the first determining module is used for determining the process program corresponding to each scheduling station; wherein, the corresponding process formulas of at least two scheduling stations with the same process conditions are the same;

and the first dispatching module is used for sequentially dispatching each dispatching station to execute the process programs corresponding to the dispatching stations based on the dispatching sequence so as to carry out process processing on the wafers of the current batch.

An embodiment of the present disclosure provides an apparatus for processing a wafer, the apparatus including: a processor and a memory for storing a computer program operable on the processor, wherein the processor is operable to perform the steps of the method as described above when executing the computer program.

An embodiment of the present disclosure provides a computer storage medium, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the steps of the method as described above.

An embodiment of the present disclosure provides a system for processing a wafer, the system including:

an apparatus for processing a wafer as described above;

and the executive machine executes the process program corresponding to the dispatching station according to the dispatching instruction of the equipment for processing the wafers, and carries out process processing on the wafers of the current batch.

In the embodiment of the disclosure, a dispatching path of a current batch of wafers is obtained, wherein the dispatching path comprises at least one dispatching station for processing the current batch of wafers and a dispatching sequence among the dispatching stations; determining the process programs corresponding to each scheduling station, wherein the process programs corresponding to at least two scheduling stations with the same process conditions are the same; and sequentially dispatching each dispatching station to execute the process program corresponding to the dispatching station based on the dispatching sequence so as to carry out process treatment on the wafers in the current batch. Thus, a process program can be preset in the dispatch site with the same process conditions, and the process program can be directly called in the dispatch site. Therefore, the repetition of the same process program in the flow program of the wafer configuration can be reduced, thereby reducing the occupation of the storage memory by the process program configuration.

Drawings

Fig. 1 is a schematic flow chart illustrating an implementation of a method for processing a wafer according to an embodiment of the disclosure;

fig. 2 is a schematic flow chart illustrating another method for processing a wafer according to an embodiment of the present disclosure;

FIG. 3 is a schematic flow chart illustrating another method for processing a wafer according to an embodiment of the present disclosure;

fig. 4 is a schematic flow chart illustrating another method for processing a wafer according to an embodiment of the present disclosure;

FIG. 5 is a schematic flow chart illustrating another method for processing a wafer according to an embodiment of the present disclosure;

fig. 6a is a schematic structural diagram of an apparatus for processing a wafer according to an embodiment of the present disclosure;

FIG. 6b is a schematic diagram illustrating another apparatus for processing a wafer according to an embodiment of the present disclosure;

FIG. 6c is a schematic diagram illustrating another apparatus for processing a wafer according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of an apparatus for processing a wafer according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram illustrating a system for processing a wafer according to an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features of the art have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual embodiment are described herein, and well-known functions and constructions are not described in detail.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In the related art, when configuring the flow program, the number of scheduled dispatch sites through which the wafer is scheduled is large, and the conditions of the sub-program executed by each dispatch site are complicated. This results in higher cost of allocating process programs and larger amount of process programs, which results in more memory. In the process of implementing the embodiment of the present disclosure, the inventor finds that, when configuring the flow, there are cases where a plurality of scheduling stations correspond to the same machine and process conditions of the plurality of scheduling stations are the same, so that process recipes corresponding to the plurality of scheduling stations are the same. The same process recipe may cause the sub-recipe to be repeated in the process recipe, which may occupy more memory.

On this basis, the embodiment of the present disclosure provides a method for processing a wafer, which presets a process program for a scheduling site with the same process conditions and directly calls the process program at the scheduling site. Therefore, the repetition of the same process program in the flow program of the wafer configuration can be reduced, thereby reducing the occupation of the storage memory by the process program configuration.

Fig. 1 is a schematic flow chart illustrating an implementation of a method for processing a wafer according to an embodiment of the present disclosure, and referring to fig. 1, the embodiment of the present disclosure provides a method for processing a wafer, the method including steps S11 to S13 as follows:

step S11: obtaining a dispatching path of the wafers in the current batch; the dispatching path comprises at least one dispatching station for processing the current batch of wafers and a dispatching sequence among the dispatching stations;

step S12: determining a process program corresponding to each scheduling station; wherein, the corresponding process formulas of at least two scheduling stations with the same process conditions are the same;

step S13: and sequentially scheduling each scheduling station to execute the process program corresponding to the scheduling station based on the scheduling sequence so as to perform process processing on the wafers of the current batch.

Here, the current lot of wafers refers to wafers reserved to the machine. The wafer is not subjected to any processing treatment. The dispatching path comprises at least one dispatching station for processing the current batch of wafers and a dispatching sequence among the dispatching stations. It is understood that the dispatch path is a pre-configured path of the wafer during the fabrication process according to the product requirements. The dispatching path comprises dispatching stations through which the wafer is scheduled to pass and a dispatching sequence of the wafer through each dispatching station in advance. For example, there are N scheduling sites in the scheduling path Rout1, and each scheduling site may be numbered sequentially with 100, 200 \8230andn 00. Alternatively, a dispatch station may be understood as a tool that can perform a process corresponding to a corresponding layer of a wafer. For example, one scheduling station may perform any one of photolithography, etching, ion implantation, thin film deposition, chemical mechanical polishing, and the like corresponding to a certain film layer in a wafer. As another example, photolithography may be a process including gumming, baking, developing, hardening, or exposing. It can be understood that, in the whole scheduling path, multiple scheduling sites corresponding to the execution of multiple sub programs may correspond to the same machine. For example, a plurality of scheduling stations (e.g., scheduling station numbers 300, 700, 1500) corresponding to the execution of a plurality of photolithography process recipes may correspond to the same photolithography tool.

The process recipe includes process parameters for performing a process on the wafer. It is understood that for the current lot of wafers, the process conditions for each scheduled dispatch station and the process at each dispatch station are predetermined according to the product requirements. Therefore, the dispatching sites through which the wafers of the current lot are scheduled to pass and the process programs to be executed by each dispatching site are in corresponding relation.

In some embodiments, the step S12 may include the following step S121:

step S121: inquiring the first matching relation, and determining a process program corresponding to each scheduling station; wherein, the first matching relationship represents the corresponding relationship between the dispatching station and the process program.

Here, the first matching relationship includes a relationship between each dispatching station through which the wafer is scheduled to pass and a process program to be executed by each dispatching station. For example, the first matching relationship may be a corresponding relationship between scheduling site identification information and process program identification information, where the corresponding scheduling site can be determined according to the scheduling site identification information, and the corresponding process program can be determined according to the process program identification information.

In some embodiments, the first matching relationship may be a correspondence between a scheduling site number and a process recipe number. For example, the process program number corresponding to the dispatching site 300 through which the wafer of the current lot passes is recipe1, the process program number corresponding to the dispatching site 700 is recipe 2, and the process program number corresponding to the dispatching site 1500 is recipe1. Accordingly, querying the first matching relationship to determine the process recipe corresponding to each scheduling site may include: and determining process program identification information corresponding to each scheduling station according to the corresponding relation between the scheduling station identification information and the process program identification information, and calling the process program corresponding to each scheduling station according to the process program identification information.

It should be noted that the process recipe corresponding to each dispatch site may be determined when the current lot of wafers is shipped, that is, when the wafer is reserved to the machine and no process is performed yet. In addition, the process recipe corresponding to each dispatching station can be determined when the wafers of the current batch arrive at each corresponding dispatching station.

In addition, the process recipes corresponding to at least two scheduling stations having the same process condition are the same, and it can be understood that when a plurality of scheduling stations correspond to the same machine, the process conditions of the plurality of scheduling stations are the same, and the process recipes corresponding to the scheduling stations having the same process condition are the same. In this case, one process recipe is previously allocated to the scheduling site having the same process recipe. When each dispatching station processes the current batch, the process program can be directly called without setting a process program for each dispatching station. Therefore, the repetition of the same process program in the allocated process program can be reduced, thereby reducing the occupation of the memory for the process program allocation. For example, the recipe corresponding to the current lot of wafers passing through the dispatching site 300 is recipe1, and the recipe corresponding to the dispatching site 1500 is also recipe1. Only one process program, namely the recipe1, needs to be configured in advance, and the recipe1 can be directly called at both the dispatching station 300 and the dispatching station 1500.

In addition, each dispatching station is sequentially dispatched to execute the process program corresponding to the dispatching station based on the dispatching sequence so as to carry out process processing on the wafers of the current batch. Here, each scheduling station is scheduled according to the scheduling sequence, and each scheduling station executes the process program corresponding to the scheduling station. Each dispatching station executes the process program corresponding to the dispatching station until all processes scheduled for the current batch of wafers are processed.

In the embodiment of the disclosure, a dispatching path of a current batch of wafers is obtained, wherein the dispatching path comprises at least one dispatching station for processing the current batch of wafers and a dispatching sequence among the dispatching stations; determining the process programs respectively corresponding to each scheduling station, wherein the process programs corresponding to at least two scheduling stations with the same process conditions are the same; and sequentially dispatching each dispatching station to execute the process program corresponding to the dispatching station based on the dispatching sequence so as to carry out process processing on the wafers of the current batch. Thus, a process program can be preset in the dispatch site with the same process conditions, and the process program can be directly called in the dispatch site. Therefore, the repetition of the same process program in the flow program of the wafer configuration can be reduced, thereby reducing the occupation of the storage memory by the process program configuration.

Fig. 2 is a schematic flow chart illustrating a method for processing a wafer according to another embodiment of the present disclosure, and referring to fig. 2, in some embodiments, the method includes steps S11 to S15:

step S11: obtaining a dispatching path of the current batch of wafers; the dispatching path comprises at least one dispatching station for processing the current batch of wafers and a dispatching sequence among the dispatching stations;

step S12: determining a process program corresponding to each scheduling station; wherein, the corresponding process formulas of at least two scheduling stations with the same process conditions are the same;

step S13: and sequentially scheduling each scheduling station to execute the process program corresponding to the scheduling station based on the scheduling sequence so as to perform process processing on the wafers of the current batch.

Step S14: determining a detection program corresponding to each scheduling station;

step S15: and for each dispatching station, after the dispatching station is dispatched to execute the process program corresponding to the dispatching station, the dispatching station is dispatched to execute the detection program corresponding to the dispatching station so as to detect and process the wafers of the current batch after the process processing.

Here, the inspection program includes inspection parameters for performing an inspection process on the wafer after the process. For example, the detection program may be a pattern shape, a size, a position, a number of test points, and the like of the corresponding product. Determining the detection program corresponding to each dispatching station, it can be understood that, for each dispatching station, after the completion process program is executed to perform the process on the wafer, the wafer is also subjected to the detection process to detect whether the process performed on the wafer of the current batch meets the requirements of the corresponding film layer. For example, after the glue developing station performs glue development on the wafer, a detection unit may be further provided to detect the wafer. For example, the Inspection unit may be a WIS (Wafer Inspection System). When determining the sub-programs of the dispatching sites, besides the process program corresponding to each dispatching site, the detection program of the dispatching site can also be included. In practical applications, different dispatch sites corresponding to the same tool often have the same process conditions and different detection programs. That is, different dispatch sites corresponding to the same tool often have the same process recipe and different detection recipes. For example, in a photoresist coating and developing machine for performing photolithography, different film processing conditions of a wafer are the same, such as the conditions of photoresist, film thickness, temperature of a cold plate and a hot plate, and rotation speed, and the detection conditions are different. It should be noted that, the determining of the inspection program corresponding to the dispatching station can sequentially determine the inspection program corresponding to each dispatching station when the current lot of wafers is delivered, and can also determine the inspection program corresponding to each dispatching station when the current lot of wafers arrives at each corresponding dispatching station.

According to the embodiment of the disclosure, by respectively determining the detection program corresponding to each scheduling site and the process program corresponding to each scheduling site, the situation that the process programs are the same and the detection programs are different at a plurality of scheduling sites can be realized, and support is provided for reducing the occupation of more memories of the machine by the configuration of the process programs. For example, the process recipe and the inspection recipe are separated, one process recipe and a plurality of inspection recipes are configured in advance, and the corresponding process recipe and inspection recipe are determined for each dispatch station. Thereby eliminating the need to configure multiple repeated process recipes and corresponding inspection recipes in the recipe for each lot of wafers. Therefore, the repetition of the same process program at different scheduling sites can be reduced, and the occupation of the storage memory by the process program can be further reduced.

Regarding how to determine the detection program corresponding to each scheduling site, in some embodiments, the step S14 includes the following steps S141:

step S141: inquiring a second matching relation, and determining a detection program corresponding to each scheduling station; and the second matching relationship represents the corresponding relationship between the dispatching station and the detection program.

Here, the second matching relationship includes a relationship between each dispatching station through which the wafer is scheduled to pass and the inspection program to be executed by each dispatching station. For example, the second matching relationship may be a correspondence relationship including scheduling site identification information and detection program identification information.

In some embodiments, the second matching relationship may be a corresponding relationship between the dispatching site number and the inspection program number, for example, the inspection program number corresponding to the dispatching site 300 through which the current lot of wafers pass is WIS recipe1 and the process program number is recipe1, the inspection program number corresponding to the dispatching site 1500 is WIS recipe 3 and the process program number is recipe1. Accordingly, the second matching relationship is queried to determine the detection program corresponding to each scheduling site, for example, the detection program identification information corresponding to each scheduling site is determined according to the corresponding relationship between the scheduling site identification information and the detection program identification information, and the detection program corresponding to the detection program identification information is called according to the detection program identification information.

In the embodiment of the disclosure, the detection program corresponding to each scheduling site can be directly determined by querying the second matching relationship. The corresponding relationship between the inspection program and the dispatching site is determined by the second matching relationship, so that the inspection program and the process program corresponding to the same dispatching site are separately determined without configuring a plurality of repeated process programs and corresponding inspection programs in the flow program of each batch of wafers. Therefore, the repetition of the same process program at different dispatching stations can be reduced, and the occupation of the process program on the storage memory can be further reduced.

In addition, for each dispatching station, after the dispatching station is dispatched to execute the process program corresponding to the dispatching station, the dispatching station is dispatched to execute the detection program corresponding to the dispatching station, so as to perform detection processing on the wafers of the current batch after the process processing. The dispatching station is dispatched to execute the detection program corresponding to the dispatching station, and after the dispatching station is dispatched to execute the process program corresponding to the dispatching station, whether the process of the current batch of wafers in the dispatching station meets the requirement of preparing the corresponding product or not is determined.

Fig. 3 is a schematic flow chart illustrating a method for implementing another wafer processing according to an embodiment of the disclosure, and referring to fig. 3, in some embodiments, the method includes steps S11 to S151:

step S11: obtaining a dispatching path of the wafers in the current batch; the dispatching path comprises at least one dispatching station for processing the current batch of wafers and a dispatching sequence among the dispatching stations;

step S12: determining a process program corresponding to each scheduling station; wherein, the corresponding process formulas of at least two scheduling stations with the same process conditions are the same;

step S13: and sequentially dispatching each dispatching station to execute the process program corresponding to the dispatching station based on the dispatching sequence so as to carry out process treatment on the wafers of the current batch.

Step S14: determining a detection program corresponding to each scheduling station;

step S16: determining a target detection ratio corresponding to each scheduling station;

step S151: and scheduling the scheduling station to execute the detection program corresponding to the scheduling station based on the target detection ratio corresponding to the scheduling station.

Here, the target inspection ratio corresponding to each dispatching station is determined, and it can be understood that each dispatching station performs an inspection process on the wafer after performing a process on the wafer. In practical applications, different lots of wafers flowing through the same dispatch site are sampled. It is understood that the target inspection ratio is a preset ratio of different lots of wafers processed by the inspection process after the processing at the same dispatch station.

Regarding how to determine the target detection ratio corresponding to the scheduling station, in some embodiments, the step S16 includes the step S161:

step S161: inquiring a third matching relation, and determining a target detection ratio corresponding to each scheduling station; and the third matching relationship represents the corresponding relationship between the scheduling site and the target detection ratio.

Here, the third matching relationship includes a relationship between each scheduled station through which the wafer is scheduled to pass and a target inspection ratio of each scheduled station.

In some embodiments, the third matching relationship may be a correspondence relationship between the scheduled station identification information and the target detection ratio. For example, the detection ratio for the scheduling station 300 is 50%, the detection ratio for the scheduling station 700 is 100%, and the detection ratio for the scheduling station 1500 is 50%.

The step S15 includes the step S151:

step S151: and scheduling the scheduling station to execute a detection program corresponding to the scheduling station based on the target detection ratio corresponding to the scheduling station.

Here, after the target inspection ratio corresponding to each dispatch station is determined, after the current wafer flows to a dispatch station, whether the inspection process is performed at the dispatch station is determined according to the target inspection ratio of the dispatch station. And sequentially determining whether the wafers in the current batch are detected and processed at each dispatching station or not according to the sequence of the dispatching stations until the wafers flow out of the last dispatching station, and finishing the processing of each film layer of the wafers in the current batch to form each film layer meeting the product requirements.

Fig. 4 is a schematic flow chart illustrating an implementation of another method for processing a wafer according to an embodiment of the disclosure, and referring to fig. 4, in some embodiments, the method further includes steps S11 to S18:

step S11: obtaining a dispatching path of the current batch of wafers; the dispatching path comprises at least one dispatching station for processing the current batch of wafers and a dispatching sequence among the dispatching stations;

step S12: determining a process program corresponding to each scheduling station; wherein, the corresponding process formulas of at least two scheduling stations with the same process conditions are the same;

step S13: and sequentially dispatching each dispatching station to execute the process program corresponding to the dispatching station based on the dispatching sequence so as to carry out process treatment on the wafers of the current batch.

Step S14: determining a detection program corresponding to each scheduling station;

step S16: determining a target detection ratio corresponding to each scheduling station;

step S151: scheduling the scheduling station to execute a detection program corresponding to the scheduling station based on the target detection ratio corresponding to the scheduling station;

step S17: for each dispatching station, acquiring a first waiting time consumed by the detection processing of at least one batch of historical batch wafers at the dispatching station, and updating a target detection ratio corresponding to the dispatching station based on the first waiting time;

step S18: and updating the third matching relationship based on the updated target detection ratio corresponding to at least one scheduling station.

Here, the first waiting time is a waiting time for a dispatching station where the historical lot wafers are detected and processed. For example, the first waiting duration may be a waiting duration consumed by the historical lot of wafers after the process units in a dispatching station perform the process treatment until the detection units enter the dispatching station. The first wait time can be used to characterize whether the inspection unit is a bottleneck unit of productivity. For example, when the first waiting time is greater than the preset threshold, the detection unit is characterized as a capacity bottleneck unit. When the first waiting time is less than the preset threshold value, the characteristic detection machine does not influence the wafer processing capacity. It can be understood that, when the first waiting time is less than the preset threshold, it may reflect that the time consumed for the detection unit and the process unit to perform the processing is similar or the same, and may reflect that the time consumed for the detection unit to perform the detection processing is much less than the time consumed for the process unit to perform the processing.

In some other embodiments, the parameter characterizing the inspection unit as the capacity bottleneck may be: and for each dispatching station, historical batch wafers wait for the first waiting wafer number between the process unit and the detection unit. For example, when the number of the first waiting wafers is greater than the predetermined number, the inspection unit is characterized as a capacity bottleneck unit. Therefore, the target detection ratio corresponding to the dispatching station can be reduced under the condition that the number of the first waiting wafers corresponding to the dispatching station is greater than the preset number; and under the condition that the number of the first waiting wafers corresponding to the dispatching station is less than or equal to the preset number, increasing the target detection ratio corresponding to the dispatching station.

And updating the target detection ratio corresponding to the scheduling station based on the first waiting time length. And adjusting the target detection ratio of the current batch of wafers corresponding to the dispatching station according to the first waiting time length. In this way, the time period for the current lot of wafers to pass through the dispatching station can be optimized.

Regarding how to update the target detection ratio corresponding to the scheduling station based on the first waiting duration, in some embodiments, the step S17 includes steps S171 to S172:

step S171: reducing a target detection ratio corresponding to the scheduling station under the condition that the first waiting time is greater than a first time threshold;

step S172: and under the condition that the first waiting time is less than or equal to a second time threshold, increasing the target detection ratio corresponding to the scheduling station, wherein the second time threshold does not exceed the first time threshold.

Here, the first latency is greater than the first latency threshold, which indicates that the detecting unit in the scheduling site is a capacity bottleneck unit. And when the first waiting time length is greater than a first time length threshold value, reducing the target detection ratio corresponding to the scheduling station. For example, the first time threshold is 15s, and when the first waiting time consumed after the wafer process is finished and before the wafer process enters the detection unit is longer than 15s, the target detection ratio corresponding to the scheduling station is reduced. The first waiting time is smaller than or larger than the second time threshold, which indicates that the detection unit in the scheduling site has sufficient time for detection, and the process unit is a capacity bottleneck unit. The target detection ratio is reduced, and the time for detection processing by the detection unit can be reduced. Therefore, when the detection unit is the bottleneck of the wafer processing capacity, the total capacity of the wafer processing is improved.

In some other embodiments, the time for performing the inspection process by the inspection unit corresponding to the dispatch station can be reduced by optimizing the inspection program, so as to improve the productivity when the inspection unit is the bottleneck unit. For example, the number of detection points in the detection program can be reduced, and the whole inspection is adjusted to point inspection; or the number of detection point positions of point detection is reduced.

And when the first waiting time is less than or greater than a second time threshold, increasing the target detection ratio corresponding to the scheduling station. For example, the second duration threshold is 10s, and when the second waiting duration consumed after the wafer process is finished and before the wafer process enters the detection unit is less than 10s, the target detection ratio corresponding to the scheduling station is increased. The target detection ratio is increased, and the time difference between the detection unit and the process unit can be reduced, so that the number of wafers detected and processed by the detection unit within a period of time is increased, and the utilization rate of the detection unit is increased.

It should be noted that the first waiting time is between the second time threshold and the first time threshold, and the time difference between the detection by the detection unit representing the scheduling station and the process by the process unit is reasonable. The current batch of wafers can continue to adopt the original target detection ratio without adjusting the target detection ratio. Here, the second duration threshold may be the same as the first duration threshold or may be smaller than the first duration threshold.

In the embodiment of the disclosure, the first waiting time is respectively compared with the first time threshold and the second time threshold, and the target detection ratio corresponding to the scheduling station is updated. In this way, the time difference between the detection unit and the process unit in each dispatch station can be optimized. On one hand, the time difference between the detection unit and the process unit is optimized, so that the total energy of wafer processing can be improved when the detection unit is the bottleneck of the wafer processing. On the one hand, the time difference between the detection unit and the process unit is optimized, the utilization rate of the detection unit can be improved, and the wafer is guaranteed to be subjected to the spot inspection with the maximum rate so as to meet the performance requirements of each film layer of the wafer.

In addition, the third matching relationship is updated based on an updated target detection ratio corresponding to at least one of the scheduling sites. Here, since the third matching relationship includes a relationship between each scheduled station through which the wafer is scheduled to pass and a target inspection ratio of each scheduled station. And when the target detection ratio corresponding to the scheduling station is changed, correspondingly updating the changed target detection ratio in the third matching relationship.

According to the embodiment of the disclosure, by judging whether the capacity of the detection unit is the capacity bottleneck or not, adjusting the target detection ratio based on the judgment result and updating the target detection ratio into the third matching relationship, a support can be provided for directly calling the target detection ratio considering both the capacity and the sampling rate for subsequent wafer processing.

Fig. 5 is a schematic flow chart illustrating an implementation of another method for processing a wafer according to an embodiment of the disclosure, and referring to fig. 5, in some embodiments, the method includes steps S11 to S1512:

step S11: obtaining a dispatching path of the current batch of wafers; the dispatching path comprises at least one dispatching station for processing the current batch of wafers and a dispatching sequence between the dispatching stations;

step S12: determining a process program corresponding to each scheduling station; wherein, the corresponding process formulas of at least two scheduling stations with the same process conditions are the same;

step S13: and sequentially scheduling each scheduling station to execute the process program corresponding to the scheduling station based on the scheduling sequence so as to perform process processing on the wafers of the current batch.

Step S14: determining a detection program corresponding to each scheduling station;

step S16: determining a target detection ratio corresponding to each scheduling station;

step S1511: acquiring the current detection ratio of the dispatching station for detecting and processing the historical batch of wafers;

step S1512: and scheduling the scheduling station to execute a detection program corresponding to the scheduling station based on the target detection ratio and the current detection ratio.

Regarding how to determine the current detection ratio, in some embodiments, the above step S1511 includes steps S15111 to S15112:

step S15111: determining a first calling frequency of a process program corresponding to the scheduling site and a second calling frequency of a detection program corresponding to the scheduling site;

step S15112: and determining the current detection ratio based on the first calling times and the second calling times.

Step S1512: and scheduling the scheduling station to execute a detection program corresponding to the scheduling station based on the target detection ratio and the current detection ratio.

Here, the current inspection ratio is a ratio of the historical lot wafers to be processed after being processed at a dispatch station. The current detection rate of any scheduling site can be determined according to the number of times that the scheduling site calls the process program and the number of times that the scheduling site calls the detection program.

And calling a detection program corresponding to the dispatching station based on the target detection ratio and the current detection ratio to detect and process the wafers of the current batch after the process treatment. For example, whether to perform the inspection process on the wafers of the current lot after the process processing according to the inspection program is determined according to the target inspection ratio and the current inspection ratio. For example, when the current lot of wafers is the first lot of wafers, the current inspection ratio of any dispatching station is zero, and at this time, any dispatching station performs inspection processing according to the inspection program. And when the current batch of wafers is the second batch of wafers, comparing the magnitude relation between the current detection ratio and the target detection ratio to determine whether each dispatching station carries out detection processing. If the detection ratio of the current batch of wafers is less than or equal to the target detection ratio, the current batch of wafers after the process treatment is detected according to the detection program.

In some embodiments, the step S1512 includes the step S15121:

step S15121: and scheduling the scheduling station to execute a detection program corresponding to the scheduling station when the current detection ratio is smaller than or equal to the target detection ratio.

Here, when the current inspection ratio is less than or equal to the target inspection ratio, the inspection process is performed on the wafers of the current lot after the process processing according to the inspection program. In some other embodiments, if the inspection ratio of the current lot of wafers is greater than the target inspection ratio, the inspection process is skipped for the current lot of wafers. For example, the target detection ratio for the scheduling station with the number 300 is 50%. When the current batch of wafers is the first batch of wafers, the current detection ratio of the dispatching station is zero and is less than 50% of the target detection ratio, so that the first batch of wafers are detected; when the second batch of wafers are delivered, the current detection ratio of the dispatching station is 100%, and the current detection ratio is 100% and is greater than the target detection ratio by 50%, so that the second batch of wafers skip the detection processing; when the third lot of wafers are delivered, the current inspection ratio of the dispatching station is 50%, and the current inspection ratio 50% is equal to the target inspection ratio 50%, so the third lot of wafers are inspected after the process according to the inspection program.

In the embodiment of the disclosure, whether the wafers in the current batch are detected or not is determined by comparing the current detection ratio with the target detection ratio, so as to ensure sampling detection of the wafers after the process treatment of each dispatching station, and further determine whether the process treatment performed by each dispatching station meets the product requirements or not.

Fig. 6a is a schematic structural view of an apparatus for processing a wafer according to an embodiment of the present disclosure, and referring to fig. 6a, an embodiment of the present disclosure provides an apparatus for processing a wafer, the apparatus 60 including:

an obtaining module 61, configured to obtain a dispatching path of a current batch of wafers; the dispatching path comprises at least one dispatching station for processing the current batch of wafers and a dispatching sequence between the dispatching stations;

a first determining module 62, configured to determine a process recipe corresponding to each scheduling station; wherein, the corresponding process formulas of at least two scheduling stations with the same process conditions are the same;

the first dispatching module 63 is configured to sequentially dispatch each dispatching station to execute the process program corresponding to the dispatching station based on the dispatching sequence, so as to perform the process processing on the current lot of wafers.

Here, in practical applications, the obtaining module 61, the first determining module 62 and the first scheduling module 63 may be configured in an EAP (Equipment Automation Program). For example, the scheduling path of MM (Material Management) transmission is acquired by EAP. And determining the process corresponding to each dispatching station by the EDP, and sequentially dispatching each dispatching station to execute the process program corresponding to the dispatching station based on the dispatching sequence so as to perform process processing on the wafers of the current batch.

In some embodiments, the first determining module 62 is further configured to query the first matching relationship, and determine a process recipe corresponding to each scheduling station; wherein, the first matching relationship represents the corresponding relationship between the dispatching station and the process program.

Fig. 6b is a schematic structural diagram of another apparatus for processing a wafer according to an embodiment of the disclosure, and referring to fig. 6b, in some embodiments, the apparatus further includes:

a second determining module 64, configured to determine a detection program corresponding to each scheduling station;

a second dispatching module 65, configured to, for each dispatching station, dispatch the dispatching station to execute the detection program corresponding to the dispatching station after the dispatching station executes the process program corresponding to the dispatching station, so as to perform detection processing on the current lot of wafers after processing.

In some embodiments, the second determining module 65 is further configured to query the second matching relationship, and determine a detecting program corresponding to each scheduling site; and the second matching relationship represents the corresponding relationship between the dispatching station and the detection program.

Fig. 6c is a schematic structural diagram of another apparatus for processing a wafer according to an embodiment of the disclosure, and referring to fig. 6c, in some embodiments, the apparatus further includes:

a third determining module 66, configured to determine a target detection ratio corresponding to each scheduling station;

the second dispatching module 65 is further configured to dispatch the dispatching station to execute the testing program corresponding to the dispatching station based on the target testing ratio corresponding to the dispatching station, so as to perform testing processing on the current batch of wafers after the processing.

In some embodiments, the third determining module 66 is further configured to query a third matching relationship, and determine a target detection ratio corresponding to each scheduling station; and the third matching relation represents the corresponding relation between the scheduling site and the target detection ratio.

For example, the second determining module and the third determining module may be disposed in a big data system, and determine the target detection ratio and the detection program corresponding to each scheduling station through the big data system, and send the determined target detection ratio and the detection program corresponding to the scheduling station to the second scheduling module. And dispatching the dispatching station to execute the detection program corresponding to the dispatching station by a second dispatching module based on the target detection ratio corresponding to the dispatching station so as to detect and process the wafers of the current batch after the process treatment.

In some embodiments, the apparatus further comprises:

an updating module 67, configured to obtain, for each dispatching station, a first waiting duration consumed for performing detection processing on at least one batch of historical batch wafers at the dispatching station, and update a target detection ratio corresponding to the dispatching station based on the first waiting duration; and updating the third matching relation based on the updated target detection ratio corresponding to at least one scheduling station.

In some embodiments, the updating module 67 is further configured to decrease the target detection ratio corresponding to the scheduling station if the first waiting time is greater than a first time threshold; and under the condition that the first waiting time is less than or equal to a second time threshold, increasing the target detection ratio corresponding to the scheduling station, wherein the second time threshold does not exceed the first time threshold.

In some embodiments, the second dispatching module 65 is further configured to obtain a current inspection ratio of the dispatching station to perform inspection processing on the historical lots of wafers; and dispatching the dispatching station to execute a detection program corresponding to the dispatching station based on the target detection ratio and the current detection ratio so as to detect and process the wafers of the current batch after the process processing.

In some embodiments, the second scheduling module 65 is further configured to schedule the dispatching station to execute the inspection program corresponding to the dispatching station to perform the inspection process on the current lot of wafers after the processing if the current inspection ratio is smaller than or equal to the target inspection ratio.

In some embodiments, the second scheduling module 65 is further configured to determine a first number of times of calling the process program corresponding to the scheduling site, and a second number of times of calling the detection program corresponding to the scheduling site; and determining the current detection ratio based on the first calling times and the second calling times.

The wafer processing device has similar beneficial effects with the method for processing the wafer. For technical details not disclosed in embodiments of the apparatus for processing wafers according to the present disclosure, reference is made to the description of embodiments of the method for processing wafers.

An embodiment of the present disclosure provides an apparatus for processing a wafer, the apparatus including: a processor and a memory for storing a computer program capable of running on the processor,

wherein the processor is adapted to perform the steps of the method as described above when running the computer program.

An embodiment of the present disclosure provides a computer storage medium, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the steps of the method as described above. The computer readable storage medium may be transitory or non-transitory.

It should be noted that fig. 7 is a schematic structural diagram of an apparatus for processing a wafer according to an embodiment of the present disclosure, and as shown in fig. 7, an apparatus 70 for processing a wafer includes: a processor 71, a communication interface 72, and a memory 73, wherein:

the processor 71 generally controls the overall operation of the apparatus 70 for processing wafers.

The communication interface 72 may enable the apparatus 70 for processing wafers to communicate with other terminals or servers via a network.

The Memory 73 is configured to store instructions and applications executable by the processor 71, and may also buffer data (e.g., image data, audio data, voice communication data, and video communication data) to be processed or already processed by each module in the apparatus 70 for processing a wafer and the processor 71, and may be implemented by a FLASH Memory (FLASH) or a Random Access Memory (RAM). Data transfer between the processor 71, the communication interface 72 and the memory 73 may be performed via a bus 74.

Fig. 8 is a schematic structural diagram of a system for processing a wafer according to an embodiment of the present disclosure, and as shown in fig. 8, the system 800 for processing a wafer includes:

an apparatus 70 for processing wafers as described above;

and the execution machine 80 executes the process program corresponding to the dispatching station according to the dispatching instruction of the wafer processing equipment, and performs process processing on the wafers of the current batch.

Here, it should be noted that: the above description of the storage medium, device and system embodiments is similar to the description of the method embodiments above, with similar benefits as the method embodiments. For technical details not disclosed in the embodiments of the storage medium and apparatus of the present disclosure, reference is made to the description of the embodiments of the method of the present disclosure.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description and do not represent the merits of the embodiments.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or in other forms.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units; can be located in one place or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as a removable Memory device, a Read Only Memory (ROM), a magnetic disk, or an optical disk.

Alternatively, the integrated unit of the present disclosure may be stored in a computer-readable storage medium if it is implemented in the form of a software functional module and sold or used as a separate product. Based on such understanding, the technical solutions of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing an electronic device (which may be a personal computer, a server, or a network device) to execute all or part of the methods according to the embodiments of the present disclosure. And the aforementioned storage medium includes: a removable storage device, a ROM, a magnetic or optical disk, or other various media that can store program code.

The above description is only a few embodiments of the present disclosure, but the scope of the embodiments of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the embodiments of the present disclosure, and all the changes or substitutions should be covered by the scope of the embodiments of the present disclosure.

Claims (16)

1. A method of processing a wafer, the method comprising:

obtaining a dispatching path of the current batch of wafers; the dispatching path comprises at least one dispatching station for processing the current batch of wafers and a dispatching sequence among the dispatching stations;

determining a process program corresponding to each scheduling station; wherein, the corresponding process formulas of at least two scheduling stations with the same process conditions are the same;

and sequentially dispatching each dispatching station to execute the process program corresponding to the dispatching station based on the dispatching sequence so as to carry out process treatment on the wafers of the current batch.

2. The method of claim 1, wherein the determining the process recipe corresponding to each dispatch site comprises:

inquiring a first matching relation, and determining a process program corresponding to each scheduling station; wherein, the first matching relationship represents the corresponding relationship between the dispatching station and the process program.

3. The method of claim 1, further comprising:

determining a detection program corresponding to each scheduling station;

and for each dispatching station, after the dispatching station is dispatched to execute the process program corresponding to the dispatching station, the dispatching station is dispatched to execute the detection program corresponding to the dispatching station so as to detect and process the wafers of the current batch after the process processing.

4. The method of claim 3, wherein the determining the detection formula corresponding to each scheduling station comprises:

inquiring a second matching relation, and determining a detection program corresponding to each scheduling station; and the second matching relationship represents the corresponding relationship between the dispatching station and the detection program.

5. The method of claim 4, further comprising:

determining a target detection ratio corresponding to each scheduling station;

the dispatching station to execute the detection program corresponding to the dispatching station so as to detect and process the current batch of wafers after the process treatment, including:

and scheduling the scheduling station to execute the detection program corresponding to the scheduling station based on the target detection ratio corresponding to the scheduling station.

6. The method of claim 5, wherein the determining the target detection ratio for each of the plurality of scheduling stations comprises:

inquiring a third matching relation, and determining a target detection ratio corresponding to each scheduling station; and the third matching relationship represents the corresponding relationship between the scheduling site and the target detection ratio.

7. The method of claim 6, further comprising:

for each dispatching station, acquiring a first waiting time length consumed by detection processing of at least one batch of historical batch wafers at the dispatching station, and updating a target detection ratio corresponding to the dispatching station based on the first waiting time length;

and updating the third matching relation based on the updated target detection ratio corresponding to at least one scheduling station.

8. The method of claim 7, wherein updating the target detection ratio corresponding to the scheduled station based on the first wait duration comprises:

reducing a target detection ratio corresponding to the scheduling station under the condition that the first waiting time is greater than a first time threshold;

and under the condition that the first waiting time is less than or equal to a second time threshold, increasing the target detection ratio corresponding to the scheduling station, wherein the second time threshold does not exceed the first time threshold.

9. The method according to claim 5, wherein the scheduling station to execute the detection program corresponding to the scheduling station based on the target detection ratio corresponding to the scheduling station comprises:

acquiring the current detection ratio of the dispatching station for detecting and processing the historical batch of wafers;

and scheduling the scheduling station to execute a detection program corresponding to the scheduling station based on the target detection ratio and the current detection ratio.

10. The method according to claim 9, wherein said scheduling the dispatching station to execute the detection program corresponding to the dispatching station based on the target detection ratio and the current detection ratio comprises:

and scheduling the scheduling station to execute a detection program corresponding to the scheduling station when the current detection ratio is smaller than or equal to the target detection ratio.

11. The method as claimed in claim 9, wherein said obtaining the current inspection ratio of the dispatching site to the inspection process of the historical lots of wafers comprises:

determining a first calling frequency of a process program corresponding to the scheduling site and a second calling frequency of a detection program corresponding to the scheduling site;

and determining the current detection ratio based on the first calling times and the second calling times.

12. An apparatus for processing a wafer, the apparatus comprising:

the obtaining module is used for obtaining the dispatching path of the current batch of wafers; the dispatching path comprises at least one dispatching station for processing the current batch of wafers and a dispatching sequence among the dispatching stations;

the first determining module is used for determining the process program corresponding to each scheduling station; wherein, the corresponding process formulas of at least two scheduling stations with the same process conditions are the same;

and the first dispatching module is used for sequentially dispatching each dispatching station to execute the process program corresponding to the dispatching station based on the dispatching sequence so as to carry out process processing on the wafers of the current batch.

13. The apparatus of claim 12, further comprising:

a second determining module, configured to determine a detection program corresponding to each scheduling station;

and the second dispatching module is used for dispatching the dispatching station to execute the detection program corresponding to the dispatching station after the dispatching station executes the process program corresponding to the dispatching station aiming at each dispatching station so as to detect and process the wafers of the current batch after the process processing.

14. An apparatus for processing a wafer, the apparatus comprising: a processor and a memory for storing a computer program operable on the processor, wherein the processor is operable to perform the steps of the method of any of claims 1 to 11 when executing the computer program.

15. A computer storage medium on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 11.

16. A system for processing a wafer, the system comprising:

the apparatus for processing a wafer of claim 14;

and the executive machine executes the process program corresponding to the dispatching station according to the dispatching instruction of the equipment for processing the wafers, and carries out process processing on the wafers of the current batch.

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