CN115936127B - Quantum technology-based numerical comparison method and device and quantum computer - Google Patents

Quantum technology-based numerical comparison method and device and quantum computer Download PDF

Info

Publication number
CN115936127B
CN115936127B CN202111163459.XA CN202111163459A CN115936127B CN 115936127 B CN115936127 B CN 115936127B CN 202111163459 A CN202111163459 A CN 202111163459A CN 115936127 B CN115936127 B CN 115936127B
Authority
CN
China
Prior art keywords
quantum
module
value
quantum state
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202111163459.XA
Other languages
Chinese (zh)
Other versions
CN115936127A (en
Inventor
方圆
王伟
李蕾
窦猛汉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Benyuan Quantum Computing Technology Hefei Co ltd
Original Assignee
Benyuan Quantum Computing Technology Hefei Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Benyuan Quantum Computing Technology Hefei Co ltd filed Critical Benyuan Quantum Computing Technology Hefei Co ltd
Priority to CN202111163459.XA priority Critical patent/CN115936127B/en
Publication of CN115936127A publication Critical patent/CN115936127A/en
Application granted granted Critical
Publication of CN115936127B publication Critical patent/CN115936127B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Logic Circuits (AREA)

Abstract

The application provides a numerical comparison method and device based on a quantum technology and a quantum computer. The method of the embodiment of the application comprises the following steps: obtaining a first value and a second value to be compared, preparing the first value and the second value into a first quantum state and a second quantum state respectively, operating a preset quantum circuit, wherein the preset quantum circuit is used for carrying out subtraction operation on the first quantum state and the second quantum state, measuring preset quantum bits of the preset quantum circuit, obtaining difference sign bits of the first quantum state and the second quantum state according to a measurement result, and determining the magnitude relation between the first value and the second value according to the difference sign bits. The application can realize the comparison of the values among integers through the quantum circuit, and fills the blank of the related technology.

Description

Quantum technology-based numerical comparison method and device and quantum computer
Technical Field
The invention belongs to the field of quantum computing, and particularly relates to a numerical comparison method and device based on a quantum technology and a quantum computer.
Background
Quantum computers use the superposition of quanta and in theory have the ability to accelerate exponentially in some cases. For example, cracking RSA keys takes hundreds of years on classical computers, while executing quantum algorithms on quantum computers takes only a few hours. However, the current quantum computer is limited by the limited number of controllable bits caused by the development of quantum chip hardware, so that the computing power is limited, and the quantum algorithm cannot be universally run. Generally, quantum algorithms are operated by quantum subtraction.
In the implementation process of the quantum algorithm, the quantum algorithm is generally required to be built by means of various quantum logic gates, but when the quantum algorithm is built by means of various quantum logic gates, the quantum logic gates corresponding to the operation of a relatively large size between two integers of classical operation are not available. Therefore, it is highly desirable to provide a technique capable of realizing numerical comparison in a quantum wire, so as to fill the gap of the related art.
Disclosure of Invention
The invention aims to provide a numerical comparison method and device based on a quantum technology and a quantum computer, which are used for solving the defects in the prior art and can realize the comparison of numerical values among integers through a quantum circuit.
In a first aspect, the present application provides a quantum technology-based numerical comparison method, comprising:
obtaining a first numerical value and a second numerical value to be compared, and preparing a first quantum state and a second quantum state by respectively corresponding the first numerical value and the second numerical value;
Running a preset quantum circuit, wherein the preset quantum circuit is used for carrying out subtraction operation on the first quantum state and the second quantum state;
Measuring preset quantum bits of the preset quantum circuit, and acquiring difference sign bits of the first quantum state and the second quantum state according to a measurement result;
and determining the magnitude relation between the first numerical value and the second numerical value according to the difference sign bit.
The method of claim 1, wherein the preparing the first and second values into first and second quantum states, respectively, comprises:
And respectively encoding the first numerical value and the second numerical value according to an H gate and a RY gate to obtain the first quantum state and the second quantum state, wherein the encoding parameters are determined by the first numerical value and the second numerical value, and the H gate and the RY gate are one type of quantum logic gate.
Optionally, the obtaining the sign bit of the difference between the first quantum state and the second quantum state according to the measurement result includes:
measuring sign bit quantum bits of difference sign bits corresponding to subtraction operation in the preset quantum circuit, and obtaining quantum states of the sign bit quantum bits;
And determining the value of the difference sign bit according to the quantum state of the sign bit quantum bit.
Optionally, the obtaining the magnitude relation between the first value and the second value according to the difference sign bit includes:
If the value of the difference sign bit is 0, the first value is smaller than the second value;
and if the value of the difference sign bit is 1, the first value is larger than the second value.
Optionally, the preset quantum circuit includes: the adder module and the complementary code module comprises the adder module; wherein the adder module is constructed in the following manner:
Determining the number of target modules of a front cascade module MAJ module to be cascaded and a rear cascade module UMA module to be cascaded according to the number of quantum bits corresponding to the first quantum state and the second quantum state, wherein the number of the modules of the MAJ module is the same as the number of the modules of the UMA module;
And cascading the MAJ modules and UMA modules with the number of the target modules to generate adder sub-quantum circuits corresponding to the adder modules.
Optionally, the MAJ module and the UMA module are constructed according to a CNOT gate and a TOFFOLI gate, and the CNOT gate and the TOFFOLI gate are both one of quantum logic gates.
In a second aspect, the present application provides a quantum technology-based numerical comparison device, comprising:
The device comprises an acquisition unit, a comparison unit and a comparison unit, wherein the acquisition unit is used for acquiring a first numerical value and a second numerical value to be compared, and preparing the first numerical value and the second numerical value into a first quantum state and a second quantum state respectively;
The operation unit is used for operating a preset quantum circuit, and the preset quantum circuit is used for carrying out subtraction operation on the first quantum state and the second quantum state;
The measuring unit is used for measuring the operation result of the quantum circuit and acquiring the difference value between the first quantum state and the second quantum state according to the operation result;
And the determining unit is used for determining the magnitude relation between the first numerical value and the second numerical value according to the difference value.
In a third aspect, an embodiment of the present application provides an electronic device, including a processor, a memory, a communication interface, and one or more programs, where the one or more programs are stored in the memory and configured to be executed by the processor, and the programs include instructions for performing steps in the method according to the first aspect of the embodiment of the present application.
In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program for electronic data exchange, where the computer program causes a computer to perform some or all of the steps described in the method according to the first aspect of the embodiment of the present application.
In a fifth aspect, embodiments of the present application provide a computer program product, wherein the computer program product comprises a non-transitory computer readable storage medium storing a computer program, the computer program being operable to cause a computer to perform some or all of the steps described in the method according to the first aspect of the embodiments of the present application. The computer program product may be a software installation package.
In a sixth aspect, an embodiment of the present application provides a quantum computer, where the quantum computer includes a quantum computer operating system, where the quantum computer operating system implements a quantum technology-based numerical comparison process according to some or all of the steps described in the method according to the first aspect of the embodiment of the present application.
Drawings
Fig. 1 is a schematic flow chart of a quantum technology-based numerical comparison method according to an embodiment of the present application;
FIG. 2 is a schematic flow chart of a quantum-technology-based numerical comparison method according to an embodiment of the present application;
FIG. 3 is another flow chart of a quantum technology-based numerical comparison method according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a quantum circuit for quantum state fabrication according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a complementary code quantum circuit according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a quantum circuit of a complementary code before addition operation provided by the application;
FIG. 7 is a schematic diagram of a complementary code quantum circuit after addition according to the present application;
FIG. 8 is a schematic diagram of a quantum circuit of the subtractor provided by the present application;
FIG. 9 is a schematic diagram of an adder according to an embodiment of the present application;
FIG. 10 is a schematic diagram of an adder quantum circuit according to an embodiment of the present application;
FIG. 11 is a schematic diagram of an MAJ module according to one embodiment of the present application;
FIG. 12 is a schematic diagram of a MAJ module quantum circuit assembly process according to one embodiment of the present application;
fig. 13 is a schematic diagram of a UMA module provided in an embodiment of the present application;
Fig. 14 is a schematic diagram of a UMA module quantum wire assembly process according to an embodiment of the present application;
Fig. 15 is a schematic diagram of a numerical comparison device based on quantum technology according to an embodiment of the present application;
Fig. 16 is a hardware block diagram of a computer terminal according to a numerical comparison method based on quantum technology according to an embodiment of the present application.
Detailed Description
The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
The application provides a numerical comparison method based on a quantum technology, which solves the defects in the prior art and can realize the comparison of numerical values among integers through a quantum circuit.
It should be noted that, the quantum program referred to in the embodiments of the present application is a program written in a classical language to characterize qubits and their evolution, where qubits, quantum logic gates, and the like related to quantum computation are all represented by corresponding classical codes.
Quantum circuits, which are one embodiment of quantum programs, also weigh sub-logic circuits, are the most commonly used general quantum computing models, representing circuits that operate on qubits under an abstract concept, the composition of which includes qubits, circuits (timelines), and various quantum logic gates, and finally the results often need to be read out by quantum measurement operations. The quantum circuit may be presented in a sequence of quantum logic gates arranged in a certain execution timing sequence.
Unlike conventional circuits that are connected by metal lines to pass voltage or current signals, in quantum circuits, the circuits can be seen as being connected by time, i.e., the state of the qubit naturally evolves over time, as indicated by the hamiltonian operator, during which the circuit is operated until the quantum logic gate is encountered.
One quantum program is corresponding to one total quantum circuit, and the quantum program refers to the total quantum circuit, wherein the total number of quantum bits in the total quantum circuit is the same as the total number of quantum bits of the quantum program. It can be understood that: one quantum program may consist of a quantum circuit, a measurement operation for the quantum bits in the quantum circuit, a register to hold the measurement results, and a control flow node (jump instruction), and one quantum circuit may contain several tens to hundreds or even thousands of quantum logic gate operations. The execution process of the quantum program is a process of executing all quantum logic gates according to a certain time sequence. Note that the timing is the time sequence in which a single quantum logic gate is executed.
It should be noted that in classical computation, the most basic unit is a bit, and the most basic control mode is a logic gate, and the purpose of the control circuit can be achieved by a combination of logic gates. Similarly, the way in which the qubits are handled is a quantum logic gate. Quantum logic gates are used, which are the basis for forming quantum lines, and include single-bit quantum logic gates (or single-quantum logic gates, abbreviated as "single gates"), such as Hadamard gates (H gates, ada Ma Men), bery-X gates (X gates), bery-Y gates (Y gates), bery-Z gates (Z gates), RX gates, RY gates, RZ gates, and the like; two-bit quantum logic gates (or double quantum logic gates, simply "double gates"), such as CNOT gates, CR gates, SWAP gates, ISWAP gates, and the like; multi-bit quantum logic gates (or multi-quantum logic gates, simply "multi-gates"), such as Toffoli gates, and the like. Quantum logic gates are typically represented using unitary matrices, which are not only in matrix form, but also an operation and transformation. The effect of a general quantum logic gate on a quantum state is calculated by multiplying the unitary matrix by the matrix corresponding to the right vector of the quantum state. For example, the vector corresponding to the quantum state right vector |0> isThe vector corresponding to the quantum state right vector |1> is/>
Quantum states, i.e., the logical states of a qubit. In the quantum algorithm (or weighing subroutine), for the quantum states of a group of quantum bits contained in the quantum circuit, a binary expression mode is adopted, for example, the group of quantum bits are q0, q1 and q2, the 0 th, 1 st and 2 nd quantum bits are represented, the q2q1q0 are ordered from high order to low order in the binary expression mode, the quantum states corresponding to the group of quantum bits are in total number of 2 quantum bits to the power of the total number of the quantum bits, namely 8 eigenstates (determined states): the bits of each quantum state correspond to the quantum bits in correspondence, such as the state |001>, the higher order to the lower order corresponds to q2q1q0, and the symbol | > is a dirac. For a quantum wire containing N quantum bits q 0、q1、…、qn、…、qN-1, the order of the binary representation quantum states is q N-1qN-2…、q1q0.
Describing with a single qubit, the logic state ψ of a single qubit may be in an overlap state (uncertain state) of the state |0>, the state |1>, the state |0> and the state |1>, and may be specifically expressed as ψ=a|0 > +b|1>, where a and b are complex numbers representing the amplitude (probability amplitude) of the quantum state, the square of the modulus of the amplitude represents the probability, |a| 2、|b|2 represents the probability that the logic state is the state |0> and the state |1>, respectively, |a| 2+|b|2 =1. In short, a quantum state is an superposition of eigenstates, when the probability of the other states is 0, i.e. in a uniquely defined eigenstate.
Referring to fig. 1, a schematic flow diagram of a quantum-technology-based numerical comparison method provided by an embodiment of the present application includes:
101. obtaining a first numerical value and a second numerical value to be compared, and preparing a first quantum state and a second quantum state by respectively corresponding the first numerical value and the second numerical value;
In this embodiment, the first value and the second value are compared according to a quantum computing technique, the first value is a subtracted number, the second value is a subtracted number, the first value and the second value are subtracted by a quantum circuit, the difference value is compared with 0, if the difference value is greater than 0, the subtracted number is greater than the subtracted number, i.e. the first value is greater than the second value, and if the difference value is less than 0, the subtracted number is less than the subtracted number, i.e. the first value is less than the second value.
Specifically, the first value and the second value are prepared into quantum states, as shown in fig. 4, the first value and the second value are encoded according to an H gate and an RY gate, respectively, so as to obtain the first quantum state and the second quantum state, and the encoding parameters are determined by the first value and the second value. Since RY is a single-qubit rotary gate, the encoding parameter may be set to an angle, and the angle of the RY gate acting on the qubit corresponding to the first value and the second value may be set to a corresponding relationship between the first value and the second value, which is illustrated by the following example:
If the first value is a and the second value is b, the parameters of RY may be:
In addition to the above manner of encoding according to the angle of the deflection gate, the first value and the second value may be prepared into corresponding quantum states according to the manner of amplitude encoding, and the decimal data to be operated may be converted into binary quantum state representation. For example, the subtracted data is 7, the signed binary represents 0111, the most significant bit is 0 representing a positive number, and 1 representing a negative number; the reduction data is 4 and the signed binary representation 0011.
102. Running a preset quantum circuit, wherein the preset quantum circuit is used for carrying out subtraction operation on the first quantum state and the second quantum state;
In this embodiment, the magnitudes of the first value and the second value are compared according to a quantum computing technique, after the first value and the second value are converted into quantum states, subtraction operation is performed on the first quantum state and the second quantum state according to a preset quantum circuit, the preset quantum circuit includes an adder module and a complementary code module, the first quantum state is subtracted and is 7, and the second quantum state is subtracted and is 4 examples:
At least 4-bit qubits a.sign, a2, a1, a0 are obtained, 7 is encoded onto the first quantum state |0111> of a.sign, a2, a1, a0, and the amplitude of the quantum state is set to 1. Wherein, |0111> = |0> |1>, |0>, |1> are sub-quantum states of |0111>, one sub-quantum state corresponds to one quantum bit, from left to right, the highest bit corresponds to a.sign, the second bit corresponds to a2, the third bit corresponds to a1, the lowest bit corresponds to a0, the highest |0> represents a symbol bit sub-quantum state, and the rest represents a numerical bit sub-quantum state. In order to unify the operation dimensions, 4-bit qubits b.sign, b2, b1, b0 are additionally obtained, 4 is encoded into the second quantum state |0100> of b.sign, b2, b1, b0, the amplitudes of which are equal to 1.
103. Measuring preset quantum bits of the preset quantum circuit, and acquiring difference sign bits of the first quantum state and the second quantum state according to a measurement result;
In this embodiment, since the present application aims to compare the magnitude between two numerical values, only the sign bit quantum bit of the difference sign bit is needed to be measured, the difference sign bit is also the sign bit of the first quantum state, only the quantum state of the quantum bit corresponding to the difference sign bit is needed to be measured, taking binary as an example, according to the subtraction rule of computer binary, the preset quantum circuit includes a complement module and an adder module, the preset quantum circuit includes the numerical value bit quantum bit and the sign bit quantum bit corresponding to the subtracted number and the numerical value quantum bit, the numerical value bit quantum bit is used to represent the numerical value of the subtracted number or the subtracted number, the sign bit quantum bit is used to represent the sign of the subtracted number or the subtracted number, the binary is also taken as 100, the sign bit is added in front of the binary, 4 can be represented by 0100, as shown in fig. 8, a.sign is the sign bit of a, only the sign bit after the addition process and the two complementary states are needed to be measured, and the sign after a-b symbol is obtained, and the magnitude relation between a and b is determined according to the magnitude of the sign and b.
104. And determining the magnitude relation between the first numerical value and the second numerical value according to the difference sign bit.
Specifically, the preset quantum circuit is operated, and a target quantum bit including a difference sign bit of the first quantum state and the second quantum state is measured, wherein a binary sign bit of 0 represents that the binary is a positive number, and a binary sign bit of 1 represents that the binary is a negative number. If the value of the difference sign bit is 0, the first value minus the second value is a positive number, and the first value is larger than the second value; and if the value of the difference sign bit is 1, the first value is smaller than the second value if the first value minus the second value is negative.
It can be seen that a first value and a second value to be compared are obtained, the first value and the second value are respectively and correspondingly prepared into a first quantum state and a second quantum state, a preset quantum circuit is operated, the preset quantum circuit is used for carrying out subtraction operation on the first quantum state and the second quantum state, measuring preset quantum bits of the preset quantum circuit, obtaining difference sign bits of the first quantum state and the second quantum state according to a measurement result, and determining the magnitude relation between the first value and the second value according to the difference sign bits. The invention can realize the comparison of the values among integers through the quantum circuit, and fills the blank of the related technology.
Referring to fig. 1 for a further description of a process of obtaining a difference sign bit, referring to fig. 2 specifically, another flow chart of a quantum technology-based numerical comparison method provided by an embodiment of the present application includes:
201. measuring sign bit quantum bits of difference sign bits corresponding to subtraction operation in the preset quantum circuit, and obtaining quantum states of the sign bit quantum bits;
202. And determining the value of the difference sign bit according to the quantum state of the sign bit quantum bit.
In this embodiment, since the present application aims to compare the magnitude between two values, only the sign bit quantum bit of the difference sign bit is needed to be measured, the difference sign bit is the sign bit of the first quantum state, only the quantum state of the quantum bit is needed to be measured, if the value of the difference sign bit is0, it represents that the first value minus the second value is a positive number, and the first value is greater than the second value as described in embodiment 104; and if the value of the difference sign bit is 1, the first value is smaller than the second value if the first value minus the second value is negative.
The following describes the process of performing the quantum subtraction function:
In this embodiment, the greatest difference between the subtractor and the adder described below is that a negative number is generated, so that a binary processing method is adopted to add one sign bit to both the number to be subtracted and the number to be subtracted to represent the positive and negative of the numerical value, and a complementary code is used to perform the operation. The positive number complement is unchanged, and the negative number is added with 1 after being inverted according to the bit except the sign bit. The sign bit is used for controlling whether the complementary code operation is performed or not in the quantum circuit, the inversion can be realized by using an X gate, and the addition of 1 can be realized by using an adder. And after the operation is completed under the condition of the complement, the result is subjected to the complement operation once again, and the target value is obtained. And obtaining a first numerical value and a second numerical value to be operated, and converting the first numerical value (reduced number) and the second numerical value (reduced number) into a first quantum state and a second quantum state respectively. Wherein the quantum state comprises: a sign bit sub-quantum state representing the data sign and a magnitude bit sub-quantum state representing the data magnitude.
Specifically, according to the sign bit sub-quantum state in the first quantum state and the quantum state of the first preset auxiliary bit, controlling the first quantum state to execute quantum state evolution corresponding to the complement code operation, and executing CNOT gate operation on the first sign bit quantum bit and the first preset auxiliary bit corresponding to the sign bit sub-quantum state in the first quantum state, wherein the first sign bit quantum bit is a control bit, and the first preset auxiliary bit is a controlled bit; moreover, the CNOT gate can be replaced by other equivalent existing quantum logic gates or quantum logic gate combinations, which is also reasonable and feasible;
According to the quantum state of the first preset auxiliary bit after the CNOT gate operation is executed, controlling whether the current first quantum state executes quantum state evolution corresponding to the complement code operation or not;
if so, inverting the non-symbol bit quantum state of the current first quantum state, carrying out quantum state evolution corresponding to addition operation on the inverted first quantum state and the quantum state |1> state of a second preset auxiliary bit to obtain an evolved first complement quantum state, otherwise, taking the first quantum state as the first complement quantum state; when the quantum state of the first preset auxiliary bit after the CNOT gate operation is executed can be in a state of |1>, controlling the quantum state evolution corresponding to the complementary code operation to be executed, otherwise, not executing the quantum state evolution;
Performing CNOT gate operation on the current first sign bit quantum bit and the first preset auxiliary bit to restore the quantum state of the current first preset auxiliary bit; the first sign bit quantum bit is a control bit, and the first preset auxiliary bit is a controlled bit.
Illustratively, the first quantum state is assumed to be |0011>. The symbol bit sub-quantum state of the i 0011> is the highest sub-quantum state, i.e., the i 0> state, the value of the bit is 0, the corresponding first symbol bit quantum bit is set to a.sign, the first preset auxiliary bit is the preset quantum bit q1, and the state is initially the i 0> state.
And performing CNOT gate operation on the a.sign and the q1, wherein the a.sign is used as a control bit, the q1 is used as a controlled bit, the quantum state of the a.sign bit is in a state of |0>, and the quantum state |0> of the controlled bit q1 is unchanged after the CNOT gate operation.
Since the quantum state of q1 after the execution of the CNOT gate operation is the |0> state, the quantum state evolution corresponding to the complement operation is not executed on the first quantum state. In principle, when the number to be subtracted is positive, no complementary code is required in the subtraction operation, or the complementary code is itself, and |0011> can be directly used as the first complementary code quantum state.
Finally, the CNOT gate may be performed again on the current a.sign and q1, where the quantum state of the a.sign bit is |0> state, and after the CNOT gate operation, the quantum state |0> of the controlled bit q1 is unchanged to restore q1 to be |0> state, thereby releasing the information stored in the first preset auxiliary bit. The first complement quantum state may contain a value 0011 that is the complement of the subtracted number 0011.
As shown in fig. 5, q 1 is a first preset auxiliary bit for controlling whether to perform a complementary operation, where the first quantum state is a, a.sign is a sign bit sub-quantum state in the first quantum state, the remaining a is a numerical bit sub-quantum state representing the data value, j is a second preset auxiliary bit, the initial state is 0 state, the state is set to 1 state through an X gate before the complementary operation, and t is an auxiliary bit (a third preset auxiliary bit described below) used by an adder, and the initial state is 0 state.
The quantum circuit shown in fig. 5 realizes the quantum circuit for the operation of obtaining the complement to a, firstly, the CNOT gate operation is carried out on the a.sign and the q 1, so that the q 1 temporarily represents the a.sign, the q 1 is used for controlling whether the complement is carried out or not, and after the complement is obtained, the q 1 is restored. Thus, the first quantum state is controlled to execute quantum state evolution corresponding to the complement code calculation, and the first complement code quantum state is obtained.
Specifically, according to the symbol bit sub-quantum state of a, a first preset auxiliary bit q 1 is used to control whether to make the complementary code or not. If a is a negative number, performing a negative number complement operation. The complement of the negative number is that 1 is added after the inversion according to the bit except the sign bit, and when the operation of inverting according to the bit except the sign bit is realized by using a logic gate, only the X gate is needed to be made for all the numerical bits, and 1 is also needed to be added after the inversion, therefore, by adding j and a, the current value of j is set as 1, t is the auxiliary bit of the adder, after adding a and j after inverting the numerical bits, the numerical value after the complement is taken is stored on a, and q 1 is restored for the next use.
For example: when a is a negative number, a.sign is 1, and thus q 1 is also 1, and the operations such as inverting are required, whereas when a is a positive number, a.sign is 0, and thus q 1 is also 0, and thus the complement is not required.
The description above is about whether the first quantum state, i.e., the complement of the subtracted number, needs to be introduced, and in binary subtraction calculation, the complement of the subtracted number needs to be added to the complement of the subtracted number, and the process of the complement of the subtracted number, i.e., the second quantum state, is described below.
Specifically, an X gate operation may be performed on the second sign bit quantum bit corresponding to the sign bit sub-quantum state in the second quantum state, to obtain a sign bit sub-quantum state after the inversion; the X gate can be replaced by other equivalent existing quantum logic gates or quantum logic gate combinations, and the method is reasonable and feasible;
likewise, performing a CNOT gate operation on a current second sign bit qubit and a first preset auxiliary bit, wherein the second sign bit qubit is a control bit and the first preset auxiliary bit is a controlled bit;
According to the current quantum state of the first preset auxiliary bit after the CNOT gate operation is executed, controlling whether the current second quantum state executes quantum state evolution corresponding to the complement code operation or not;
If so, inverting the non-symbol bit quantum state of the current second quantum state, carrying out quantum state evolution corresponding to addition operation on the inverted second quantum state and the quantum state |1> state of a second preset auxiliary bit to obtain an evolved second complement quantum state, otherwise, taking the current second quantum state as the second complement quantum state;
performing CNOT gate operation on the current second sign bit quantum bit and the first preset auxiliary bit to restore the current quantum state of the first preset auxiliary bit; the second sign bit quantum bit is a control bit, and the first preset auxiliary bit is a controlled bit.
Illustratively, the second quantum state is assumed to be |0100>. The symbol bit sub-quantum state of i 0100> is the highest sub-quantum state, i.e., i 0> state, the value of this bit is 0, the corresponding second symbol bit quantum bit is b.sign, and the current third auxiliary bit is restored to i 0> state.
First, an X gate may be performed on b.sign, inverting the corresponding sign bit sub-quantum state |0> to |1>, and the second quantum state to |1100>.
And (3) continuing to execute CNOT gate operation on b.sign and q1, wherein b.sign is used as a control bit, q1 is used as a controlled bit, the quantum state of the current b.sign bit is in a state of |1>, and after the CNOT gate operation, the quantum state |0> of the controlled bit q1 is inverted to be in a state of |1 >.
The quantum state of q1 after the CNOT gate operation is performed is the state |1>, so that the quantum state evolution corresponding to the complementary code operation is performed on the current second quantum state |1100 >. The implementation of the quantum state evolution corresponding to the execution of the complement operation is as follows:
Inverting the non-sign bit quantum state of the current second quantum state |1100>, and executing quantum state evolution corresponding to addition operation on the inverted second quantum state |1011> and the quantum state |1> of the second preset auxiliary bit to obtain an evolved second complement quantum state |1100>.
Wherein the non-sign bit sub-quantum state |100> of |1100> can be inverted by performing an X gate; in order to keep the dimensions consistent, the second preset auxiliary bit j is a preset 4-bit qubit j [3]、j[2]、j[1]、j[0], and the quantum state |1> of the second preset auxiliary bit is actually written as |0001>, both of which are equivalent.
Finally, the CNOT gate may be performed again on the current b.sign and q1, the quantum state of the b.sign bit is the |1> state, and after the CNOT gate operation, the quantum state |1> of the controlled bit q1 is inverted to |0>, thereby restoring q1 to the initial |0> state again, and releasing the storage space of q 1. The second complement quantum state may contain a value 1100 that is the complement of the reduction 1100 after performing an X gate on b.sign.
In this embodiment, the second quantum state b is also the same, the initial state of j is 0 state, the initial X gate is used to set the value of j [0] to 1, and the sign sub-quantum state b.sign in the second quantum state is used to change the subtraction into the addition. As shown in fig. 6, fig. 6 is a schematic quantum circuit diagram of quantum state evolution corresponding to the complementary code operation performed on a and b, and the second complementary code quantum state is obtained by performing the complementary code operation on the second quantum state b according to the same method.
Substituting the first complement quantum state and the second complement quantum state into a quantum circuit of an adder, and executing quantum state evolution corresponding to addition operation, thereby evolving the first complement quantum state into a third quantum state containing the sum of the complement of the subtracted data and the complement of the subtracted data.
It should be noted that, the quantum state evolution corresponding to the execution of the complementary code operation may be the same as that described above, and after the evolution, the quantum state of the first preset auxiliary bit is still restored to |0>, so as to facilitate the subsequent calculation and use.
Further, after the step of controlling the third quantum state to perform the quantum state evolution corresponding to the complement operation to obtain the fourth quantum state after evolution, the quantum state evolution corresponding to the complement operation performed on the current second quantum state may be further controlled according to the sign bit sub-quantum state in the current second quantum state and the quantum state of the current first preset auxiliary bit, and the sign bit inversion corresponding to the sign bit sub-quantum state in the current second quantum state may be performed to restore the current second quantum state. And after addition operation, further executing quantum state evolution corresponding to complement operation on a third quantum state of the sum of the complement of the subtracted data and the complement of the subtracted data. As shown in fig. 7, after the processing of making the complementary codes by a and b is completed, adding the complementary codes of a and b, after the addition result is obtained on a, making a complementary code solving operation on a, and evolving a into a final subtraction result; b is restored by carrying out complement on b once and inverting the sign bit of b through an X gate; the first preset auxiliary bit q1 is restored through the last CNOT gate, j [0] is reversely restored to be in an initial 0 state through the X gate, so that a simple quantum circuit diagram of the whole subtracter shown in fig. 8 is obtained from fig. 6 and 7, a is a quantum bit representing the number to be reduced by taking fig. 8 as an example, a.sign is a sign bit of a, n quantum bits are shared by a.sign and a, and the number to be reduced in the signed state is represented jointly; b is a quantum bit representing the number reduction, b.sign is a sign bit of b, b.sign and b share n quantum bits, the sign and b together represent the number to be reduced in signed state, j and j [0] share n quantum bits, q1 is an auxiliary bit for controlling whether to complement or not, t is an auxiliary bit in the adder, and the auxiliary bit is a generic term for quantum bits for assisting in realizing quantum circuit function.
From the above, the complements of the first value (corresponding to the first quantum state) and the second value (corresponding to the second quantum state) can be obtained, and according to the binary algorithm, the difference value of the first value minus the second value can be obtained by adding and restoring the two complements.
Referring to fig. 2, a process of adding a first quantum state complement to a second quantum state complement is further described, and referring specifically to fig. 3, another flow chart of a quantum technology-based numerical comparison method provided by an embodiment of the present application includes:
301. Determining the number of target modules of a front cascade module MAJ module to be cascaded and a rear cascade module UMA module to be cascaded according to the number of quantum bits corresponding to the first quantum state and the second quantum state, wherein the number of the modules of the MAJ module is the same as the number of the modules of the UMA module;
From the foregoing, the two quantum states to be operated on may be: a first complement quantum state and a second complement quantum state; and taking the inverted first quantum state and the quantum state |1> state of the second preset auxiliary bit.
For example, as shown in fig. 9, the first qubit in the line is the third preset auxiliary bit, and is initially in the state of |0>, and finally returns to the state of |0>, where e and f are the qustates corresponding to the data to be added, and each of the qubits corresponds to a group of qubits. c represents the final carry term, corresponding to the preset carry auxiliary bit, s is the output bit not containing carry. It is generally required that the number of qubits corresponding to e and f be the same, and the number of bits s and e, f be the same.
Illustratively, as shown in fig. 9, e [i] and f [i] are respectively the ith bit of the two addend-corresponding quantum states, and c [i] is the upper level carry.
s[i]＝e[i]XOR f[i]XOR c[i]，
c[i+1]＝(e[i]AND f[i])XOR(e[i]AND f[i])XOR(e[i]AND f[i])，
The first quantum bit is a third preset auxiliary bit, corresponding to c 0 in the quantum circuit. The first MAJ module comprises three input quantum states and three corresponding output quantum states, wherein the three input quantum states are respectively c 0、e0、f0,e0 which is the 0 th quantum state of the first quantum state to be operated, f 0 is the 0 th quantum state of the second quantum state to be operated, c 0 is the quantum state of the third preset auxiliary bit, and the initial value is 0, namely no carry. The three output quantum states are respectivelyC 1,c1 is the carry after the addition of e 0 and f 0, and similarly, the three input quantum states of the next MAJ module are c 1、e1、f1, and the three output quantum states are/>, respectivelyC 2, and so on to the last MAJ module.
For the first UMA module, the first UMA module includes three input quantum states and three corresponding output quantum states, wherein the three output quantum states of the MAJ module are three input quantum states of the corresponding UMA module, and the three output quantum states are the results of c 0、s0、e0,s0 being e 0 and f 0 added and do not contain carry. Similarly, s1 is the carry-free result of the addition of e 1 and f 1, and similarly, c4 is the final carry term. In practical application, the quantum bit corresponding to c4 may not be set in the quantum circuit under the condition that the final carry is not calculated.
And the number of the modules of the MAJ module and the number of UMA modules can be determined according to the number of sub-quantum states contained in any quantum state to be operated, wherein one sub-quantum state corresponds to one quantum bit, and the number of the modules of the MAJ module and the number of the UMA modules are equal. The example shown in fig. 10 only shows that 4-bit qubits are needed to encode each of e and f, and the numbers of MAJ modules and UMA modules are 4. The MAJ module and the UMA module form a front and rear cascade unit of the adder. The MAJ module may be used to extract the carry term of any one step and pass on to the next stage, thereby calculating the final carry term. On the one hand, the UMA module extracts information of c and transmits the information to the UMA of the previous stage, s (result item) of each stage is calculated, and e information is recovered.
Exemplary: when 4 (the quantum state corresponding to the 3 qubits is denoted as 100) +2 (the quantum state corresponding to the 3 qubits is denoted as 010) =6 (the quantum state corresponding to the 3 qubits is denoted as 110). At this time, the number of the qubits of the encoding operation result is consistent with the number of the qubits of the encoding e or the number of the qubits used for encoding f, and the number of the modules of the MAJ module and the number of the UMA modules are 3.
Exemplary: when 4 (the quantum state corresponding to the 3 qubits is represented as 100) +7 (the quantum state corresponding to the 3 qubits is represented as 111) =11 (the quantum state corresponding to the 3 qubits is represented as 011), but it is understood that the binary number corresponding to 11 is 1011 and the bit where the leftmost 1 is located is a carry term, which can be represented by an auxiliary bit. At this time, the number of the qubits of the encoding operation result and the number of the qubits of the encoding e or the number of the qubits of the encoding f is large, and the number of the modules of the MAJ module and the number of the UMA modules are 3.
For example, when 2 (the quantum state corresponding to the encoding at 2 qubits is denoted as 10) +4 (the quantum state corresponding to the encoding at 3 qubits is denoted as 100) =6 (the quantum state corresponding to the encoding at 3 qubits is denoted as 110). At this time, the numerical term "3" of the numerical value of the code "6" is consistent with the number of quantum states of the quantum bit of the code b, and the number of modules of the MAJ module and the number of UMA modules are both 3.
302. And cascading the MAJ modules and UMA modules with the number of the target modules to generate adder sub-quantum circuits corresponding to the adder modules.
The MAJ cascade module and the UMA module respectively comprise three input items and three output items, and the three output items of one MAJ cascade module can be used as the three input items of one corresponding UMA cascade module according to an addition instruction so as to cascade the MAJ cascade module and the corresponding UMA cascade module to generate a target quantum circuit corresponding to the adder, wherein the MAJ cascade module is determined by cascading among the MAJ modules of the target module number, and the UMA cascade module is determined by cascading among the UMA modules of the target module number.
Specifically, the three input items of the MAJ module comprise one carry input item and two sub-quantum state input items to be calculated, the three output items of the MAJ module comprise one carry output item and two intermediate result output items, the three input items of the UMA module comprise one carry output item and two intermediate result output items of the corresponding MAJ module, the three output items of the UMA module comprise one result carry output item, an accumulation and output item and one sub-quantum state input item to be calculated,
Then, according to the addition instruction, the carry output item output by the last MAJ module and the two sub-quantum state input items to be calculated are used as three input items of the next MAJ module, so that MAJ modules with the number of the target modules are cascaded;
Taking two intermediate result output items of one MAJ module as two input items of a corresponding UMA module, acquiring a last UMA module of the corresponding UMA module, taking a result carry output item of the last UMA module as one input item of the corresponding UMA module, and cascading the MAJ modules with the target modules and UAM modules with the target modules to generate the initial quantum circuit; the carry output item of the last MAJ module is used as an input item of the corresponding first UMA module;
Adding a CNOT quantum logic gate between the last MAJ module and the corresponding first UMA module in the initial quantum circuit, wherein a quantum bit corresponding to a carry output item of the MAJ module is used as a control bit, and a preset carry auxiliary bit is used as a controlled bit, so as to generate a target quantum circuit of the adder. In the case that the carry term is not required, the CNOT gate and the carry auxiliary bit may not be set.
In this embodiment, the MAJ module and the UMA module form a front and rear cascade unit of the adder. As shown in fig. 11, the MAJ module is configured to extract the carry term after each stage of addition operation and transfer the carry term to the next stage, thereby calculating the final carry term. As shown in fig. 12, the MAJ module may mainly consist of three logic gates, two CNOT gates and one Toffoli gate. The role of the CNOT gate (first, second logic gate from left to right in FIG. 12) is: the control bit is added to the target bit to form a modulo-2 addition, i.e. an exclusive-or operation, resulting in (e i+ci)％2、(ei+fi)% 2, the order of the two CNOT gates being swappable. The function of the Toffoli gate (third logic gate from left to right in fig. 12) is: both control bits are added to the target bit to obtain the carry term c [i+1]＝(e[i]AND f[i])XOR(e[i]AND f[i])XOR(e[i]AND f[i]). I.e. by the first CNOT gate from left to right in FIG. 12By the second CNOT gate from left to right in FIG. 14C i+1 is implemented by the third TOFFOLI gate from left to right in fig. 12, whereby the front-stage cascade of quantum adders is formed by 2 CNOT gates and 1 TOFFOLI gate.
As shown in fig. 13, the UMA module is used in the later stage of the cascade adder, the implementation manner of the UMA module is similar to that of the MAJ module, as shown in fig. 14, c i+1 is reduced to e i by using a Toffoli gate (the first logic gate from left to right in fig. 14), (e+c)% 2 is reduced once by using a CNOT gate (the second logic gate from left to right in fig. 14) by using e i, (e i+ci)% 2 is reduced to c i, and finally, c i is used to make a CNOT gate (the third logic gate from left to right in fig. 14) by using c i to (e i+fi)% 2), so as to obtain the final result s [i]＝e[i]XOR f[i]XOR c[i] of the current bit.
Example 1: (e i+ci)% 2 is 0, (e i+fi)% 2 is 0, and c i+1 is 1.
Starting to add (e i+ci)% 2 and (e i+fi)% 2 to c i+1, the value of c i+1 becomes 1, the meaning indicated becomes e i, then e i to (e i+ci)% 2, (e i+ci)% 2 becomes 1, the meaning indicated becomes c i, then c i to (e i+fi)% 2, (e i+fi)% 2 becomes 1, and the meaning indicated becomes s i.
Example 2: (e i+ci)% 2 is 1, (e i+fi)% 2 is 1, and c i+1 is 1.
Starting to add (e i+ci)% 2 and (e i+fi)% 2 to c i+1, the value of c i+1 becomes 0, the meaning becomes e i, then e i to (e i+ci)% 2, (e i+ci)% 2 becomes 1, the meaning becomes c i, then c i to (e i+fi)% 2, (e i+fi)% 2 becomes 0, and the meaning becomes s i.
The last CNOT gate from top to bottom in FIG. 10, i.e., the CNOT gate in the middle of the whole adder MAJ module and UMA module, is used to save the result of c i+1.
In this embodiment, two quantum states to be operated, such as |111> and |111>, are input into a quantum subtraction circuit, i.e., a preset quantum circuit, so as to obtain a corresponding binary sign bit representing a quantum state comparison result.
It can be seen that a first value and a second value to be compared are obtained, the first value and the second value are respectively and correspondingly prepared into a first quantum state and a second quantum state, a preset quantum circuit is operated, the preset quantum circuit is used for carrying out subtraction operation on the first quantum state and the second quantum state, measuring preset quantum bits of the preset quantum circuit, obtaining difference sign bits of the first quantum state and the second quantum state according to a measurement result, and determining the magnitude relation between the first value and the second value according to the difference sign bits. The invention can realize the comparison of the values among integers through the quantum circuit, and fills the blank of the related technology.
The foregoing describes the present invention from a method perspective, and the following further describes the present invention from a device perspective, with particular reference to fig. 15, including:
an obtaining unit 1501, configured to obtain a first value and a second value to be compared, and prepare the first value and the second value into a first quantum state and a second quantum state respectively;
An operation unit 1502, configured to operate a preset quantum circuit, where the preset quantum circuit is configured to perform subtraction operation on the first quantum state and the second quantum state;
the measurement unit 1503 is configured to measure an operation result of the quantum circuit, and obtain a difference value between the first quantum state and the second quantum state according to the operation result;
a determining unit 1504 is configured to determine a magnitude relation between the first value and the second value according to the difference value.
It may be seen that, the obtaining unit 1501 is configured to obtain a first value and a second value to be compared, respectively prepare the first value and the second value into a first quantum state and a second quantum state, the operation unit 1502 is configured to operate a preset quantum circuit, the preset quantum circuit is configured to perform subtraction operation on the first quantum state and the second quantum state, the measurement unit 1503 is configured to measure an operation result of the quantum circuit, obtain a difference value between the first quantum state and the second quantum state according to the operation result, and the determining unit 1504 is configured to determine a magnitude relation between the first value and the second value according to the difference value, so that comparison between values between integers can be implemented through the quantum circuit.
The following describes the operation of the computer terminal in detail by taking it as an example. Fig. 16 is a hardware block diagram of a computer terminal according to a numerical comparison method based on quantum technology according to an embodiment of the present invention. As shown in fig. 16, the computer terminal may include one or more (only one is shown in fig. 16) processors 1601 (the processor 1601 may include, but is not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 1602 for storing data, and optionally, a transmission device 1603 for communication functions and an input-output device 1604. It will be appreciated by those skilled in the art that the configuration shown in fig. 16 is merely illustrative and is not intended to limit the configuration of the computer terminal described above. For example, the computer terminal may also include more or fewer components than shown in fig. 16, or have a different configuration than shown in fig. 16.
The memory 1602 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the quantum-based numerical comparison method in the embodiments of the present application, and the processor 1601 executes the software programs and modules stored in the memory 1602 to perform various functional applications and data processing, i.e., to implement the above-described method. Memory 1602 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 1602 may further include memory located remotely from the processor 1601, which may be connected to a computer terminal by a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 1603 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 1603 includes a network adapter (Network Interface Controller, NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 1603 may be a Radio Frequency (RF) module for communicating with the internet wirelessly. The embodiment of the application also provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program for electronic data exchange, and the computer program causes a computer to execute part or all of the steps of any one of the above method embodiments, and the computer includes an electronic device.
Embodiments of the present application also provide a computer program product comprising a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform part or all of the steps of any one of the methods described in the method embodiments above. The computer program product may be a software installation package, said computer comprising an electronic device.
The embodiment of the application also provides a quantum computer, which comprises a quantum computer operating system, wherein the quantum computer operating system realizes the numerical comparison processing based on the quantum technology according to part or all of the steps of any one of the methods described in the embodiment of the method.
It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present application is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, such as the above-described division of units, merely a division of logic functions, and there may be additional manners of dividing in actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, or may be in electrical or other forms.
The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units described above, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a memory, comprising several instructions for causing a computer device (which may be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the above-mentioned method of the various embodiments of the present application. And the aforementioned memory includes: a usb disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Those of ordinary skill in the art will appreciate that all or a portion of the steps in the various methods of the above embodiments may be implemented by a program that instructs associated hardware, and the program may be stored in a computer readable memory, which may include: flash disk, read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk.
The foregoing has outlined rather broadly the more detailed description of embodiments of the application, wherein the principles and embodiments of the application are explained in detail using specific examples, the above examples being provided solely to facilitate the understanding of the method and core concepts of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims (8)

1. A quantum technology-based numerical comparison method, comprising:
obtaining a first numerical value and a second numerical value to be compared, and preparing a first quantum state and a second quantum state by respectively corresponding the first numerical value and the second numerical value;
Running a preset quantum circuit, wherein the preset quantum circuit is used for carrying out subtraction operation on the first quantum state and the second quantum state; the preset quantum circuit comprises: the adder module and the complementary code module comprises the adder module; wherein the adder module is constructed in the following manner: determining the number of target modules of a front cascade module MAJ module to be cascaded and a rear cascade module UMA module to be cascaded according to the number of quantum bits corresponding to the first quantum state and the second quantum state, wherein the number of the modules of the MAJ module is the same as the number of the modules of the UMA module; cascading the MAJ modules and UMA modules with the number of the target modules to generate adder sub-quantum circuits corresponding to the adder modules; the MAJ module and the UMA module are constructed according to a CNOT gate and a TOFFOLI gate, and the CNOT gate and the TOFFOLI gate are one of quantum logic gates;
Measuring preset quantum bits of the preset quantum circuit, and acquiring difference sign bits of the first quantum state and the second quantum state according to a measurement result;
and determining the magnitude relation between the first numerical value and the second numerical value according to the difference sign bit.
2. The method of claim 1, wherein the preparing the first and second values into first and second quantum states, respectively, comprises:
And respectively encoding the first numerical value and the second numerical value according to an H gate and a RY gate to obtain the first quantum state and the second quantum state, wherein the encoding parameters are determined by the first numerical value and the second numerical value, and the H gate and the RY gate are one type of quantum logic gate.
3. The method of claim 1, wherein the obtaining the sign bit of the difference between the first quantum state and the second quantum state from the measurement result comprises:
measuring sign bit quantum bits of difference sign bits corresponding to subtraction operation in the preset quantum circuit, and obtaining quantum states of the sign bit quantum bits;
And determining the value of the difference sign bit according to the quantum state of the sign bit quantum bit.
4. The method of claim 3, wherein said obtaining a magnitude relationship between said first value and said second value from said difference sign bit comprises:
If the value of the difference sign bit is 0, the first value is smaller than the second value;
and if the value of the difference sign bit is 1, the first value is larger than the second value.
5. A quantum-based numerical comparison device, comprising:
The device comprises an acquisition unit, a comparison unit and a comparison unit, wherein the acquisition unit is used for acquiring a first numerical value and a second numerical value to be compared, and preparing the first numerical value and the second numerical value into a first quantum state and a second quantum state respectively;
The operation unit is used for operating a preset quantum circuit, and the preset quantum circuit is used for carrying out subtraction operation on the first quantum state and the second quantum state; the preset quantum circuit comprises: the adder module and the complementary code module comprises the adder module; wherein the adder module is constructed in the following manner: determining the number of target modules of a front cascade module MAJ module to be cascaded and a rear cascade module UMA module to be cascaded according to the number of quantum bits corresponding to the first quantum state and the second quantum state, wherein the number of the modules of the MAJ module is the same as the number of the modules of the UMA module; cascading the MAJ modules and UMA modules with the number of the target modules to generate adder sub-quantum circuits corresponding to the adder modules; the MAJ module and the UMA module are constructed according to a CNOT gate and a TOFFOLI gate, and the CNOT gate and the TOFFOLI gate are one of quantum logic gates;
The measuring unit is used for measuring the operation result of the quantum circuit and acquiring the difference value between the first quantum state and the second quantum state according to the operation result;
And the determining unit is used for determining the magnitude relation between the first numerical value and the second numerical value according to the difference value.
6. An electronic device comprising a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing the steps in the method of any of claims 1-4.
7. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program, which is executed by a processor to implement the method of any of claims 1-4.
8. A quantum computer comprising a quantum computer operating system implementing a quantum technology based numerical comparison process according to the method of any one of claims 1-4.
CN202111163459.XA 2021-09-30 2021-09-30 Quantum technology-based numerical comparison method and device and quantum computer Active CN115936127B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111163459.XA CN115936127B (en) 2021-09-30 2021-09-30 Quantum technology-based numerical comparison method and device and quantum computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111163459.XA CN115936127B (en) 2021-09-30 2021-09-30 Quantum technology-based numerical comparison method and device and quantum computer

Publications (2)

Publication Number Publication Date
CN115936127A CN115936127A (en) 2023-04-07
CN115936127B true CN115936127B (en) 2024-06-14

Family

ID=86653007

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111163459.XA Active CN115936127B (en) 2021-09-30 2021-09-30 Quantum technology-based numerical comparison method and device and quantum computer

Country Status (1)

Country Link
CN (1) CN115936127B (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108984849A (en) * 2018-06-21 2018-12-11 广西师范大学 A kind of quantum comparison device design method based on quantum superposition state

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5204698B2 (en) * 2009-03-19 2013-06-05 日本電信電話株式会社 Quantum operation method, quantum operation device, quantum circuit
CN110493000B (en) * 2019-09-02 2021-11-16 福建师范大学 Multi-party quantum secret comparison method and system based on single particles
CN111310928B (en) * 2020-02-28 2024-03-05 东南大学 Method for realizing universal quantum comparison circuit
CN111598249B (en) * 2020-05-19 2021-09-07 北京百度网讯科技有限公司 Method, apparatus, classical computer and storage medium for determining approximate quantum gate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108984849A (en) * 2018-06-21 2018-12-11 广西师范大学 A kind of quantum comparison device design method based on quantum superposition state

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
基于Toffoli门的可逆数值比较器的设计与优化;李明翠;;华东交通大学学报;20111215(06);全文 *

Also Published As

Publication number Publication date
CN115936127A (en) 2023-04-07

Similar Documents

Publication Publication Date Title
CN112162723B (en) Quantum subtraction operation method, device, electronic device and storage medium
CN112114776B (en) Quantum multiplication method, device, electronic device and storage medium
CN111563599B (en) Quantum circuit decomposition method and device, storage medium and electronic device
CN113222155B (en) Quantum circuit construction method and device, electronic device and storage medium
CN112633508A (en) Quantum line generation method and device, storage medium and electronic device
CN112214200B (en) Quantum subtraction operation method, device, electronic device and storage medium
CN112162724B (en) Quantum division operation method and device with precision
CN115809707B (en) Quantum comparison operation method, device, electronic device and basic arithmetic component
CN115936127B (en) Quantum technology-based numerical comparison method and device and quantum computer
CN116048458B (en) Quantum computation-based numerical dividing method, device, equipment and storage medium
CN116049506B (en) Quantum calculation-based numerical value searching method, device, equipment and storage medium
CN115809042B (en) Quantum modulus addition operation method and device, electronic device and modulus arithmetic component
CN112162725B (en) Quantum division operation method, quantum division operation device, electronic device and storage medium
CN115809706B (en) Quantum modulus multiplication operation method and device, electronic device and modulus arithmetic component
CN115879555B (en) Quantum modulus rapid multiplication operation method, device and modulus arithmetic component
CN115879554B (en) Quantum modulus square operation method and device, electronic device and modulus arithmetic component
CN115907016B (en) Quantum-based method for calculating search target range value and related device
CN115713122B (en) Method and device for determining size relation between quantum data and classical data
CN116402149B (en) Quantum circuit optimization method and device, storage medium and electronic device
CN115879552B (en) Quantum modulus multiplication inverse operation method and device, electronic device and modulus arithmetic component
CN115879557B (en) Quantum circuit-based data size comparison method and device and quantum computer
CN115879558B (en) Method and device for comparing sizes of multiple quantum states
CN115879553B (en) Quantum modulus complete multiplication method and device and modulus arithmetic component
CN117744817A (en) Quantum Fourier transform-based constant modulus adder, method and related device
CN115879556A (en) Quantum modulus operation method, device, medium and modulus arithmetic component

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information
CB02 Change of applicant information

Address after: 230088 6th floor, E2 building, phase II, innovation industrial park, 2800 innovation Avenue, Hefei high tech Zone, Hefei City, Anhui Province

Applicant after: Benyuan Quantum Computing Technology (Hefei) Co.,Ltd.

Address before: 230088 6th floor, E2 building, phase II, innovation industrial park, 2800 innovation Avenue, Hefei high tech Zone, Hefei City, Anhui Province

Applicant before: ORIGIN QUANTUM COMPUTING COMPANY, LIMITED, HEFEI

GR01 Patent grant
GR01 Patent grant