CN115934617A - Serial data recovery method and device - Google Patents
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Abstract
The invention discloses a serial data recovery method and a device of an image sensor, wherein the method comprises the following steps: when the image sensor is in an idle state, oversampling serial data from the image sensor by using a high-speed clock; calculating the single-bit clock period number and the two-bit clock period number of the serial data according to the oversampling result; acquiring the current clock period number of data retention between adjacent rising edges and falling edges of serial data when the image sensor is in a working state; comparing the current clock period number with the single-bit clock period number or two-bit clock period number, and performing serial data recovery according to the comparison result; and decoding the recovered data according to the coding rule of the serial data sending end to obtain image data. The method can adaptively match the data rate of the transmitting end, and can recover the serial data without a special clock recovery circuit, thereby reducing the development cost.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a serial data recovery method and a serial data recovery device.
Background
At present, in a conventional asynchronous serial data transmission method, such as UART (universal asynchronous receiver transmitter), during data transmission, a transmitting end and a receiving end of data must be configured with the same baud rate in advance, and in general, transmission rates are relatively low, and a typical UART communication rate is 115.2Kbps.
The prior serial communication data recovery method applied to the field of data communication detects data jumping edges at a data receiving end, uses 4 times of oversampling, and finally judges whether the received data is '1' or '0' by comparing the times of the sampled '1' and '0', although the method can solve the problem of serial data recovery of the traditional UART, the receiving end must keep the same baud rate as the transmitting end when receiving the data, and because the baud rate of some miniature image sensors in the market is not fixed, and the transmission rate of the miniature image sensors is far greater than the transmission rate of the common UART, such as 100Mbps, the prior data recovery method is not suitable for the application scene.
Therefore, it is desirable to provide a serial data recovery method to improve the above problems.
Disclosure of Invention
The embodiment of the invention provides a serial data recovery method and a serial data recovery device, which are used for providing a data recovery method for adaptively matching the data rate of a sending end.
In a first aspect, the present invention provides a serial data recovery method, comprising: when the image sensor is in an idle state, oversampling serial data from the image sensor by using a high-speed clock; calculating the single-bit clock period number and the two-bit clock period number of the serial data according to the oversampling result; acquiring the current clock period number of data retention between adjacent rising edges and falling edges of serial data when the image sensor is in a working state; comparing the current clock period number with the single-bit clock period number or the two-bit clock period number, and performing serial data recovery according to the comparison result; and decoding the recovered data according to the coding rule of the serial data sending end to obtain image data. Optionally, the clock rate of the high-speed clock is k times the serial data transmission rate of the image sensor, and k is a positive integer.
The serial data recovery method provided by the invention has the beneficial effects that: because the serial data from the image sensor can be oversampled according to the high-speed clock, and the approximate data transmission rate is calculated according to the oversampling result, the data receiving end does not need to know the transmission rate of the transmitting end in advance, can be adaptively matched with the data rate of the transmitting end, and can recover the serial data without a special clock recovery circuit, thereby reducing the development cost.
In one possible embodiment, the oversampling the serial data from the image sensor with the high-speed clock includes:
detecting the jump of the serial data rising edge and the falling edge of the miniature image sensor in real time;
when the serial data rising edge jump is detected, starting a high-level counter, and acquiring the clock period number of data keeping high level between adjacent rising edges and falling edges by using the high-level counter;
when the serial data falling edge jump is detected, starting a low level counter, and acquiring the clock period number of data keeping low level between adjacent falling edges and rising edges by using the low level counter;
calculating the single-bit clock period number and the two-bit clock period number of the serial data according to the oversampling result, comprising:
and determining the single-bit clock period number and the two-bit clock period number of the serial data according to the counting result of the high-level counter and the counting result of the low-level counter.
In another possible embodiment, determining the number of the one-bit clock cycles and the number of the two-bit clock cycles of the serial data according to the count result of the high-level counter and the count result of the low-level counter includes:
averaging the counting results of the high-level counters acquired for multiple times to obtain a first average value, and averaging the counting results of the low-level counters acquired for multiple times to obtain a second average value; determining a maximum number of single-bit clock cycles according to a larger one of the first and second averages and a minimum number of single-bit clock cycles according to a smaller one of the first and second averages; the maximum number of two-bit clock cycles is determined from the maximum number of single-bit cycles, and the minimum number of two-bit clock cycles is determined from the minimum number of single-bit cycles.
In other possible embodiments, comparing the current number of clock cycles with the number of single-bit clock cycles or two-bit clock cycles, and serial data recovery according to the comparison result includes:
when the current clock period number is the counting result of the low-level counter and falls into a value interval consisting of the minimum single-bit clock period number and the maximum single-bit clock period number, determining that the received data is bit 0; when the current clock period number is the counting result of the high-level counter and falls into a value interval consisting of the minimum single-bit clock period number and the maximum single-bit clock period number, determining that the received data is bit 1; when the current clock period number is the counting result of the low-level counter and falls into a value interval consisting of the minimum two-bit clock period number and the maximum two-bit clock period number, determining that the received data is bit 00; and when the current clock period number is the counting result of the high-level counter and falls into a value interval consisting of the minimum two-bit clock period number and the maximum two-bit clock period number, determining that the received data is a bit 11.
In other possible embodiments, after obtaining the image data, the method further includes: and analyzing the image data according to a frame format to obtain frame synchronization, line synchronization and line data.
In a second aspect, the present invention also provides a serial data recovery apparatus for an image sensor, the apparatus comprising means for performing the method of any one of the possible designs of the first aspect. These modules/units may be implemented by hardware or by hardware executing corresponding software.
As for the advantageous effects of the above second aspect, reference may be made to the description of the above first aspect.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings may be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of an embodiment of a micro image sensor for encoding output data;
FIG. 2 is a diagram illustrating an image sensor outputting serial data during an IDLE (IDLE) period according to an embodiment of the present invention;
FIG. 3 is a flow chart illustrating a serial data recovery method according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a serial data transmission system according to an embodiment of the present invention;
fig. 5 is a schematic diagram illustrating decoding of output data of a micro image sensor according to an embodiment of the present invention.
Detailed Description
In order to make the contents of the present invention more comprehensible, the present invention is further described below with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to a person skilled in the art are also covered within the scope of the invention.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
At present, in order to reduce the pins of a chip and improve the data transmission rate of a micro image sensor, the following coding mode is adopted: "bit10" represents data "0", and "bit01" represents data "1", the micro image sensor always outputs "bit10" continuously in the idle state, fig. 1 is an example of the micro image sensor outputting serial data, the original serial data output by the micro image sensor is 1011001011101000011, and the data output (data output) after being encoded according to the above encoding method is: 01100101101001100101011001101010100101, it can be seen from the encoded data output (data output) in fig. 1 that there are no consecutive 3 "0" s or "1" s, and no consecutive 3 or more "0" s or "1" s, in the data output at the output of the image sensor.
In addition, fig. 2 shows an example of serial data output by the image sensor in an IDLE (IDLE) stage, and original serial data output by the micro image sensor in the IDLE stage is 0101010101. As can be seen from fig. 2, the image sensor alternately outputs 0 and 1 in the IDLE stage data.
Specifically, as shown in fig. 3, the serial data recovery method provided by the present invention may specifically include the following steps:
s301, when the image sensor is in an idle state, oversampling serial data from the image sensor with a high-speed clock.
The clock rate of the high-speed clock is k times of the serial data transmission rate of the image sensor, and k is a positive integer.
And S302, calculating the single-bit clock period number and the two-bit clock period number of the serial data according to the oversampling result.
Optionally, the embodiment detects the jump of the serial data rising edge and falling edge of the micro image sensor in real time; when the serial data rising edge jump is detected, starting a high-level counter, and acquiring the clock period number of data keeping high level between adjacent rising edges and falling edges by using the high-level counter; when the serial data falling edge jump is detected, a low level counter is started, and the low level counter is used for acquiring the clock period number of the data keeping low level between the adjacent falling edge and rising edge. The number of single-bit clock cycles and the number of two-bit clock cycles of the serial data may then be determined based on the count result of the high-level counter and the count result of the low-level counter.
And S303, acquiring the current clock period number of data retention between adjacent rising edges and adjacent falling edges of the serial data when the image sensor is in a working state.
S304, comparing the current clock period number with the single bit clock period number or two bit clock period numbers, and performing serial data recovery according to the comparison result.
S305, decoding the recovered data according to the coding rule of the serial data sending end to obtain image data.
In the above S302, determining a single-bit clock cycle number and a two-bit clock cycle number of the serial data according to the counting result of the high-level counter and the counting result of the low-level counter, specifically including averaging the counting results of the high-level counters acquired multiple times to obtain a first average value, and averaging the counting results of the low-level counters acquired multiple times to obtain a second average value; determining a maximum number of single-bit clock cycles according to a larger one of the first and second averages and a minimum number of single-bit clock cycles according to a smaller one of the first and second averages; a maximum two bit clock cycle number is determined based on the maximum single bit cycle number and a minimum two bit clock cycle number is determined based on the minimum single bit cycle number.
In one possible embodiment, in S304, comparing the current number of clock cycles with the number of single-bit clock cycles or two-bit clock cycles, and performing serial data recovery according to the comparison result includes: when the current clock period number is the counting result of the low-level counter and falls into a value interval consisting of the minimum single-bit clock period number and the maximum single-bit clock period number, determining that the received data is bit 0; when the current clock period number is the counting result of the high-level counter and falls into a value interval consisting of the minimum single-bit clock period number and the maximum single-bit clock period number, determining that the received data is bit 1;
when the current clock period number is the counting result of the low-level counter and falls into a value interval consisting of the minimum two-bit clock period number and the maximum two-bit clock period number, determining that the received data is bit 00; and when the current clock period number is the counting result of the high-level counter and falls into a value interval consisting of the minimum two-bit clock period number and the maximum two-bit clock period number, determining that the received data is bit 11.
For example, assuming that the serial data rate of the image sensor is v, the present embodiment may oversample the serial data of the image sensor with a clock signal having a rate k × v, and k is a positive integer, such as oversampling the serial data of the image sensor with a clock signal having a rate of 5 v. The edge detector can detect the rising edge and the falling edge of serial data of the image sensor; starting a high-level counter Ch after the rising edge jump of the serial data is detected, wherein the counter Ch records the clock period number of data keeping high level between the adjacent rising edge and the adjacent falling edge; when a serial data falling edge transition is detected, a low level counter Cl is started, which records the number of clock cycles for which data is held low between adjacent falling and rising edges. Specifically, as shown in fig. 4, in the serial data transmission system, a data sending end sends serial data to a data receiving end according to a certain baud rate, and a data receiving end obtains a sampling sequence according to a set sampling frequency, and meanwhile, the data receiving end monitors the edge jump condition of the serial data in real time, starts a high level counter Ch when detecting a rising edge jump, and starts a low level counter Cl when detecting a falling edge jump of the serial data. Referring to fig. 2, when the image sensor is in IDLE stage, the data receiving end first uses the countPerforming approximate calculation on serial transmission data rate on counting results of the Ch and the Cl, averaging the results of the Ch and Cl counters acquired for multiple times, and selecting a larger average value theta 1 from the obtained first average value and the second average value as the maximum Tb cycle number Tb of 1bit 0 or 1 in serial data transmission max Similarly, the smaller mean θ 2 is chosen as the minimum number of periods Tb of transmission 1bit's 0 ' or ' 1 min . For example, assuming that the clock frequency of the clock signal is 100Mbps, the maximum number of cycles Tb of the image sensor shown in FIG. 2 max Equal to 6, minimum number of cycles Tb min Equal to 5, the serial transmission data rate of the image sensor shown in fig. 2 is equal to 100 Mbps/(6+5) ≈ 9Mbps.
Optionally, in order to increase the receiving redundancy capability of the data receiving end, in this embodiment, the offset S may be increased on the basis of obtaining the larger mean value θ 1 and the smaller mean value θ 2 by calculation, and θ 1+S is used as the maximum 1-bit periodicity Tb max Taking theta 2-S as the minimum cycle number Tb of 1bit min I.e. Tb max Adjusted to be theta 1S, tb min Maximum number of cycles Tb adjusted to theta 2-S, successive 2bit ' 0 ' or ' 1 max A minimum number of cycles Tb min Adjusted to 2 θ 1+S and 2 θ 2-S, respectively, where S is greater than 0 and less than 2. Assuming that S is 1 and the data received by the data receiving end is as shown in fig. 2, the maximum number of cycles Tb of 1bit calculated by the data receiving end is Tb max A minimum number of cycles Tb min Maximum number of cycles Tb 6+1=7 and 5-1=4, respectively, consecutive 2bit ' 0 ' or ' 1 max A minimum number of cycles Tb min 2 × 6+1=13 and 2 × 5-1=9, respectively.
Since the image sensor does not continuously output 3 identical bits (bit) in the data output stage, it is determined whether the received data is "0", "1", "00", or "11" in the data transmission stage by comparing whether Ch and Cl values fall within the range of values ([ θ 2-S, θ 1+S ], [2 θ 2-S,2 θ 1+S ]).
Further, after the approximate calculation of the serial transmission data rate is completed, the data receiving end enters a serial data receiving state; the edge detector detects the jump of the serial data rising edge and falling edge of the miniature image sensor in real time; if the serial data rising edge jump is detected, starting a high-level counter Ch, and recording the clock period number of data keeping high level between the adjacent rising edge and the falling edge by the counter Ch; after the jump of the falling edge is detected, whether the Ch value falls into a value range [ theta 2-S, theta 1+S ] or not is compared, if Ch is in a [ theta 2-S, theta 1+S ] interval, that the receiving end receives 1bit 1 before the falling edge is shown, and 1bit 1 is moved into a shift cache register R1; if Ch is in the interval [2 theta 2-S,2 theta 1+S ], indicating that the receiving end receives continuous 2bit '1' before the falling edge, and moving 2bit '1' into the shift buffer register R1; if the serial data falling edge jump is detected, starting a low-level counter Cl, and recording the clock period number of data keeping low level between the adjacent falling edge and rising edge; after the rising edge jump is detected, whether the Cl value falls into a value range ([ theta 2-S, theta 1+S ], if Cl is in the interval of [ theta 2-S, theta 1+S ], the receiving end receives 1bit of 0 before the rising edge is shown, and 1bit of 0 is moved into the shift buffer register R1; if Cl is in the interval [2 theta 2-S,2 theta 1+S ], it indicates that the receiving end receives continuous 2bit '0' before the rising edge, and moves 2bit '0' into the shift buffer register R1, the data in the shift register R1 is compared into a group with 2 bits, whether the comparison data is 'bit 10' or 'bit 01' is judged, according to the coding rule of the image sensor, if "bit10" indicates that 1bit "0" is received, then 1bit "0" is shifted into the shift register R2; if it is "bit01", it means that 1bit "1" has been received, and 1bit "1" has been shifted into the shift register R2; at this time, the data in the shift register R2 is the data which is subjected to serial transmission and decoding recovery; i.e., the data in the shift register R2, is decoded according to the image sensor frame structure rules, frame synchronization, line data, etc. of the image can be decoded, as described in connection with figure 5, according to the counting results of the high level counter Ch and the low level counter Cl, when Cl =6, 4 is more than or equal to 6 and less than or equal to 7, the data receiving end restores the received data to 1bit '0', because Ch =5, 4 is less than or equal to 5 and less than or equal to 7, the data receiving end restores the received data to 1bit, since Cl =11, 9 is less than or equal to 11 is less than or equal to 13, the data receiving end restores the received data to 2bit 00', because Ch =11, 9 is less than or equal to 11 is less than or equal to 13, the data receiving end restores the received data to 2bit 11", and finally the serial data decoded by the data receiving end is 0100101101101101.
In summary, serial data from the image sensor can be oversampled according to the high-speed clock, and the approximate data transmission rate is calculated according to the oversampling result, so that the data receiving end can adaptively match the data rate of the transmitting end without knowing the transmission rate of the transmitting end in advance, and can recover the serial data without a special clock recovery circuit, thereby reducing the development cost.
The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that any equivalent structural changes made by using the contents of the specification and the drawings should be included in the scope of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A serial data recovery method of an image sensor, comprising:
when the image sensor is in an idle state, oversampling serial data from the image sensor by using a high-speed clock;
calculating the number of single-bit clock cycles and the number of two-bit clock cycles of the serial data according to the oversampling result;
acquiring the current clock period number of data retention between adjacent rising edges and falling edges of serial data when the image sensor is in a working state;
comparing the current clock period number with the single-bit clock period number or the two-bit clock period number, and performing serial data recovery according to the comparison result;
and decoding the recovered data according to the coding rule of the serial data sending end to obtain image data.
2. The method of claim 1, wherein oversampling serial data from an image sensor with a high speed clock comprises:
detecting the jump of the serial data rising edge and the falling edge of the miniature image sensor in real time;
when the serial data rising edge jump is detected, starting a high-level counter, and acquiring the clock period number of data keeping high level between adjacent rising edges and falling edges by using the high-level counter;
when the serial data falling edge jump is detected, starting a low level counter, and acquiring the clock period number of data keeping low level between adjacent falling edges and rising edges by using the low level counter;
calculating the single-bit clock period number and the two-bit clock period number of the serial data according to the oversampling result, comprising:
and determining the single-bit clock period number and the two-bit clock period number of the serial data according to the counting result of the high-level counter and the counting result of the low-level counter.
3. The method of claim 2, wherein determining the number of single-bit and two-bit clock cycles of the serial data according to the count result of the high-level counter and the count result of the low-level counter comprises:
averaging the counting results of the high-level counters acquired for multiple times to obtain a first average value, and averaging the counting results of the low-level counters acquired for multiple times to obtain a second average value;
determining a maximum number of single bit clock cycles according to a larger one of the first and second mean values, and determining a minimum number of single bit clock cycles according to a smaller one of the first and second mean values;
a maximum two bit clock cycle number is determined based on the maximum single bit cycle number and a minimum two bit clock cycle number is determined based on the minimum single bit cycle number.
4. The method of claim 3, wherein comparing the current number of clock cycles to the number of single bit clock cycles or two bit clock cycles, and performing serial data recovery based on the comparison comprises:
when the current clock period number is the counting result of the low-level counter and falls into a value interval consisting of the minimum single-bit clock period number and the maximum single-bit clock period number, determining that the received data is bit 0;
when the current clock period number is the counting result of the high-level counter and falls into a value interval consisting of the minimum single-bit clock period number and the maximum single-bit clock period number, determining the received data as bit 1;
when the current clock period number is the counting result of the low-level counter and falls into a value interval consisting of the minimum two-bit clock period number and the maximum two-bit clock period number, determining that the received data is bit 00;
and when the current clock period number is the counting result of the high-level counter and falls into a value interval consisting of the minimum two-bit clock period number and the maximum two-bit clock period number, determining that the received data is a bit 11.
5. The method according to any one of claims 1 to 4, wherein the high speed clock has a clock rate k times the serial data transfer rate of the image sensor, k being a positive integer.
6. The method of claims 1 to 4, further comprising, after obtaining the image data:
and analyzing the image data according to a frame format to obtain frame synchronization, line synchronization and line data.
7. A serial data recovery apparatus of an image sensor, comprising:
the sampling unit is used for oversampling serial data from the image sensor by using a high-speed clock when the image sensor is in an idle state;
the calculation unit is used for calculating the single-bit clock period number and the two-bit clock period number of the serial data according to the oversampling result;
the sampling unit is further used for acquiring the current clock period number of data retention between adjacent rising edges and falling edges of serial data when the image sensor is in a working state;
the computing unit is further configured to compare the current number of clock cycles with the number of single-bit clock cycles or the number of two-bit clock cycles;
a data recovery unit for serial data recovery according to the comparison result;
and the decoding unit is used for decoding the recovered data according to the coding rule of the serial data sending end to obtain image data.
8. The apparatus of claim 7, wherein the sampling unit, when oversampling serial data from the image sensor with the high-speed clock, is specifically configured to:
detecting the jump of the serial data rising edge and the falling edge of the miniature image sensor in real time;
when the serial data rising edge jump is detected, starting a high-level counter, and acquiring the clock period number of data keeping high level between adjacent rising edges and falling edges by using the high-level counter;
when the serial data falling edge jump is detected, starting a low level counter, and acquiring the clock period number of data keeping low level between adjacent falling edges and rising edges by using the low level counter;
the calculation unit calculates a single-bit clock cycle number and a two-bit clock cycle number of the serial data according to the oversampling result, and is specifically configured to:
and determining the single-bit clock period number and the two-bit clock period number of the serial data according to the counting result of the high-level counter and the counting result of the low-level counter.
9. The apparatus according to claim 8, wherein the calculating unit, when determining the number of single-bit clock cycles and the number of two-bit clock cycles of the serial data according to the counting result of the high-level counter and the counting result of the low-level counter, is specifically configured to:
averaging the counting results of the high-level counters acquired for multiple times to obtain a first average value, and averaging the counting results of the low-level counters acquired for multiple times to obtain a second average value;
determining a maximum number of single-bit clock cycles according to a larger one of the first and second averages and a minimum number of single-bit clock cycles according to a smaller one of the first and second averages;
a maximum two bit clock cycle number is determined based on the maximum single bit cycle number and a minimum two bit clock cycle number is determined based on the minimum single bit cycle number.
10. The apparatus according to any one of claims 7 to 9, wherein the high speed clock has a clock rate k times a serial data transfer rate of the image sensor, k being a positive integer.
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