CN115933811A

CN115933811A - Clock frequency adjusting system and method and electronic equipment

Info

Publication number: CN115933811A
Application number: CN202211664320.8A
Authority: CN
Inventors: 秦双双
Original assignee: Chixin Technology Beijing Co ltd
Current assignee: Chixin Technology Beijing Co ltd
Priority date: 2022-12-23
Filing date: 2022-12-23
Publication date: 2023-04-07

Abstract

The application provides a clock frequency adjusting system, a clock frequency adjusting method and electronic equipment, wherein the clock frequency adjusting system comprises a time sequence generator and a phase-locked loop, and the time sequence generator is in communication connection with the phase-locked loop; the time sequence generator is used for adjusting the frequency multiplication coarse adjustment coefficient of the phase-locked loop according to the obtained single adjustment amplitude and the times to be adjusted so as to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop to a target coarse adjustment coefficient; the times to be adjusted represent the times for adjusting the frequency multiplication coarse adjustment coefficient of the phase-locked loop, the difference between the target coarse adjustment coefficient and the initial value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop is equal to the product of the single adjustment amplitude and the times to be adjusted, and the absolute value of the ratio of the single adjustment amplitude to the smaller value of the initial value and the target coarse adjustment coefficient is smaller than a preset proportional threshold. Through multiple times of small-amplitude adjustment, lock losing is avoided, so that the time for frequency adjustment is saved, and additional hardware cost cannot be increased.

Description

Clock frequency adjusting system and method and electronic equipment

Technical Field

The present disclosure relates to the field of chips, and in particular, to a clock frequency adjusting system, a clock frequency adjusting method, and an electronic device.

Background

Dynamic Voltage and Frequency Scaling (DVFS) is a technology for optimizing chip power consumption, and dynamically adjusts the operating frequency and voltage of a chip (for the same chip, the higher the frequency is, the higher the required voltage is) according to different requirements of an application program or a load task operated by the chip on computing capacity, and specifically, the chip is in different performance levels when processing tasks of different loads by adjusting the frequency and voltage of the chip, thereby achieving the purpose of saving energy.

How to quickly and stably realize frequency adjustment becomes a problem which is continuously concerned by the technicians in the field.

Disclosure of Invention

It is an object of the present application to provide a clock frequency adjustment system, method and electronic device to at least partially improve the above problems.

In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:

in a first aspect, an embodiment of the present application provides a clock frequency adjustment system, where the adjustment system includes a timing generator and a phase-locked loop, where the timing generator is communicatively connected to the phase-locked loop;

the time sequence generator is used for adjusting the frequency multiplication coarse adjustment coefficient of the phase-locked loop according to the obtained single adjustment amplitude and the times to be adjusted so as to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop to a target coarse adjustment coefficient;

the frequency to be adjusted represents the number of times of adjusting the frequency doubling coarse adjustment coefficient of the phase-locked loop, the difference between the target coarse adjustment coefficient and the initial value of the frequency doubling coarse adjustment coefficient of the phase-locked loop is equal to the product of the single adjustment amplitude and the number of times to be adjusted, and the absolute value of the ratio of the single adjustment amplitude to the smaller value of the initial value and the target coarse adjustment coefficient is smaller than a preset proportional threshold.

Optionally, the timing generator is further configured to, according to the obtained fine tuning amplitude, synchronously adjust a frequency multiplication fine tuning coefficient of the phase-locked loop when adjusting the frequency multiplication coarse tuning coefficient of the phase-locked loop at the ith time, so as to adjust the frequency multiplication fine tuning coefficient of the phase-locked loop to a target fine tuning coefficient;

and i is more than or equal to 1 and less than or equal to N, N represents the number of times to be adjusted, and the difference between the target fine tuning coefficient and the initial value of the frequency doubling fine tuning coefficient of the phase-locked loop is equal to the fine tuning amplitude.

Optionally, the timing generator includes a first configuration register, a second configuration register, a third configuration register, a fourth configuration register, an intermediate value register control state machine, and a first output register, where the first configuration register is configured to store the target coarse tuning coefficient, the second configuration register is configured to store the single-time tuning amplitude, the third configuration register is configured to store the number of times to be tuned, the fourth configuration register is configured to store a starting value of a frequency multiplication coarse tuning coefficient of the pll, and the intermediate value register is configured to store a current value of the frequency multiplication coarse tuning coefficient of the pll;

the control state machine is used for writing the initial value into the intermediate value register as the current value of the frequency multiplication coarse tuning coefficient of the phase-locked loop when the numerical value in the first configuration register is monitored to be modified;

the control state machine is further used for writing the sum of the single adjustment amplitude and the current value into the first output register so as to transmit the sum to the phase-locked loop, so that the phase-locked loop adjusts the frequency multiplication coarse adjustment coefficient according to the value in the first output register;

the control state machine is further configured to write the value in the first output register into the intermediate value register, and update the current value of the frequency multiplication coarse tuning coefficient of the phase-locked loop;

the control state machine is further configured to record the adjusted times after each writing of the single adjustment magnitude to the first output register;

the control state machine is further configured to, in a case where the adjusted number of times is smaller than the number of times to be adjusted, repeatedly write the sum of the single-time adjustment amplitude and the current value into the first output register until the adjusted number of times is equal to the number of times to be adjusted.

Optionally, the timing generator further includes a fifth configuration register and a second output register, the fifth configuration register is used for storing the fine tuning amplitude;

the control state machine is further configured to write the fine tuning amplitude into the second output register when the frequency multiplication coarse tuning coefficient of the phase-locked loop is adjusted for the ith time, so as to transmit the fine tuning amplitude to the phase-locked loop, so that the phase-locked loop adjusts the frequency multiplication fine tuning coefficient according to the fine tuning amplitude;

Optionally, the clock frequency adjustment system further comprises a processor, the processor being communicatively coupled to the timing generator;

the processor is used for determining the target coarse adjustment coefficient, the single adjustment amplitude, the times to be adjusted, the initial value and the fine adjustment amplitude according to a target frequency point and an initial frequency point of the phase-locked loop;

the processor is further configured to write the target coarse tuning coefficient, the single-time tuning amplitude, the number of times to be tuned, and the start value into the first configuration register, the second configuration register, the third configuration register, the fourth configuration register, and the fifth configuration register, respectively.

Optionally, the processor is further configured to match the corresponding target frequency point according to a current load task of the system.

Optionally, the clock frequency adjustment system further includes a selector and a status register, the selector is respectively connected to the timing generator, the status register, the phase-locked loop, and the processor is connected to the status register;

the processor is further used for judging whether the frequency multiplication coarse tuning coefficient of the phase-locked loop needs to be adjusted or not according to the target frequency point and the starting frequency point;

the processor is further configured to control the selector to keep a communication link between the timing generator and the phase-locked loop clear when the frequency multiplication coarse tuning coefficient of the phase-locked loop needs to be adjusted;

the processor is further configured to control the selector to keep a communication link between the status register and the phase-locked loop clear and write the fine tuning amplitude and/or the target frequency division coefficient into the status register to adjust the frequency multiplication fine tuning coefficient or/and the frequency division coefficient of the phase-locked loop, when the frequency multiplication coarse tuning coefficient of the phase-locked loop does not need to be adjusted.

In a second aspect, an embodiment of the present application provides a clock frequency adjustment method, which is applied to an adjustment system, where the adjustment system includes a timing generator and a phase-locked loop, and the timing generator is communicatively connected to the phase-locked loop, and the method includes:

the time sequence generator adjusts the frequency multiplication coarse adjustment coefficient of the phase-locked loop according to the obtained single adjustment amplitude and the times to be adjusted so as to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop to a target coarse adjustment coefficient;

the times to be adjusted represent the times of adjusting the frequency multiplication coarse adjustment coefficient of the phase-locked loop, the difference between the target coarse adjustment coefficient and the initial value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop is equal to the product of the single adjustment amplitude and the times to be adjusted, and the absolute value of the ratio of the single adjustment amplitude to the smaller value of the initial value and the target coarse adjustment coefficient is smaller than a preset proportional threshold.

Optionally, the method further comprises:

the time sequence generator synchronously adjusts the frequency multiplication fine tuning coefficient of the phase-locked loop according to the obtained fine tuning amplitude when the frequency multiplication coarse tuning coefficient of the phase-locked loop is adjusted for the ith time so as to adjust the frequency multiplication fine tuning coefficient of the phase-locked loop to a target fine tuning coefficient;

In a third aspect, an embodiment of the present application provides an electronic device, including the above clock frequency adjustment system.

Compared with the prior art, the clock frequency adjusting system, the clock frequency adjusting method and the electronic equipment provided by the embodiment of the application comprise a time sequence generator and a phase-locked loop, wherein the time sequence generator is in communication connection with the phase-locked loop; the time sequence generator is used for adjusting the frequency multiplication coarse adjustment coefficient of the phase-locked loop according to the obtained single adjustment amplitude and the times to be adjusted so as to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop to a target coarse adjustment coefficient; the frequency to be adjusted represents the number of times of adjusting the frequency multiplication coarse adjustment coefficient of the phase-locked loop, the difference between the target coarse adjustment coefficient and the initial value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop is equal to the product of the single adjustment amplitude and the number of times to be adjusted, and the absolute value of the ratio of the single adjustment amplitude to the smaller value of the initial value and the target coarse adjustment coefficient is smaller than a preset proportional threshold. Through multiple times of small-amplitude adjustment, lock losing is avoided, so that the time for frequency adjustment is saved, and extra hardware cost is not increased.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a schematic structural diagram of a clock frequency adjustment system according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a timing generator according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a clock frequency adjustment system according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a clock frequency adjustment system according to an embodiment of the present application;

fig. 5 is a flowchart illustrating a clock frequency adjustment method according to an embodiment of the present application.

In the figure: 10-a timing generator; 20-a phase-locked loop; 30-a processor; 40-a status register; 50-a selector; 101-a first configuration register; 102-a second configuration register; 103-a third configuration register; 104-a fourth configuration register; 105-a fifth configuration register; 106-a control state machine; 107-intermediate value register; 108-a first output register; 109-second output register.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

It should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.

In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

The frequency adjustment is performed by using the DVFS technology, and comprises two possible modes, namely frequency divider adjustment and phase-locked loop adjustment. The phase-locked loop regulation and the frequency divider regulation have respective advantages and disadvantages. For pll tuning, a long lock time is required from the start of tuning to the final settling, and during this time, the clock signal output may cause execution errors. Therefore, in a processor using a phase-locked loop to adjust the frequency, two phase-locked loops (PLLs) are generally used, and the current PLL will switch to another standby PLL to provide a clock when adjusting the phase-locked loops, which increases the hardware cost and power consumption. And when the condition of losing lock occurs, the locking time of the PLL is more than tens of microseconds. Therefore, when a phase-locked loop is used to adjust the frequency, frequent adjustment is not suitable, which also results in fine-grained adjustment not being suitable when designing the DVFS algorithm. The frequency is adjusted much faster with the divider relative to the phase locked loop. Also, without a lock-in time, it takes only a few clock cycles to complete from the time the signal is received to the time it produces a stable output. Thus, a relatively fast frequency adjustment can be achieved, but this adjustment is not suitable for all frequency point changes. The current DVFS has finer and finer adjustment granularity, the difference between two adjacent DVFS frequency points is smaller and smaller, the DVFS cannot be realized through a frequency divider, and even if the DVFS can be realized, the DVFS is obtained by improving the frequency of a PLL phase-locked loop, so that the power consumption of the PLL is increased.

In order to overcome the above problems, embodiments of the present application provide a clock frequency adjustment system, which optimizes a DVFS implementation scheme, and implements relatively fast frequency adjustment on the basis of not increasing cost, thereby ensuring smooth implementation of fine granularity in a DVFS adjustment process.

Specifically, referring to fig. 1, fig. 1 is a schematic structural diagram of a clock frequency adjusting system according to an embodiment of the present disclosure.

As shown in fig. 1, the regulation system includes a timing generator 10 (PLL sequencer) and a phase locked loop 20 (PLL), the timing generator 10 and the phase locked loop 20 being communicatively coupled.

The timing generator 10 is configured to adjust a frequency multiplication coarse tuning coefficient (FBDIV) of the phase-locked loop 20 according to the obtained single adjustment amplitude and the number of times to be adjusted, so as to adjust the frequency multiplication coarse tuning coefficient of the phase-locked loop 20 to a target coarse tuning coefficient.

The times to be adjusted represent the times of adjusting the frequency doubling rough adjustment coefficient of the phase-locked loop 20, the difference between the target rough adjustment coefficient and the initial value of the frequency doubling rough adjustment coefficient of the phase-locked loop 20 is equal to the product of the single adjustment amplitude and the times to be adjusted, and the absolute value of the ratio of the single adjustment amplitude to the smaller value of the initial value and the target rough adjustment coefficient is smaller than a preset proportional threshold.

For example, if the starting value is 50 and the target coarse adjustment factor is 100, the absolute value of the ratio of the single adjustment amplitude to the starting value (50) is smaller than the preset proportional threshold. The initial value is 100, the target coarse adjustment coefficient is 50, and the absolute value of the ratio of the single adjustment amplitude to the target coarse adjustment coefficient (50) is smaller than a preset proportional threshold.

Optionally, the value of the ratio threshold may be, but is not limited to, 10%. Since the PLL does not lose lock when the FBDIV of the PLL changes its magnitude within a proportional threshold (e.g., + -10%), it can be adjusted to a corresponding frequency within 1 reference clock.

It should be understood that if the frequency multiplication coarse tuning coefficient of the PLL is directly adjusted from the initial value to the target coarse tuning coefficient, it may cause the PLL to lose lock, and it takes a long time to complete phase locking.

In summary, the embodiment of the present application provides a clock frequency adjustment system, which includes a timing generator and a phase-locked loop, where the timing generator is in communication connection with the phase-locked loop; the time sequence generator is used for adjusting the frequency multiplication coarse adjustment coefficient of the phase-locked loop according to the obtained single adjustment amplitude and the times to be adjusted so as to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop to a target coarse adjustment coefficient; the frequency to be adjusted represents the number of times of adjusting the frequency multiplication coarse adjustment coefficient of the phase-locked loop, the difference between the target coarse adjustment coefficient and the initial value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop is equal to the product of the single adjustment amplitude and the number of times to be adjusted, and the absolute value of the ratio of the single adjustment amplitude to the smaller value of the initial value and the target coarse adjustment coefficient is smaller than a preset proportional threshold. Through multiple times of small-amplitude adjustment, lock losing is avoided, so that the time for frequency adjustment is saved, and additional hardware cost cannot be increased.

In an optional implementation manner, the timing generator 10 is further configured to, according to the obtained fine tuning amplitude, synchronously adjust a frequency multiplication coarse tuning coefficient (FRAC) of the phase-locked loop 20 when adjusting the frequency multiplication coarse tuning coefficient of the phase-locked loop 20 for the ith time, so as to adjust the frequency multiplication fine tuning coefficient of the phase-locked loop 20 to a target fine tuning coefficient;

wherein i is greater than or equal to 1 and less than or equal to N, N represents the number of times to be adjusted, and the difference between the target fine tuning coefficient and the initial value of the frequency doubling fine tuning coefficient of the phase locked loop 20 is equal to the fine tuning amplitude.

Alternatively, the frequency doubling fine tuning coefficient (FRAC) of the phase-locked loop 20 may be synchronously adjusted each time the frequency doubling coarse tuning coefficient of the phase-locked loop 20 is adjusted, or the frequency doubling fine tuning coefficient (FRAC) of the phase-locked loop 20 may be synchronously adjusted only when the frequency doubling coarse tuning coefficient of the phase-locked loop 20 is adjusted for a certain time, for example, the frequency doubling fine tuning coefficient (FRAC) of the phase-locked loop 20 is synchronously adjusted when the frequency doubling coarse tuning coefficient of the phase-locked loop 20 is adjusted for the last (i = N) times.

It should be understood that by adjusting the frequency multiplication fine tuning coefficient, the frequency output by the phase-locked loop can be further ensured to accurately match the system.

With reference to fig. 2, fig. 2 is a schematic structural diagram of the timing generator provided in the embodiment of the present application.

As shown in fig. 2, the timing generator 10 includes a first configuration register 101 (target _ FBDIV), a second configuration register 102 (step _ size), a third configuration register 103 (step _ count), a fourth configuration register 104 (start _ FBDIV), an intermediate value register 107 (current _ FBDIV), a control state machine 106, and a first output register 108 (output _ FBDIV), where the first configuration register 101 is used to store a target coarse tuning coefficient, the second configuration register 102 is used to store a single-shot tuning amplitude (FBDIV step), the third configuration register 103 is used to store a to-be-tuned number (total step), the fourth configuration register 104 is used to store a start value of a frequency multiplication coarse tuning coefficient of the pll 20, and the intermediate value register 107 is used to store a current value of the frequency multiplication coarse tuning coefficient of the pll 20.

The initial value of the frequency-doubled coarse tuning coefficient of the phase-locked loop 20 refers to the value of the frequency-doubled coarse tuning coefficient of the phase-locked loop before tuning, and the initial value and the target coarse tuning coefficient may be, but are not limited to, written into corresponding registers by the processor 30 (MCU or CPU) in the following.

Optionally, control state machine 106 includes three states, an initial (INIT) state, a Send (SEND) state, and a Check (CHK) state. When no adjustment is required, the control state machine 106 is in the INIT state and monitors the first configuration register 101. Upon detecting that the value in the first configuration register 101 has been modified, the control state machine 106 jumps to the SEND state.

The control state machine 106 is configured to write a start value into the intermediate value register 107 as a current value of the frequency-doubled coarse-tuned coefficient of the phase locked loop 20 when it is monitored that the value in the first configuration register 101 is modified.

It should be understood. When the value in the first configuration register 101 is monitored to be modified, it indicates that a target coarse tuning coefficient is written into the first configuration register 101, and at this time, the frequency multiplication coarse tuning coefficient of the phase-locked loop 20 needs to be adjusted. In the adjusting process, the current value of the frequency multiplication coarse adjustment coefficient of the phase locked loop 20 is needed, so that the initial value is written into the intermediate value register 107 to be used as the current value of the frequency multiplication coarse adjustment coefficient of the phase locked loop 20.

The control state machine 106 is further configured to write the sum of the single adjustment magnitude and the current value into the first output register 108 for transmission to the pll 20, so that the pll 20 adjusts the frequency multiplication coarse adjustment coefficient thereof according to the value in the first output register 108.

For example, assume a starting value of 50 and a single adjustment of 10. The control state machine 106, after entering the SEND state, writes the start value (50) in the fourth configuration register 104 into the intermediate value register 107, i.e. the current value in the intermediate value register 107 is 50. The control state machine 106 also obtains the sum (60) of the current value (50) in the intermediate value register 107 and the single-shot trim amplitude (10). The sum (60) is then written into the first output register 108, and the sum (60) is sent to the pll 20 via the first output register 108, and the pll 20 adjusts its frequency multiplication coarse adjustment factor from 50 to 60 without losing lock.

It should be understood that in the solution of the present application, the adjustment of the frequency multiplication coarse tuning coefficient is performed in multiple times, and in order to facilitate the control state machine to obtain the current value of the phase locked loop 20, the embodiment of the present application also provides a possible implementation manner, please refer to the following.

The control state machine 106 is further configured to write the value in the first output register 108 into the intermediate value register 107, and update the current value of the frequency-doubled coarse tuning coefficient of the phase-locked loop 20.

Continuing with the above example, the control state machine 106 may also write the sum (60) into the intermediate value register 107 as the current value of the frequency doubling coarse tuning coefficient of the pll 20 for use in subsequent tuning.

It should be understood that, in order to ensure that the frequency multiplication coarse tuning coefficient of the phase locked loop 20 can be adjusted to the target coarse tuning coefficient, management statistics on the adjustment times are required, and refer to the following.

The control state machine 106 is also operative to record the adjusted number of times after each writing of the single adjustment magnitude to the first output register 108.

Alternatively, the initial value of the adjusted number of times (step _ number) may be 0, and after the first adjustment, step _ number +1 is performed, and the adjusted number of times (step _ number) =1, and so on until the adjusted number of times (step _ number) = the number of times to be adjusted.

In an alternative embodiment, after counting the adjusted number (step _ number), a check is needed to determine whether the frequency-doubled coarse tuning coefficient of the pll 20 has been adjusted to the target coarse tuning coefficient, and the control state machine 106 enters the CHK state and then determines based on the adjusted number (see below).

The control state machine 106 is further configured to repeat writing the sum of the single adjustment magnitude and the current value into the first output register 108 if the adjusted number is less than the number to be adjusted until the adjusted number is equal to the number to be adjusted.

It should be understood that the adjusted number of times is smaller than the number of times to be adjusted, which means that the frequency doubling coarse tuning coefficient of the phase locked loop 20 has not been adjusted to the target coarse tuning coefficient, and further adjustment is needed, and the control state machine 106 jumps to the SEND state.

With reference to the above example, assume that the initial value is 50, the single adjustment amplitude is 10, the target coarse adjustment coefficient is 100, and the number of times to be adjusted is 5. At the second time, the sum of the single adjustment amplitude and the current value is 70, the third time is 80, the fourth time is 90, and the fifth time is 100. The value of the intermediate value register 107 is transformed along with the value of the first output register 108 during the adjustment process.

When the adjusted number of times is equal to the number of times to be adjusted, it indicates that the frequency multiplication coarse adjustment coefficient of the phase locked loop 20 has been adjusted to the target coarse adjustment coefficient to complete the adjustment of the frequency multiplication coarse adjustment coefficient.

Alternatively, after the adjustment of the frequency doubled coarse tuning coefficient is completed, the control state machine 106 jumps to the INIT state, and the adjusted number of times (step number) may be cleared.

With continued reference to fig. 2, in an alternative embodiment, timing generator 10 further includes a fifth configuration register 105 (target _ FRAC) and a second output register 109 (output _ FRAC), where fifth configuration register 105 is used to store the trim magnitude.

The control state machine 106 is further configured to write the fine tuning amplitude into the second output register 109 for transmission to the phase-locked loop 20 when the ith time is performed to adjust the frequency multiplication coarse tuning coefficient of the phase-locked loop 20, so that the phase-locked loop 20 adjusts the frequency multiplication fine tuning coefficient thereof according to the fine tuning amplitude.

Wherein i is greater than or equal to 1 and less than or equal to N, N represents the number of times to be adjusted, and the difference between the target fine tuning coefficient and the initial value of the frequency doubling fine tuning coefficient of the phase-locked loop 20 is equal to the fine tuning amplitude.

It should be understood that the timing generator 10 is a hardware module that automatically performs PLL settings based on register configuration, enabling the PLL to output the target frequency in a short period of time by setting the PLL one or more times, the PLL remaining locked throughout the adjustment period.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a clock frequency adjustment system according to an embodiment of the present disclosure. As shown in fig. 3, the clock frequency adjustment system further includes a processor 30, and the processor 30 is communicatively coupled to the timing generator 10. Processor 30 may write a value to a register in timing generator 10.

Alternatively, the processor 30 may be an integrated circuit chip having signal processing capabilities. The Processor 30 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Micro Control Unit (MCU), a Network Processor (NP), and the like; the device can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, or a discrete hardware component.

In an alternative embodiment, the processor 30 is configured to determine the target coarse adjustment coefficient, the single adjustment amplitude, the number of times to be adjusted, the starting value, and the fine adjustment amplitude according to the target frequency point and the starting frequency point of the phase locked loop 20.

The starting frequency point is the clock frequency point of the pll 20 before adjustment.

The processor 30 is further configured to write the target coarse tuning coefficient, the single-time tuning amplitude, the number of times to be tuned, and the start value into the first configuration register 101, the second configuration register 102, the third configuration register 103, the fourth configuration register 104, and the fifth configuration register 105, respectively.

In an alternative embodiment, the processor 30 is further configured to match the corresponding target frequency point according to a current load task of the system.

As mentioned above, the operating frequency and voltage of the chip are dynamically adjusted according to the different requirements of the application program or the load task operated by the chip on the computing power.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a clock frequency adjustment system according to an embodiment of the present disclosure. As shown in fig. 4, the clock frequency adjustment system further includes a selector 50 (MUX) and a status register 40 (PLL registers), the selector 50 is connected to the timing generator 10, the status register 40, the phase locked loop 20, and the processor 30, respectively, and the processor 30 is connected to the status register 40.

The processor 30 is further configured to determine whether the frequency multiplication coarse adjustment coefficient of the phase-locked loop 20 needs to be adjusted according to the target frequency point and the starting frequency point.

The processor 30 is also configured to control the selector 50 to keep the timing generator 10 clear of the communication link with the phase locked loop 20 in the event that an adjustment of the multiplied coarse tuning factor of the phase locked loop 20 is required.

The processor 30 is further configured to control the selector 50 to keep the communication link between the status register 40 and the phase-locked loop 20 clear and to write the fine tuning amplitude and/or the target division factor into the status register 40 to adjust the frequency multiplication fine tuning coefficient or/and the division factor of the phase-locked loop 20, in case that the adjustment of the frequency multiplication coarse tuning coefficient of the phase-locked loop 20 is not required.

Alternatively, as shown in fig. 4, when performing DVFS demodulation, the processor 30 selects to directly configure the PLL registers or the PLL sequence according to the target frequency point and the start frequency point, and selects the PLL registers path when the target frequency point can be reached only by changing the frequency dividers (postiv 1/postiv 2), and otherwise selects the PLL sequence path. The processor 30 switches the selector 50 to the corresponding path by configuring HW _ SEL, selects the PLL sequencer path to control the input of the PLL when HW _ SEL =1, and selects the PLL registers output to control the input of the PLL when HW _ SEL = 0.

With continued reference to fig. 4, in one possible implementation, the clock frequency adjustment system further includes a resetting disposed between the selector 50 and the phase-locked loop 20. Optionally, retiming in the clock frequency adjustment system is adaptively set according to the requirements of the phase locked loop 20, which is not necessary.

The clock frequency adjusting system provided by the embodiment of the application can quickly switch the frequency of the DVFS, and according to the frequency range of the actual CPU DVFS and the PLL configuration parameters, the frequency switching only needs 250ns in the worst case, so that compared with dozens of us of a phase-locked loop adjusting mode, the efficiency of the DVFS frequency switching is greatly optimized, and the problem of low speed of the phase-locked loop adjusting mode is solved. The method is suitable for switching among all DVFS frequency points, and the problem that the coverage frequency range of a frequency divider adjusting mode is small is solved. The efficiency of DVFS is improved, and therefore the energy efficiency ratio of SOC is improved.

Referring to fig. 5, a clock frequency adjusting method provided in the embodiment of the present application can be applied to, but is not limited to, the above clock frequency adjusting system, and the specific process includes: s1001, S1002, and S1003, which will be described in detail below.

S1001, the time sequence generator obtains single adjustment amplitude and times to be adjusted.

And S1002, the timing generator adjusts the frequency multiplication coarse adjustment coefficient of the phase-locked loop according to the obtained single adjustment amplitude and the times to be adjusted, so as to adjust the frequency multiplication coarse adjustment coefficient of the phase-locked loop to a target coarse adjustment coefficient.

The frequency to be adjusted represents the number of times of adjusting the frequency multiplication coarse adjustment coefficient of the phase-locked loop, the difference between the target coarse adjustment coefficient and the initial value of the frequency multiplication coarse adjustment coefficient of the phase-locked loop is equal to the product of the single adjustment amplitude and the number of times to be adjusted, and the absolute value of the ratio of the single adjustment amplitude to the smaller value of the initial value and the target coarse adjustment coefficient is smaller than a preset proportional threshold.

And S1003, the timing generator synchronously adjusts the frequency multiplication fine adjustment coefficient of the phase-locked loop according to the obtained fine adjustment amplitude when the frequency multiplication coarse adjustment coefficient of the phase-locked loop is adjusted for the ith time so as to adjust the frequency multiplication fine adjustment coefficient of the phase-locked loop to be the target fine adjustment coefficient.

Wherein i is more than or equal to 1 and less than or equal to N, N represents the number of times to be adjusted, and the difference between the target fine tuning coefficient and the initial value of the frequency doubling fine tuning coefficient of the phase-locked loop is equal to the fine tuning amplitude.

It should be noted that the clock frequency adjusting method provided in this embodiment can perform the functions and purposes shown in the above clock frequency adjusting system embodiment to achieve the corresponding technical effects. For the sake of brief description, the embodiment is not mentioned in part, and reference may be made to the corresponding contents in the above embodiments.

The embodiment of the application also provides electronic equipment which comprises the clock frequency adjusting system. The electronic device may be, but is not limited to, a terminal device such as a mobile phone, a computer, and a server.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims

1. A clock frequency adjustment system, said adjustment system comprising a timing generator and a phase locked loop, said timing generator and said phase locked loop being communicatively coupled;

2. The clock frequency adjustment system of claim 1, wherein the timing generator is further configured to adjust the frequency multiplication fine tuning coefficient of the pll synchronously at the ith time of adjusting the frequency multiplication coarse tuning coefficient of the pll according to the obtained fine tuning amplitude, so as to adjust the frequency multiplication fine tuning coefficient of the pll to a target fine tuning coefficient;

3. The clock frequency adjustment system of claim 1, wherein the timing generator comprises a first configuration register for storing the target coarse tuning coefficient, a second configuration register for storing the single-shot adjustment magnitude, a third configuration register for storing the number of times to be adjusted, a fourth configuration register for storing a starting value of a frequency multiplication coefficient of the pll, an intermediate value register for storing a current value of the frequency multiplication coarse tuning coefficient of the pll, and a first output register;

the control state machine is used for writing the initial value into the intermediate value register when monitoring that the value in the first configuration register is modified, and the initial value is used as the current value of the frequency multiplication coarse tuning coefficient of the phase-locked loop;

the control state machine is further used for writing the sum of the single adjustment amplitude and the current value into the first output register so as to transmit the sum to the phase-locked loop, so that the phase-locked loop adjusts the frequency multiplication coarse adjustment coefficient of the phase-locked loop according to the value in the first output register;

4. The clock frequency adjustment system of claim 3, wherein the timing generator further comprises a fifth configuration register and a second output register, the fifth configuration register to store a trim magnitude;

5. The clock frequency adjustment system of claim 4, further comprising a processor communicatively coupled to the timing generator;

6. The clock frequency adjustment system of claim 5, wherein the processor is further configured to match a corresponding target frequency point based on a current load task of the system.

7. The clock frequency adjustment system of claim 5, further comprising a selector and a status register, the selector coupled to the timing generator, the status register, the phase locked loop, and the processor, respectively, the processor coupled to the status register;

the processor is further configured to determine whether the frequency multiplication coarse tuning coefficient of the phase-locked loop needs to be adjusted according to the target frequency point and the starting frequency point;

8. A clock frequency adjustment method, for use in an adjustment system, the adjustment system including a timing generator and a phase-locked loop, the timing generator and the phase-locked loop being communicatively coupled, the method comprising:

9. The clock frequency adjustment method of claim 8, further comprising:

10. An electronic device comprising a clock frequency adjustment system as claimed in any one of the preceding claims 1 to 7.