CN115932557A - Chip testing method, related equipment and computer-readable storage medium - Google Patents

Abstract

Embodiments of the present application provide a chip testing method, related equipment, and a computer-readable storage medium, relating to the field of chips. The method includes: obtaining the communication state between itself and the device under test through the chip test device; wherein, the chip under test contained in the device under test works in the target working environment data; when the communication state indicates normal, according to the preset The adjustment method determines the adjustment step, and updates the target working environment data according to the adjustment step, until the adjustment step reaches the preset threshold step, and the communication status indicates abnormality; where the last working environment data when the communication status indicates abnormality is pending The working environment boundary value of the test chip. The chip testing method, related equipment, and computer-readable storage medium provided by the embodiments of the present application have relatively accurate and convenient testing of the boundary value of the working environment data of the chip to be tested, and the ability to obtain the distribution range of the working environment data of the chip to be tested advantage.

Description

Chip testing method, related equipment and computer-readable storage medium

technical field

The present invention relates to the chip field, and specifically, the embodiments of the present invention relate to a chip testing method, related equipment, and a computer-readable storage medium.

Background technique

At present, how to obtain the driving environment data used to drive the chip, related components on the chip, or an electronic product (that is, the signal that provides power or energy for the related chip or product to make it work, for example, enabling the chip or the components on the chip to work The scope of the power signal or current signal) is becoming increasingly important.

For example, for the chip itself, the specific range of working environment data such as voltage and current specified by the chip is a key performance indicator. Therefore, the reference ideal working environment data range given by the chip design requires actual testing to continuously correct the specific working environment data range. .

For example, currently there are many types of chip peripheral interface devices (eg, keyboard, mouse, printer, etc.), so providing the working environment data range of the on-chip interface is increasingly important for adapting various devices.

Taking the working environment data of the chip as IO voltage (current) as an example, as shown in FIG. The measured result of the measurement method is the normal voltage fluctuation range in a certain use environment, it is difficult to measure the actual boundary of the chip IO voltage (current), and it is inconvenient to require specific test conditions to limit.

Contents of the invention

The purpose of the embodiment of the present invention is to provide a chip testing method-related equipment and computer-readable storage medium. By using the embodiment of the present invention, the boundary value of the working environment data of the chip to be tested can be tested relatively accurately and conveniently, and the data to be tested can be obtained. The distribution range of the working environment data of the chip.

In the first aspect, an embodiment of the present invention provides a chip testing method, which is applied to a chip testing system. The chip testing system includes a chip testing device and a device to be tested. The device to be tested is equipped with a chip to be tested. The device is used to provide working environment data for the chip under test, and establish communication with the chip testing device under the working environment data; The communication state between them; wherein, the chip under test contained in the device under test works in the target working environment data; in the case that the communication state indicates normal, the adjustment step is determined according to the preset adjustment method, and according to The adjustment step updates the target working environment data until the adjustment step reaches a preset threshold step, and the communication status indicates abnormality; wherein, the last working environment data when the communication status indicates abnormality is The working environment boundary value of the chip to be tested.

In some embodiments, the obtaining the communication state between itself and the device under test through the chip testing device includes: the chip testing device sends test data to the device under test; the chip testing device receiving the returned data fed back by the device under test, and determining that the communication status with the device under test is normal when the similarity between the test data and the returned data is greater than a first threshold; If the similarity between the test data and the returned data is less than the first threshold, it is determined that the communication status with the device under test is abnormal.

By providing test data to the device under test and checking the return data obtained from the test data fed back by the device under test, it is determined whether the data between the device under test and the chip testing device can be transmitted normally, and then it can be estimated more accurately Check whether the function of the chip is normal. In addition, due to the existence of measurement errors, it is difficult to achieve complete identicalness between the test data and the returned data. Therefore, after receiving the returned data, the chip testing device calculates the similarity between the returned data and the test data. When the returned data and the test data When the similarity is greater than the first threshold, it is also determined that the returned data is the same as the test data, the communication status between the chip testing device and the device under test is normal, and the current working environment data of the chip under test is that the chip under test can work normally. working environment data; when the similarity between the returned data and the test data is less than the first threshold, it is determined that the returned data is not the same as the test data. When an exception occurs, the communication status between the chip testing device and the device under test is abnormal, and the current working environment data of the chip under test exceeds the boundary value of the working environment where the chip under test can work normally, thereby reducing the impact of measurement errors on the measurement results Influence.

In some embodiments, updating the target working environment data according to the adjustment step includes: taking the adjustment step as a step, gradually reducing the target working environment data, and at the adjustment step When the preset step threshold is reached and the communication status indicates abnormality, it is determined that the target working environment data when the adjustment step reaches the preset step threshold and the communication status indicates abnormality is the chip under test The lower limit value that can be tolerated; gradually increase the target working environment data with the adjustment step size as the step size, when the adjustment step size reaches a preset step size threshold and the communication status indicates abnormality determining that the working environment data when the adjustment step reaches a preset step threshold and the communication status indicates abnormality is an upper limit value that the chip under test can bear.

Setting a larger adjustment step size can reduce the number of adjustments of the working environment data when the communication status indicates an abnormal situation; setting a smaller adjustment step size can improve the accuracy of the upper and lower limit values of the working environment data; Adjust the adjustment step in the process of working environment boundary value of the chip to be tested, so as to achieve the effect of reducing the number of adjustments and improving the accuracy of the results.

In some embodiments, the method further includes: determining that the chip under test is A normal chip; when the upper limit value that the chip to be tested can withstand is greater than or equal to the value determined under the heat dissipation design power consumption TDP of the chip to be tested, it is determined that the chip to be tested is an abnormal chip.

By comparing the measured upper limit value of the chip to be tested with the value determined under the heat dissipation design power consumption TDP of the chip to be tested, it is judged whether the chip to be tested is an abnormal chip, so as to realize further testing of the chip to be tested Whether it is an abnormal chip detection.

In some embodiments, the working environment data is the working voltage or working current of the chip under test.

In the second aspect, the embodiment of the present invention also provides a chip testing device, which is used to test the chip to be tested. The chip to be tested is carried in the device to be tested, and the device to be tested provides work for the chip to be tested. Environmental data, the chip testing device includes: a communication module, the communication module is used to communicate with the device under test; a communication state acquisition module, the communication state acquisition module is used to obtain the working state of the chip under test Under the working environment data, the communication state between the chip testing device and the device under test; a processing module, the processing module is used to determine the adjustment step according to the preset adjustment mode when the communication state indicates normal long, and update the target working environment data according to the adjustment step, until the preset threshold step is reached, and the communication status indicates abnormality; wherein, the last working environment data when the communication status indicates abnormality is the working environment boundary value of the chip under test.

In some embodiments, the communication module includes a sending submodule and a receiving submodule; the sending submodule is used to send test data to the device under test, and the receiving submodule is used to receive feedback from the device under test the return data; the communication status acquiring module is used to determine that the communication status with the device under test is normal when the similarity between the test data and the returned data is greater than a first threshold, If the similarity between the test data and the returned data is smaller than the first threshold, it is determined that the communication status with the device under test is abnormal.

In some embodiments, the device further includes: a power consumption judging module, the power consumption judging module is used to determine that the chip under test is under thermal design power consumption TDP when the upper limit value that the chip under test can bear is less than the chip under test When the determined value is determined, it is determined that the chip to be tested is a normal chip, and when the upper limit that the chip to be tested can bear is greater than or equal to the value determined under the heat dissipation design power consumption TDP of the chip to be tested, It is determined that the chip to be tested is an abnormal chip.

By setting the power consumption judging module, the upper limit value that the measured chip to be tested can bear is compared with the value determined under the heat dissipation design power consumption TDP of the chip to be tested, so as to judge whether the chip to be tested is an abnormal chip, and realize It is further detected whether the chip to be tested is an abnormal chip.

In the third aspect, the embodiment of the present invention also provides a chip testing system, which is used to test the chip to be tested, and the system includes the aforementioned chip testing device and a device to be tested that is communicatively connected to the chip testing device; The chip to be tested is mounted in a device to be tested, and the device to be tested provides working environment data for the chip to be tested.

In a fourth aspect, the embodiment of the present invention also provides an electronic device, including: at least one processor; and a memory connected to the at least one processor in communication; wherein, the memory stores information that can be used by the at least one processor Instructions executed by a processor, the instructions are executed by the at least one processor, so that the at least one processor can execute the aforementioned chip testing method.

In the fifth aspect, the embodiment of the present invention also provides a computer storage medium, on which a computer program is stored, wherein the computer program can implement the aforementioned chip testing method when executed by a processor.

In the chip testing method-related equipment and computer-readable storage medium provided in some embodiments of the present invention, the chip testing device obtains the communication status between itself and the device under test, and when the communication status indicates normal, it indicates the status of the device to be tested. The working status of the chip under test is also normal. Determine the adjustment step according to the preset adjustment method, and update the target working environment data of the chip under test according to the adjustment step until the adjustment step reaches the preset threshold step, and the communication status indicates abnormality , the abnormal communication status indicates that the working status of the chip under test is also abnormal, which means that the current working environment data exceeds the boundary value of the working environment data when the chip under test works normally, and the previous working environment when the communication status indicates abnormality The data is the working environment boundary value of the chip to be tested. In this way, the precise measurement of the boundary value of the working environment data of the chip to be tested can be realized.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, so It should not be regarded as a limitation on the scope, and those skilled in the art can also obtain other related drawings according to these drawings without creative work.

Fig. 1 is the method for obtaining the voltage or current range of the IO circuit interface on the CPU chip provided by the related art;

2 is a schematic flowchart of a chip testing method provided by Embodiment 1 of the present invention;

3 is a schematic structural diagram of a chip testing system applied to the flow of the chip testing method provided by Embodiment 1 of the present invention;

FIG. 4 is a schematic flowchart of a chip testing method provided in Embodiment 2 of the present invention;

5 is a schematic structural diagram of a chip testing device provided in Embodiment 3 of the present invention;

6 is a schematic structural diagram of a chip testing device provided by another embodiment of the present invention;

7 is a schematic structural diagram of a chip testing device provided in Embodiment 4 of the present invention;

FIG. 8 is a schematic structural diagram of a chip testing system provided in Embodiment 5 of the present invention;

FIG. 9 is a schematic structural diagram of an electronic device provided by Embodiment 6 of the present invention.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that like numerals and letters denote similar items in the following figures, therefore, once an item is defined in one figure, it does not require further definition and explanation in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second" and the like are only used to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

At least in order to solve the technical defects caused by the direct measurement of the background technology, in some embodiments of the present application, the working environment data (for example, chip IO voltage (current)) of the tested object is automatically adjusted, and the communication monitoring mechanism is used to determine the tested object. Whether the function of the test object is abnormal, and finally gradually determine the specific range of the driving signal required by the tested object, for example, to obtain the specific range of the chip IO voltage (current).

Please refer to Figure 1, as described in the background technology section, the measured result of the direct measurement is the normal voltage fluctuation range in a certain use environment, it is difficult to measure the actual boundary of the chip IO voltage (current) and other working environment data, and Specific test conditions need to be limited, which is inconvenient.

In view of the above technical problems, the present application proposes the following chip testing method-related devices and computer-readable storage media. The chip testing method provided by an embodiment of the present application is exemplarily described below in conjunction with FIG. 2, which is applied to the chip testing system shown in FIG. 3. The chip testing system includes a chip testing device 100 and a device under test 200. Equipped with a chip to be tested 300, the device to be tested 200 is used to provide a working environment for the chip to be tested 300, the chip to be tested 300 works in the working environment provided by the device to be tested 200, the working environment data is the device to be tested 200 is the The quantified data of the working environment provided by the chip 300 .

In some embodiments of the present application, the working environment data is the working voltage or working current when the chip under test 300 works in the device under test 200 . It can be understood that the aforementioned working environment data is the working voltage or working current of the chip under test 300 when it is working in the device under test 200. It is only an example in some embodiments of the present application. Can the environmental data be other types of data, such as the power of the chip 300 to be tested, the bus frequency of the chip 300 to be tested, etc.? Specifically, it can be flexibly used according to the type of working environment data that the chip 300 to be tested actually needs to measure.

The chip testing method is specifically shown in Figure 2, and may include but not limited to the following steps:

Step S101: Obtain the communication status between itself and the device under test through the chip testing device.

The implementation process of S101 is exemplarily described below.

In some embodiments of the present application, in order to obtain the communication status between itself and the device under test, the chip testing device first needs to send test data to the device under test, then receive the return data fed back by the device under test, and finally Data gets working status. In some embodiments of the present application, after the test data is sent to the device under test, the chip under test running in the device under test will forward the test data, and the test data will be sent to the chip test device after being forwarded by the chip under test. If the test data is the same as the returned data, it means that the chip under test can realize the normal forwarding function. At this time, the working environment data of the chip under test is the working environment data under which the chip under test can work normally.

In some embodiments of the present application, due to the existence of measurement errors, it is difficult to achieve complete consistency between the test data and the returned data. Therefore, in some embodiments of the present application, the first threshold is preset, and the first threshold is preset constant value, after the chip testing device receives the returned data, by calculating the similarity between the returned data and the test data, when the similarity between the returned data and the test data is greater than the first threshold, it is also determined that the returned data is the same as the test data, The communication state between the chip testing device and the device to be tested is normal, and the current working environment data of the chip to be tested is the working environment data in which the chip to be tested can work normally; when the similarity between the returned data and the test data is less than the first threshold , it is determined that the returned data is not the same as the test data. At this time, it is considered that the chip under test cannot normally complete the forwarding of the test data, the chip under test is abnormal, and the communication status between the chip test device and the device under test is abnormal. The current working environment data of the chip under test exceeds the boundary value of the working environment where the chip under test can work normally.

That is to say, the chip testing device in some embodiments of the present application determines the data between the device under test and the chip testing device by providing test data to the device under test and checking the return data obtained by the test data fed back by the device under test. Whether it can be transmitted normally, and then it can be more accurately inferred whether the function of the chip under test is normal.

It can be understood that, in some embodiments of the present application, in addition to completing the forwarding process of the test data, the chip to be tested can also use a preset data processing algorithm to perform data processing on the test data, such as deriving the test data , add one to the value, reverse the test data, etc., forward the data obtained after data processing of the test data to the chip test device as the return data, and the chip test device performs the same processing on the test data to obtain the final result compared with the return data test data, and then calculate the similarity between the returned data and the test data at this time, so as to judge whether the communication status between the device under test and the chip testing device is normal. Use the chip to be tested to process the test data and forward it to the chip test device, which can ensure that the returned data is the processed data of the chip to be tested, and avoid the wrong collection of the test data sent by the chip test device to cause the test results of the chip to be tested. influence, and improve the accuracy of the test results of the chip to be tested.

Step S102: When the communication state indicates normal, determine the adjustment step according to the preset adjustment method, and update the target working environment data according to the adjustment step, until the adjustment step reaches the preset threshold step and the communication state indicates abnormality.

The implementation process of S102 is exemplarily described below.

The chip to be tested has an initialized working environment data when it is designed, and the chip to be tested is designed and produced according to the initialized working environment data, but there may be various errors in the production process that lead to the final production. There is a certain difference between the working environment data where the chip under test can work normally and the initialized working environment data, and what this application wants to achieve is to measure more accurately the working environment data where the chip under test can work normally.

In some embodiments of the present application, the working environment data initially provided by the device under test to the chip under test is the working environment data initialized when the chip under test is designed, that is, the target working environment data. In the process of adjusting the target working environment data, it is necessary to measure the upper limit value and the lower limit value of the working environment data where the chip under test can work normally. For the lower limit value that the chip under test can bear, the target working environment data provided by the device under test can be gradually reduced by adjusting the step size until the communication state between the device under test and the chip testing device changes from normal to When it is abnormal, stop reducing the target working environment data provided by the device under test. At this time, it is determined that the working environment data when the communication state remains normal is the lower limit value that the chip under test can bear, that is, the value when the communication state changes to abnormal. The last working environment data is the lower limit value that the chip under test can bear.

The measurement process of the upper limit value that the chip under test can withstand is similar to the measurement process of the lower limit value that the chip under test can withstand, that is, take the adjustment step as the step size, and gradually increase the target working environment data provided by the device under test until When the communication state between the device under test and the chip testing device changes from normal to abnormal, stop increasing the target working environment data provided by the device under test. At this time, it is determined that the working environment data when the communication state last remains normal is the chip under test The upper limit value that can be tolerated, that is, the upper limit value that the chip under test can withstand is the last working environment data when the communication state changes to abnormal.

In some embodiments of the present application, the adjustment step size may also be adjusted during the process of determining the working environment boundary value of the chip to be tested. When the device under test is connected to the chip test device, the chip test device first uses a larger step size to adjust the target working environment data (which can be called a rough adjustment). When the communication status of the device changes to abnormal, reduce the adjustment step size, adjust the target working environment data to the working environment data at the last moment when the communication status between the device under test and the chip testing device remains normal, and use the reduced adjustment step Adjust the target working environment data at this time (it can be called fine adjustment) until the communication state between the device under test and the chip testing device changes to abnormal again. The working environment data is the working environment boundary value of the chip to be tested.

In some embodiments of the present application, the adjustment step size adjustment process can be performed multiple times, that is, each time the communication state between the device under test and the chip testing device changes to abnormal, the size of the adjustment step size is reduced, Until the adjustment step reaches the preset threshold step, and the communication state between the device under test and the chip testing device changes to abnormal again, at this time, it is considered that the last working environment data when the communication state indicates abnormality is the working environment of the chip under test Boundary value.

Using the rough adjustment method to confirm the working environment boundary value of the chip under test can effectively reduce the number of times to adjust the target working environment data and improve the test efficiency. On the basis of rough adjustment, use the fine adjustment method to determine the working environment boundary of the chip under test Confirming the value can improve the measurement accuracy of the working environment boundary value of the chip under test on the basis of improving the test efficiency.

In some embodiments of the present application, the chip testing device adjusts the target working environment data provided by the device under test by sending a driving signal to the device under test. Sending a driving signal to the device under test requires first generating a driving signal, for example, chip testing The device may include a driving signal generating device (for example, a power control IC and a corresponding circuit), and the corresponding driving signal is generated or updated by the device.

Two examples of drive signal generating devices are illustrated below.

For example, in some embodiments of the present application, when the target working environment data is the IO voltage (current) of the chip to be tested, the driving signal generating device includes a single-chip microcomputer dedicated to voltage and current regulation (this function can also be provided by the testing equipment. Processor completed), built-in programs such as coarse adjustment, fine adjustment and step size setting. In some embodiments of the present application, corresponding programs such as coarse adjustment and fine adjustment may also be set on the test equipment.

For example, in some embodiments of the present application, the driving signal generating device is an adjustable voltage and current circuit, which is mainly divided into two types, one is a digital power supply circuit (ie PWM CONTROLLER+POWER STAGE), and the second is a DC-DC circuit , wherein the resistance of the current limiting resistor and the feedback resistor can be adjusted by a dedicated single-chip microcomputer (or system processor), so as to realize the regulation of voltage and current.

Step S103: Use the last working environment data when the communication status indicates abnormality as the working environment boundary value of the chip under test.

The implementation process of S103 is exemplarily described below.

In some embodiments of the present application, when the communication state between the chip testing device and the device under test changes from normal to abnormal, it indicates that the current working environment data of the chip under test and the working environment boundary value of the chip under test are exceeded , and the chip to be tested can still work normally under the last working environment data when the communication status indicates abnormality, and the chip to be tested can no longer maintain normal work when the working environment data exceeds this working environment data, so the previous working environment when the communication status indicates abnormality The environmental data is the boundary value of the working environment of the chip to be tested.

In the chip testing method provided in Embodiment 1 of the present application, the chip testing device obtains the communication status between itself and the device under test. If the communication status indicates normal, it means that the working status of the chip under test is also normal. The preset adjustment method determines the adjustment step size, and updates the target working environment data of the chip under test according to the adjustment step size until the adjustment step size reaches the preset threshold step size, and the communication status indication is abnormal. The abnormal communication status indication indicates the chip under test The working status of the device is also abnormal, which means that the current working environment data exceeds the boundary value of the working environment data when the chip under test is working normally, and the last working environment data when the communication status indicates abnormality is the working environment of the chip under test Boundary value. In this way, the precise measurement of the boundary value of the working environment data of the chip to be tested can be realized.

Embodiment 2 of the present application provides a chip testing method, specifically as shown in FIG. 4 , including the following steps:

Step S201: Obtain the communication status between itself and the device under test through the chip testing device.

Step S202: When the communication state indicates normal, determine the adjustment step according to the preset adjustment method, and update the target working environment data according to the adjustment step, until the adjustment step reaches the preset threshold step and the communication state indicates abnormality.

Step S203: Use the last working environment data when the communication status indicates abnormality as the working environment boundary value of the chip under test.

It can be understood that the steps S201 to S203 in the chip testing method provided in Embodiment 2 of the present application are substantially the same as Steps S101 to S103 in Embodiment 1. For details, reference may be made to the specific descriptions of the foregoing embodiments, which are not described herein. Let me repeat.

Step S204: Determine whether the upper limit value that the chip under test can withstand is less than the value determined under the heat dissipation design power consumption TDP of the chip under test, if yes, execute step S205, if not, execute step S206.

The implementation process of S101 is exemplarily described below.

Thermal Design Power (TDP) is used to indicate the highest heat dissipation that a chip may achieve when it is working at full load. When the chip to be tested is in the TDP state, it corresponds to the value of a working environment data, if the upper limit value that the chip to be tested that is tested in step S203 can bear is greater than or equal to the value of the working environment data determined by the chip to be tested under TDP, It shows that the chip under test can still work normally when the target working environment data provided by the device under test is higher than the value of the working environment data determined under TDP, and the power of the chip under test under this working environment data has exceeded The maximum heat dissipation design power consumption that the chip to be tested can achieve indicates that the chip to be tested is an abnormal chip, and step S206 is performed; otherwise, if the upper limit that the chip to be tested can withstand is less than the value determined under the heat dissipation design power consumption TDP of the chip to be tested , it means that the chip to be tested is a normal chip, and step S205 is executed.

Step S205: Determine that the chip to be tested is a normal chip.

Step S206: Determine that the chip to be tested is an abnormal chip.

Compared with the prior art, the chip testing method provided in the second embodiment of the present application retains all the technical features of the first embodiment, and has the same technical effect as the first embodiment. In addition, in the second embodiment of the present application, by comparing the upper limit value that the chip to be tested can withstand with the value determined under the heat dissipation design power consumption TDP of the chip to be tested, it is judged whether the chip to be tested is abnormal chip, to realize further detection of whether the chip to be tested is an abnormal chip.

Embodiment 3 of the present application provides a chip testing device for testing the chip to be tested. When the chip testing device is testing the chip to be tested, the chip to be tested is carried in the device to be tested, and the device to be tested provides the chip to be tested. The working environment data and the chip testing device are shown in Figure 5, including:

The communication module 601, the communication module 601 is used to communicate with the device under test, including sending test data to the device under test and receiving the return data returned by the device under test, etc.; the communication status acquisition module 602, the communication status acquisition module 602 is used to acquire the Test the communication state between the chip testing device and the device under test when the chip works under the target working environment data, that is, the communication state acquisition module 602 is used to execute step S101 in the first embodiment; the processing module 603, the processing module 603 is used to When the communication status indication is normal, determine the adjustment step size according to the preset adjustment method, and update the target working environment data according to the adjustment step size until the preset threshold step size is reached, and the communication status indication is abnormal; wherein, the communication status indication is abnormal The last working environment data at that time is the working environment boundary value of the chip under test, that is, the processing module 603 is used to execute step S102 and step S103 in the first embodiment.

It is not difficult to find that the chip testing device provided in the third embodiment of the present application is an embodiment of the device corresponding to the chip testing method provided in the foregoing embodiment one, and the technical details in the third embodiment of the present application can be applied in the first embodiment In this application, the technical details in Embodiment 1 of the present application can also be applied in Embodiment 3.

Compared with the prior art, in the chip testing device provided in Embodiment 3 of the present application, the chip testing device obtains the communication status between itself and the device under test through the communication module 601 and the communication status acquisition module 602, and the communication status indicates normal In the case of , it means that the working state of the chip under test is also normal. The processing module 603 determines the adjustment step according to the preset adjustment method, and updates the target working environment data of the chip under test according to the adjustment step until the adjustment step reaches the preset Threshold step length, and the communication status indication is abnormal. The abnormal communication status indication indicates that the working status of the chip under test is also abnormal, which means that the current working environment data exceeds the boundary value of the working environment data when the chip under test is working normally. The last working environment data when the status indication is abnormal is the working environment boundary value of the chip to be tested. In this way, the precise measurement of the boundary value of the working environment data of the chip to be tested can be realized.

Further, in some other embodiments of the present application, as shown in FIG. 6 , the communication module 601 includes a sending submodule 6011 and a receiving submodule 6012; the sending submodule 6011 is used to send test data to the device under test, and the receiving submodule Module 6012 is used to receive the return data fed back by the device under test; the communication state acquisition module 602 is used to determine that the communication status with the device under test is Normal, if the similarity between the test data and the returned data is less than the first threshold, it is determined that the communication status with the device under test is abnormal.

Embodiment 4 of the present application provides a chip testing device, as shown in FIG. 7 , which also includes: a communication module 601, a communication state acquisition module 602, and a processing module 603. In addition, in this embodiment, the chip testing device also includes Power consumption judging module 604, the power consumption judging module 604 is used for determining that the chip to be tested is a normal chip when the upper limit value that the chip to be tested can bear is less than the value determined under the heat dissipation design power consumption TDP of the chip to be tested, and When the upper limit value that the chip to be tested can withstand is greater than or equal to the value determined under the heat dissipation design power consumption TDP of the chip to be tested, it is determined that the chip to be tested is an abnormal chip.

It is not difficult to find that the chip testing device provided in Embodiment 4 of the present application is an embodiment of the device corresponding to the chip testing method provided in Embodiment 2 above, and the technical details in Embodiment 4 of the present application can be applied to Embodiment 2 In this application, the technical details in Embodiment 2 of the present application can also be applied in Embodiment 4.

Compared with the prior art, in the chip testing device provided in Embodiment 4 of the present application, by setting the power consumption judging module 604, the measured upper limit value of the chip to be tested can be compared with the heat dissipation design power consumption TDP of the chip to be tested. The determined values are compared to determine whether the chip to be tested is an abnormal chip, so as to further detect whether the chip to be tested is an abnormal chip.

Embodiment 5 of the present application provides a chip testing system for testing a chip to be tested. As shown in FIG. The device to be tested 902, the chip to be tested is mounted in the device to be tested 902, the device to be tested 902 provides working environment data for the chip to be tested, and the chip testing device 901 executes the chip testing method provided in the foregoing embodiments to test the chip to be tested.

Compared with the prior art, the chip testing system provided in Embodiment 5 of the present application includes the chip testing device provided in the aforementioned embodiment, and the aforementioned chip testing method is run in the chip testing device, so it has the same technical effect as the aforementioned embodiment, For details, reference may be made to the specific descriptions of the foregoing embodiments.

Embodiment 6 of the present application provides an electronic device, as shown in FIG. 9 , including: at least one processor 1001; and a memory 1002 communicatively connected to at least one processor 1001; Instructions executed by the processor 1001, the instructions are executed by at least one processor 1001, so that the at least one processor 1001 can execute the aforementioned chip testing method.

Wherein, the memory 1002 may be a read-only memory 1002 (Read-Only Memory, ROM), a random access memory 1002 (Random Access Memory, RAM) or other memory 1002. In the embodiment of the present application, the memory 1002 is used to store data and various algorithms and commands, such as the algorithm for determining the IO voltage (current) range in the embodiment of the present application, the entire process and final results.

In the embodiment of the present application, the memory 1002 may include a physical device for storing information, and usually the information is digitized and then stored using an electrical, magnetic or optical medium. The memory 1002 of the present embodiment may also include: a device for storing information by means of electric energy, such as RAM, ROM, etc.; Disk; A device, such as a CD or DVD, that stores information optically. Of course, there are other types of memory 1002, such as quantum memory 1002, graphene memory 1002, and so on.

The processor 1001 is configured to read a computer program from the memory 1002, and execute the computer program to implement the chip testing method provided in the foregoing embodiments.

It should be noted that the processor 1001 may be a central processing unit (Central Processing Unit, CPU), and the processor 1001 may also be other processors 1001, a digital signal processor 1001 (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 1001 may be a microprocessor 1001 or the processor 1001 may be any conventional processor 1001 or the like. The processor 1001 may also be an integrated circuit chip, which has a signal processing capability. During implementation, each step of the IO voltage (current) testing method of the present application may be completed by an integrated logic circuit of hardware in the processor 1001 or instructions in the form of software.

In some embodiments of the present application, a driving signal generating device 1003 is also included, and the driving signal generating device 1003 is configured to receive the driving signal adjustment instruction sent by the processor 1001 to adjust the driving signal provided to the device under test, the device under test After receiving the driving signal, adjust the working environment data provided for the chip under test according to the driving signal.

For example, in some embodiments of the present application, the working environment data is the IO voltage or IO current of the chip, then the driving signal generating device 1003 is an IO voltage (current) control module, and the IO voltage (current) control module is mainly a power control IC and corresponding circuits.

The working process of the IO voltage (current) control module is exemplarily described below.

In some embodiments of the present application, after receiving the driving signal adjustment instruction from the processor 1001, the IO voltage (current) control module constructs the driving signal according to the driving signal adjustment instruction, and sends the driving signal to the device under test, The IO voltage (current) provided to the chip under test is adjusted accordingly by controlling the device under test.

In some embodiments of the present application, the driving signal generating device 1003 can also automatically adjust working environment data such as the IO voltage (current) provided by the device under test to the chip under test according to the pre-classified levels of the processor 1001.

As shown in FIG. 9 , in some embodiments of the present application, the electronic device further includes: a display module 1004 configured to display a drive signal boundary value and/or receive an input drive signal adjustment step value.

It should be noted that, in some embodiments of the present application, the display module is also used to display the content of the entire process, including the communication status between the device under test and the chip testing device, the similarity between the returned data and the test data value, etc., the embodiment of the present application does not limit the specific content displayed by the display module.

The display module 1004, the display module is not limited to various display methods, for example, it may be a digital tube display or a liquid crystal screen, LCD, OLED, etc. The connection methods are not limited, such as IIC, SPI, UART, MIPI, DP, eDP and HDMI, etc. The main function of this module is to visually display the entire testing process and final results.

As shown in FIG. 9 , in some embodiments of the present application, the electronic device further includes: a communication interface 1005 . The communication interface 1005 uses a transceiver device such as but not limited to a transceiver to realize the communication between the chip testing device and the device under test.

Embodiment 7 of the present application provides a computer storage medium, on which a computer program is stored. When the computer program is executed by a processor, the method of any embodiment included in the above method for obtaining a driving signal can be implemented.

In the several embodiments provided in this application, it should be understood that the disclosed devices and methods may also be implemented in other ways. The device embodiments described above are only illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functions and possible implementations of devices, methods and computer program products according to multiple embodiments of the present application. operate. In this regard, each block in a flowchart or block diagram may represent a module, program segment, or part of code that includes one or more Executable instructions. It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by a dedicated hardware-based system that performs the specified function or action , or may be implemented by a combination of dedicated hardware and computer instructions.

In addition, each functional module in each embodiment of the present application may be integrated to form an independent part, each module may exist independently, or two or more modules may be integrated to form an independent part.

If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disc, etc., which can store program codes. .

The above descriptions are only examples of the present application, and are not intended to limit the scope of protection of the present application. For those skilled in the art, various modifications and changes may be made to the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included within the protection scope of this application. It should be noted that like numerals and letters denote similar items in the following figures, therefore, once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

Claims (11)

1. A method for testing a chip, characterized in that it is applied to a chip testing system, the chip testing system includes a chip testing device and a device to be tested, the device to be tested is equipped with a chip to be tested, and the device to be tested is used for Providing working environment data for the chip to be tested, and establishing communication with the chip testing device under the working environment data; the method includes: Obtaining the communication state between itself and the device under test through the chip testing device; wherein, the chip under test contained in the device under test works in the target working environment data; When the communication state indicates normal, determine an adjustment step according to a preset adjustment method, and update the target working environment data according to the adjustment step until the adjustment step reaches a preset threshold step, and The communication state indicates abnormality; Wherein, the last working environment data when the communication status indicates abnormality is the working environment boundary value of the chip under test. 2. The method according to claim 1, wherein said obtaining the communication state between itself and the device under test through the chip testing device comprises: The chip testing device sends test data to the device under test; The chip testing device receives the return data fed back by the device under test, and determines to communicate with the device under test when the similarity between the test data and the return data is greater than a first threshold The status is normal, and if the similarity between the test data and the returned data is less than the first threshold, it is determined that the communication status with the device under test is abnormal. 3. The method according to claim 1, wherein said updating said target working environment data according to said adjustment step size comprises: Taking the adjustment step as a step, gradually reducing the target working environment data, and determining the adjustment step when the adjustment step reaches a preset step threshold and the communication status indicates abnormality The last working environment data when the preset step threshold is reached and the communication status indicates abnormality is the lower limit value that the chip under test can bear; Taking the adjustment step as a step, gradually increasing the target working environment data, and determining the adjustment step when the adjustment step reaches a preset step threshold and the communication status indicates abnormality The last working environment data when the preset step size threshold is reached and the communication status indicates abnormality is the upper limit value that the chip under test can bear. 4. The method of claim 3, further comprising: When the upper limit value that the chip to be tested can withstand is less than the value determined under the heat dissipation design power consumption TDP of the chip to be tested, it is determined that the chip to be tested is a normal chip; When the upper limit value that the chip to be tested can withstand is greater than or equal to the value determined under the heat dissipation design power consumption TDP of the chip to be tested, it is determined that the chip to be tested is an abnormal chip. 5. The method according to claim 1, wherein the working environment data is the working voltage or working current of the chip under test. 6. A chip testing device, characterized in that, it is used to test the chip to be tested, the chip to be tested is carried in the device to be tested, the device to be tested provides working environment data for the chip to be tested, the Chip testing equipment includes: a communication module, the communication module is used to communicate with the device under test; A communication state acquisition module, the communication state acquisition module is used to obtain the communication state between the chip testing device and the device under test when the chip under test works under the target working environment data; A processing module, the processing module is used to determine the adjustment step according to the preset adjustment method when the communication status indicates normal, and update the target working environment data according to the adjustment step until the preset is reached. A threshold step size is set, and the communication status indicates abnormality; wherein, the last working environment data when the communication status indicates abnormality is the working environment boundary value of the chip under test. 7. The device according to claim 6, wherein the communication module comprises a sending submodule and a receiving submodule; The sending submodule is used to send test data to the device under test, and the receiving submodule is used to receive return data fed back by the device under test; The communication state acquisition module is used to determine that the communication state with the device under test is normal when the similarity between the test data and the returned data is greater than a first threshold. If the similarity between the data and the returned data is less than the first threshold, it is determined that the communication status with the device under test is abnormal. 8. The device of claim 6, further comprising: A power consumption judging module, the power consumption judging module is used to determine the chip to be tested when the upper limit value that the chip to be tested can withstand is less than the value determined under the heat dissipation design power consumption TDP of the chip to be tested It is a normal chip, and when the upper limit value that the chip to be tested can bear is greater than or equal to the value determined under the heat dissipation design power consumption TDP of the chip to be tested, it is determined that the chip to be tested is an abnormal chip. 9. A chip testing system, characterized in that, for testing a chip to be tested, the system includes the chip testing device as claimed in any one of claims 6 to 8 and a chip testing device communicatively connected with the chip testing device the device under test; The chip under test is carried in a device under test, and the device under test provides working environment data for the chip under test. 10. An electronic device, characterized in that it comprises: at least one processor; and, a memory communicatively coupled to the at least one processor; Wherein, the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor, so that the at least one processor can perform any one of claims 1 to 5. The chip test method described in the item. 11. A computer storage medium on which a computer program is stored, wherein the computer program can implement the chip testing method according to any one of claims 1 to 5 when the computer program is executed by a processor.

Images