CN115932557A - Chip testing method, related device and computer readable storage medium - Google Patents

Abstract

The embodiment of the application provides a chip testing method, related equipment and a computer readable storage medium, and relates to the field of chips. The method comprises the following steps: acquiring a communication state between the chip testing device and a device to be tested through the chip testing device; the chip to be tested contained in the device to be tested works in target working environment data; under the condition that the communication state indication is normal, determining an adjustment step length according to a preset adjustment mode, and updating target working environment data according to the adjustment step length until the adjustment step length reaches a preset threshold step length and the communication state indication is abnormal; and the last working environment data when the communication state indication is abnormal is a working environment boundary value of the chip to be tested. The chip testing method, the related equipment and the computer readable storage medium provided by the embodiment of the application have the advantages of relatively accurately and conveniently testing the boundary value of the working environment data of the chip to be tested and acquiring the distribution range of the working environment data of the chip to be tested.

Description

Chip testing method, related device and computer readable storage medium

Technical Field

The invention relates to the field of chips, in particular to a chip testing method, related equipment and a computer readable storage medium.

Background

At present, it is increasingly important to obtain a range of driving environment data (i.e., a signal for providing power or energy to the chip or the related product to operate, for example, a power signal or a current signal for enabling the chip or the component on the chip to operate) for driving the chip, the related component on the chip, or some electronic product.

For example, for the chip itself, the specific range of the working environment data such as voltage, current, etc. specified by the chip is a key performance index, so that the reference ideal working environment data range given by the chip design needs to be actually tested to continuously correct the specific working environment data range.

For example, current chip peripheral interface devices (e.g., keyboard, mouse, printer, etc.) are widely varied, and thus the range of operating environment data that provides an on-chip interface is increasingly important to accommodate a variety of devices.

Taking the working environment data of the chip as the IO voltage (current) as an example, as shown in fig. 1, in order to obtain the working voltage or current of the IO circuit of fig. 1, in the prior art, a direct measurement mode is generally adopted, and it can be understood that a measured result in the direct measurement mode is a normal voltage fluctuation range in a certain use environment, it is difficult to realize the measurement of the actual boundary of the IO voltage (current) of the chip, and it is not convenient to perform the limitation of a specific test condition.

Disclosure of Invention

The embodiment of the invention aims to provide a chip testing method, related equipment and a computer readable storage medium, by adopting which the boundary value of the working environment data of the chip to be tested can be tested relatively accurately and conveniently, and the distribution range of the working environment data of the chip to be tested can be obtained.

In a first aspect, an embodiment of the present invention provides a chip testing method, which is applied to a chip testing system, where the chip testing system includes a chip testing device and a device to be tested, where the device to be tested is loaded with a chip to be tested, and the device to be tested is configured to provide working environment data for the chip to be tested and establish communication with the chip testing device under the working environment data; the method comprises the following steps: acquiring a communication state between the chip testing device and the device to be tested through the chip testing device; the chip to be tested contained in the device to be tested works in target working environment data; under the condition that the communication state indication is normal, determining an adjustment step length according to a preset adjustment mode, and updating the target working environment data according to the adjustment step length until the adjustment step length reaches a preset threshold step length and the communication state indication is abnormal; and the last working environment data when the communication state indication is abnormal is the working environment boundary value of the chip to be tested.

In some embodiments, the obtaining, by the chip testing device, a communication state between the chip testing device and the device under test includes: the chip testing device sends testing data to the device to be tested; the chip testing device receives return data fed back by the device to be tested, determines that the communication state between the chip testing device and the device to be tested is normal under the condition that the similarity between the testing data and the return data is larger than a first threshold value, and determines that the communication state between the chip testing device and the device to be tested is abnormal under the condition that the similarity between the testing data and the return data is smaller than the first threshold value.

Whether the data between the device to be tested and the chip testing device can be normally transmitted or not is determined by providing the testing data for the device to be tested and checking the returned data which is fed back by the device to be tested and is obtained by the testing data, and whether the function of the chip to be tested is normal or not can be accurately presumed. In addition, due to the existence of measurement errors, the test data and the return data are difficult to be completely identical, therefore, after the chip test device receives the return data, the similarity between the return data and the test data is calculated, when the similarity between the return data and the test data is greater than a first threshold value, the return data and the test data are also considered to be identical, the communication state between the chip test device and the device to be tested is normal, and the current working environment data of the chip to be tested is the working environment data of the chip to be tested, which can normally work; when the similarity of the returned data and the test data is smaller than the first threshold, the returned data and the test data are determined to be different, at the moment, the chip to be tested cannot normally complete the forwarding of the test data, the chip to be tested is abnormal in work, the communication state between the chip test device and the device to be tested is abnormal, the current working environment data of the chip to be tested exceeds the working environment boundary value of the chip to be tested, and therefore the influence of the measurement error on the measurement result is reduced.

In some embodiments, said updating said target operating environment data according to said adjustment step size comprises: gradually reducing the target working environment data by taking the adjusting step length as a step length, and under the condition that the adjusting step length reaches a preset step length threshold and the communication state indication is abnormal, determining that the target working environment data when the adjusting step length reaches the preset step length threshold and the communication state indication is abnormal is a lower limit value which can be borne by the chip to be tested; and with the adjusting step length as a step length, gradually increasing the target working environment data, and under the condition that the adjusting step length reaches a preset step length threshold value and the communication state indication is abnormal, determining that the working environment data when the adjusting step length reaches the preset step length threshold value and the communication state indication is abnormal is an upper limit value which can be borne by the chip to be tested.

The adjustment times of the working environment data when the communication state indication abnormal condition is reached can be reduced by setting a larger adjustment step length; the accuracy of the upper limit value and the lower limit value of the working environment data can be improved by setting a smaller adjusting step length; the adjusting step length is adjusted in the process of determining the working environment boundary value of the chip to be measured, so that the effects of reducing the adjusting times and improving the result accuracy are achieved.

In some embodiments, the method further comprises: when the upper limit value which can be borne by the chip to be tested is smaller than the value determined when the chip to be tested is under the heat dissipation design power consumption TDP, determining the chip to be tested as a normal chip; and when the upper limit value which can be borne by the chip to be tested is greater than or equal to the numerical value determined when the chip to be tested is under the heat dissipation design power consumption TDP, determining that the chip to be tested is an abnormal chip.

And comparing the upper limit value which can be borne by the chip to be detected and the value which is determined when the chip to be detected is under the heat dissipation design power consumption TDP, judging whether the chip to be detected is an abnormal chip, and further detecting whether the chip to be detected is the abnormal chip.

In some embodiments, the operating environment data is an operating voltage or an operating current of the chip to be tested.

In a second aspect, an embodiment of the present invention further provides a chip testing apparatus, configured to test a chip to be tested, where the chip to be tested is mounted in a device to be tested, and the device to be tested provides working environment data for the chip to be tested, and the chip testing apparatus includes: a communication module for communicating with the device under test; the communication state acquisition module is used for acquiring the communication state between the chip testing device and the device to be tested when the chip to be tested works in the target working environment data; the processing module is used for determining an adjusting step length according to a preset adjusting mode under the condition that the communication state indication is normal, and updating the target working environment data according to the adjusting step length until the preset threshold step length is reached and the communication state indication is abnormal; and the last working environment data when the communication state indication is abnormal is the working environment boundary value of the chip to be tested.

In some embodiments, the communication module includes a transmit sub-module and a receive sub-module; the sending submodule is used for sending test data to the device to be tested, and the receiving submodule is used for receiving return data fed back by the device to be tested; the communication state acquisition module is used for determining that the communication state between the communication state acquisition module and the device to be tested is normal under the condition that the similarity between the test data and the return data is greater than a first threshold value, and determining that the communication state between the communication state acquisition module and the device to be tested is abnormal under the condition that the similarity between the test data and the return data is less than the first threshold value.

In some embodiments, the apparatus further comprises: the power consumption judgment module is used for determining that the chip to be tested is a normal chip when the chip to be tested is in the numerical value determined under the heat dissipation design power consumption TDP, and determining that the chip to be tested is an abnormal chip when the chip to be tested is in the numerical value determined under the heat dissipation design power consumption TDP.

The upper limit value which can be borne by the chip to be detected and is obtained through measurement is compared with the value determined when the chip to be detected is under the heat dissipation design power consumption TDP through the power consumption judging module, whether the chip to be detected is an abnormal chip or not is judged, and further detection on whether the chip to be detected is the abnormal chip or not is achieved.

In a third aspect, an embodiment of the present invention further provides a chip testing system, configured to test a chip to be tested, where the system includes the chip testing apparatus and a device to be tested, which is in communication connection with the chip testing apparatus; the chip to be tested is carried in a device to be tested, and the device to be tested provides working environment data for the chip to be tested.

In a fourth aspect, an embodiment of the present invention further provides an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform a chip testing method as described above.

In a fifth aspect, an embodiment of the present invention further provides a computer storage medium, on which a computer program is stored, where the computer program is executed by a processor, and is capable of implementing the chip testing method as described above.

In some embodiments of the chip testing method related devices and the computer readable storage medium provided by the present invention, a communication state between the chip testing device and the device to be tested is obtained through the chip testing device, when the communication state indicates normal, it indicates that a working state of the chip to be tested is also normal, an adjustment step is determined according to a preset adjustment mode, and target working environment data of the chip to be tested is updated according to the adjustment step until the adjustment step reaches a preset threshold step, and when the communication state indicates abnormal, which indicates that the working state of the chip to be tested is also abnormal, that is, it indicates that the current working environment data exceeds a boundary value of working environment data of the chip to be tested when the chip to be tested normally works, and the last working environment data when the communication state indicates abnormal is a working environment boundary value of the chip to be tested. Therefore, the boundary value of the working environment data of the chip to be measured is accurately measured.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other relevant drawings can be obtained based on the drawings without inventive effort.

Fig. 1 is a method for obtaining a voltage or current range of an IO circuit interface on a CPU chip according to the related art;

FIG. 2 is a schematic flow chart illustrating a chip testing method according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a chip testing system applied in a flow of a chip testing method according to an embodiment of the present invention;

FIG. 4 is a schematic flowchart illustrating a chip testing method according to a second embodiment of the present invention;

fig. 5 is a schematic structural diagram of a chip testing apparatus according to a third embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a chip testing apparatus according to another embodiment of the present invention;

fig. 7 is a schematic structural diagram of a chip testing apparatus according to a fourth embodiment of the present invention;

fig. 8 is a schematic structural diagram of a chip test system according to a fifth embodiment of the present invention;

fig. 9 is a schematic structural diagram of an electronic device according to a sixth embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

At least to solve the technical defects caused by the direct measurement in the background art, in some embodiments of the present application, by automatically adjusting the working environment data (e.g., chip IO voltage (current)) of the object to be tested, a communication monitoring mechanism is used to determine whether the function of the object to be tested is abnormal, and finally, a specific range of the driving signal required by the object to be tested is determined step by step, for example, the specific range of the chip IO voltage (current) is obtained.

Referring to fig. 1, as the direct measurement described in the background art section shows a normal voltage fluctuation range in a certain usage environment, it is difficult to measure the actual boundary of the working environment data such as the IO voltage (current) of the chip, and it is inconvenient to perform a specific test condition limitation.

In view of the above technical problems, the present application provides a chip testing method related device and a computer readable storage medium as follows. The following describes, by way of example, the chip testing method provided in an embodiment of the present application with reference to fig. 2, and is applied to the chip testing system shown in fig. 3, where the chip testing system includes a chip testing device 100 and a device under test 200, the device under test 200 is loaded with a chip 300 to be tested, the device under test 200 is used to provide a working environment for the chip 300 to be tested, the chip 300 to be tested operates in the working environment provided by the device under test 200, and the working environment data is quantized data of the working environment provided by the device under test 200 for the chip 300 to be tested.

In some embodiments of the present application, the operating environment data is an operating voltage or an operating current of the chip 300 under test when operating in the device under test 200. It is understood that the foregoing operating environment data is only an example of some embodiments of the present application, and in other embodiments of the present application, the operating environment data may also be other types of data, such as power of the chip 300 to be tested, bus frequency of the chip 300 to be tested, and the like, and may be flexibly used according to the type of the operating environment data actually required to be measured by the chip 300 to be tested.

The chip testing method specifically shown in fig. 2 may include, but is not limited to, the following steps:

step S101: and acquiring the communication state between the chip testing device and the device to be tested through the chip testing device.

The following exemplarily explains the implementation process of S101.

In some embodiments of the present application, in order to obtain a communication state between the chip test apparatus and a device under test, the chip test apparatus needs to first send test data to the device under test, then receive return data fed back by the device under test, and finally obtain a working state according to the test data and the return data. In some embodiments of the application, after the test data is sent to the device to be tested, the chip to be tested running in the device to be tested can forward the test data, the test data is forwarded by the chip to be tested and then sent to the chip test device, that is, the test data is returned, if the test data is the same as the return data, it is indicated that the chip to be tested can realize a normal forwarding function, and at this time, the working environment data of the chip to be tested is the working environment data of the chip to be tested, which can normally work.

In some embodiments of the present application, due to the existence of a measurement error, it is difficult for the test data and the return data to be completely identical, so in some embodiments of the present application, a first threshold is preset, where the first threshold is a preset constant value, after the chip testing device receives the return data, the chip testing device calculates the similarity between the return data and the test data, and when the similarity between the return data and the test data is greater than the first threshold, it is also determined that the return data is identical to the test data, a communication state between the chip testing device and the device to be tested is normal, and current working environment data of the chip to be tested is working environment data in which the chip to be tested can normally work; when the similarity between the returned data and the test data is smaller than the first threshold, the returned data and the test data are determined to be different, at this moment, the chip to be tested cannot normally complete the forwarding of the test data, the chip to be tested is abnormal in work, the communication state between the chip testing device and the device to be tested is abnormal, and the current working environment data of the chip to be tested exceeds the working environment boundary value of the chip to be tested, which can normally work.

That is to say, the chip testing device according to some embodiments of the present application determines whether data between the device under test and the chip testing device can be normally transmitted by providing the testing data to the device under test and checking the returned data obtained from the testing data fed back by the device under test, so as to more accurately estimate whether the function of the chip under test is normal.

It can be understood that, in some embodiments of the present application, in addition to completing the forwarding process of the test data, the chip to be tested may also perform data processing on the test data by using a preset data processing algorithm, for example, derivation, value addition, inversion of the test data, and the like on the test data, forward the data obtained after the data processing on the test data to the chip testing apparatus as the return data, perform the same processing on the test data by the chip testing apparatus to obtain the test data finally compared with the return data, and then calculate the similarity between the return data and the test data at this time to determine whether the communication state between the device to be tested and the chip testing apparatus is normal. The chip to be tested is used for conducting data processing on the test data and then forwarding the data to the chip testing device, the returned data can be guaranteed to be the data processed by the chip to be tested, the test result of the chip to be tested is prevented from being influenced due to the fact that the test data sent by the chip testing device are collected by mistake, and the accuracy of the test result of the chip to be tested is improved.

Step S102: and under the condition that the communication state indication is normal, determining an adjustment step length according to a preset adjustment mode, and updating target working environment data according to the adjustment step length until the adjustment step length reaches a preset threshold step length and the communication state indication is abnormal.

The following exemplarily sets forth the implementation of S102.

The chip to be tested has an initialized working environment data during design, the chip to be tested is designed and produced according to the initialized working environment data, however, various errors may exist in the production process, so that a certain difference exists between the final working environment data, which is obtained by production and can work normally, of the chip to be tested and the initialized working environment data, and what is to be achieved by the method is to measure the working environment data, which can work normally, of the chip to be tested more accurately.

In some embodiments of the present application, the working environment data initially provided by the device to be tested to the chip to be tested is the working environment data initialized during the design of the chip to be tested, that is, the target working environment data. In the process of adjusting the target working environment data, an upper limit value and a lower limit value of the working environment data of the chip to be measured, which can work normally, are obtained through measurement respectively. And for the lower limit value which can be borne by the chip to be tested, gradually reducing the target working environment data provided by the device to be tested by taking the adjustment step length as the step length until the communication state between the device to be tested and the chip testing device is changed from normal to abnormal, stopping reducing the target working environment data provided by the device to be tested, determining that the working environment data when the communication state is finally kept normal is the lower limit value which can be borne by the chip to be tested, namely determining that the last working environment data when the communication state is changed to abnormal is the lower limit value which can be borne by the chip to be tested.

The measurement process of the upper limit value which can be borne by the chip to be measured is similar to the measurement process of the lower limit value which can be borne by the chip to be measured, namely, the target working environment data provided by the device to be measured is gradually increased by taking the adjusting step length as the step length until the communication state between the device to be measured and the chip testing device is changed from normal to abnormal, the target working environment data provided by the device to be measured is stopped being increased, the working environment data when the communication state is finally kept normal is determined to be the upper limit value which can be borne by the chip to be measured, namely, the last working environment data when the communication state is changed to abnormal is determined to be the upper limit value which can be borne by the chip to be measured.

In some embodiments of the present application, the adjustment step size may also be adjusted in the process of determining the working environment boundary value of the chip to be tested. When the device to be tested is connected with the chip testing device, the chip testing device firstly adjusts the target working environment data by using a larger step length (which can be called as coarse adjustment), when the communication state between the device to be tested and the chip testing device is changed into abnormal by coarse adjustment, the adjustment step length is reduced, the target working environment data is adjusted into the working environment data of the last moment when the communication state between the device to be tested and the chip testing device is kept normal, the target working environment data at the moment is adjusted again by using the reduced adjustment step length (which can be called as fine adjustment) until the communication state between the device to be tested and the chip testing device is changed into abnormal again, and at the moment, the last working environment data when the communication state indicates abnormal is considered as the working environment boundary value of the chip to be tested.

In some embodiments of the present application, the adjusting process of the adjusting step size may be performed multiple times, that is, each time the communication state between the device to be tested and the chip testing apparatus changes to be abnormal, the adjusting step size is reduced until the adjusting step size reaches the preset threshold step size, and the communication state between the device to be tested and the chip testing apparatus changes to be abnormal again, at this time, the last working environment data when the communication state indicates abnormal is considered as the working environment boundary value of the chip to be tested.

The working environment boundary value of the chip to be tested is confirmed in a coarse adjustment mode, the number of times of adjusting target working environment data can be effectively reduced, the testing efficiency is improved, the working environment boundary value of the chip to be tested is confirmed in a fine adjustment mode on the basis of the coarse adjustment, and the measuring accuracy of the working environment boundary value of the chip to be tested can be improved on the basis of improving the testing efficiency.

In some embodiments of the present application, the chip testing apparatus adjusts the target operating environment data provided by the device under test by sending a driving signal to the device under test, which requires first generating the driving signal, for example, the chip testing apparatus may include a driving signal generating apparatus (e.g., a power control IC and corresponding circuitry) that generates or updates the corresponding driving signal.

Two examples of the drive signal generation apparatus are exemplarily set forth below.

For example, in some embodiments of the present application, when the target operating environment data is an IO voltage (current) of a chip to be tested, the driving signal generating device includes a single chip (this function may also be performed by a processor in the test equipment) dedicated to voltage and current regulation, and the driving signal generating device includes programs such as coarse tuning, fine tuning, and step setting. In some embodiments of the present application, a corresponding coarse tuning program, a fine tuning program, and the like may also be set on the test device.

For example, in some embodiments of the present application, the driving signal generating device is a voltage-current adjustable circuit, which is mainly divided into two types, one is a digital POWER supply circuit (i.e. PWM CONTROLLER + POWER STAGE), and the second is a DC-DC circuit, where the resistance values of the current limiting resistor and the feedback resistor can be adjusted by a dedicated single chip (or a system processor), so as to achieve the adjustment of the voltage and the current.

Step S103: and taking the last working environment data when the communication state indication is abnormal as a working environment boundary value of the chip to be detected.

The following exemplarily sets forth the implementation of S103.

In some embodiments of the present application, when the communication status between the chip testing apparatus and the device under test is changed from normal to abnormal, it indicates that the current working environment data of the chip under test and the working environment boundary value of the chip under test are exceeded, and the chip under test can still work normally under the previous working environment data when the communication status indicates abnormal, and the chip under test can not work normally any more when the communication status indicates abnormal, so that the previous working environment data when the communication status indicates abnormal is the working environment boundary value of the chip under test.

In the chip testing method provided in the first embodiment of the present application, a communication state between the chip testing device and the device to be tested is obtained through the chip testing device, and when the communication state indicates normal, it indicates that a working state of the chip to be tested is also normal, an adjustment step is determined according to a preset adjustment manner, and target working environment data of the chip to be tested in working is updated according to the adjustment step until the adjustment step reaches a preset threshold step, and the communication state indicates abnormal, and when the communication state indicates abnormal, it indicates that the working state of the chip to be tested is also abnormal, that is, it indicates that the current working environment data exceeds a boundary value of working environment data of the chip to be tested in normal working, and the last working environment data when the communication state indicates abnormal is a working environment boundary value of the chip to be tested. Therefore, the boundary value of the working environment data of the chip to be measured is accurately measured.

An embodiment of the present application provides a chip testing method, specifically as shown in fig. 4, including the following steps:

step S201: and acquiring the communication state between the chip testing device and the device to be tested through the chip testing device.

Step S202: and under the condition that the communication state indication is normal, determining an adjusting step length according to a preset adjusting mode, and updating target working environment data according to the adjusting step length until the adjusting step length reaches a preset threshold step length and the communication state indication is abnormal.

Step S203: and taking the last working environment data when the communication state indication is abnormal as a working environment boundary value of the chip to be detected.

It can be understood that steps S201 to S203 in the chip testing method provided in the second embodiment of the present application are substantially the same as steps S101 to S103 in the first embodiment, and specific reference may be made to the detailed description of the foregoing embodiment, which is not repeated herein.

Step S204: and judging whether the upper limit value which can be borne by the chip to be tested is smaller than the value determined when the chip to be tested is under the heat dissipation design power consumption TDP, if so, executing the step S205, and if not, executing the step S206.

The following exemplarily explains the implementation process of S101.

Thermal Design Power (TDP) is used to indicate the maximum amount of heat dissipated a chip may achieve during full load operation. When the chip to be tested is in the TDP state, the chip to be tested corresponds to a value of the working environment data, if the upper limit value that the chip to be tested can bear is greater than or equal to the value of the working environment data determined by the chip to be tested under the TDP, it indicates that the chip to be tested can still normally work under the condition that the target working environment data provided by the device to be tested is higher than the value of the working environment data determined under the TDP, and the power of the chip to be tested under the working environment data exceeds the maximum heat dissipation design power consumption that the chip to be tested can reach, which indicates that the chip to be tested is an abnormal chip, step S206 is executed, otherwise, if the upper limit value that the chip to be tested can bear is less than the value determined by the chip to be tested under the heat dissipation design TDP, it indicates that the chip to be tested is a normal chip, and step S205 is executed.

Step S205: and determining the chip to be tested as a normal chip.

Step S206: and determining the chip to be tested as an abnormal chip.

Compared with the prior art, the chip testing method provided by the second embodiment of the application reserves all the technical characteristics of the first embodiment and has the same technical effects as the first embodiment. In addition, in the second embodiment of the application, the upper limit value that the chip to be tested can bear obtained through measurement is compared with the value of the determined value of the chip to be tested under the heat dissipation design power consumption TDP, and whether the chip to be tested is an abnormal chip is judged, so that whether the chip to be tested is an abnormal chip is further detected.

The third embodiment of the application provides a chip testing device for testing the chip to be tested, when chip testing device tests the chip to be tested, the chip to be tested is carried in the device to be tested, the device to be tested provides operational environment data for the chip to be tested, the chip testing device is specifically as shown in fig. 5, include:

the communication module 601 is used for communicating with the device to be tested, and comprises sending test data to the device to be tested, receiving return data returned by the device to be tested and the like; a communication state obtaining module 602, where the communication state obtaining module 602 is configured to obtain a communication state between the chip testing apparatus and the apparatus to be tested when the chip to be tested works in the target working environment data, that is, the communication state obtaining module 602 is configured to execute step S101 in the first embodiment; the processing module 603, the processing module 603 is configured to determine an adjustment step length according to a preset adjustment manner when the communication status indication is normal, and update the target working environment data according to the adjustment step length until a preset threshold step length is reached and the communication status indication is abnormal; the previous working environment data when the communication status indicates an abnormality is a working environment boundary value of the chip to be tested, that is, the processing module 603 is configured to execute step S102 and step S103 in the first embodiment.

It is to be understood that the chip testing apparatus provided in the third embodiment of the present application is an embodiment of an apparatus corresponding to the chip testing method provided in the first embodiment, and the technical details in the third embodiment of the present application can be applied to the first embodiment, and the technical details in the first embodiment of the present application can also be applied to the third embodiment.

Compared with the prior art, in the chip testing device provided in the third embodiment of the present application, the chip testing device obtains the communication state between itself and the device to be tested through the communication module 601 and the communication state obtaining module 602, when the communication state indicates normal, it indicates that the working state of the chip to be tested is also normal, the processing module 603 determines the adjustment step length according to the preset adjustment mode, and updates the target working environment data of the chip to be tested according to the adjustment step length until the adjustment step length reaches the preset threshold step length, and the communication state indicates abnormal, and when the communication state indicates abnormal, it indicates that the working state of the chip to be tested is also abnormal, that is, it indicates that the current working environment data exceeds the boundary value of the working environment data when the chip to be tested is working normally, and the last working environment data when the communication state indicates abnormal is the working environment boundary value of the chip to be tested. Therefore, the boundary value of the working environment data of the chip to be measured is accurately measured.

Further, in some other embodiments of the present application, as shown in fig. 6, the communication module 601 includes a sending submodule 6011 and a receiving submodule 6012; the sending submodule 6011 is configured to send test data to the device to be tested, and the receiving submodule 6012 is configured to receive return data fed back by the device to be tested; the communication state obtaining module 602 is configured to determine that a communication state with the device under test is normal when the similarity between the test data and the return data is greater than a first threshold, and determine that the communication state with the device under test is abnormal when the similarity between the test data and the return data is less than the first threshold.

An embodiment of the present application provides a chip testing apparatus, as shown in fig. 7, similarly including: the chip testing apparatus further includes a power consumption determining module 604, where the power consumption determining module 604 is configured to determine that the chip to be tested is a normal chip when an upper limit value that the chip to be tested can bear is smaller than a value determined when the chip to be tested is under the thermal design power consumption TDP, and determine that the chip to be tested is an abnormal chip when the upper limit value that the chip to be tested can bear is greater than or equal to the value determined when the chip to be tested is under the thermal design power consumption TDP.

It is to be understood that the chip testing apparatus provided in the fourth embodiment of the present application is an embodiment of an apparatus corresponding to the chip testing method provided in the second embodiment, and the technical details in the fourth embodiment of the present application can be applied to the second embodiment, and the technical details in the second embodiment of the present application can also be applied to the fourth embodiment.

Compared with the prior art, in the chip testing device provided in the fourth embodiment of the present application, the power consumption determining module 604 is arranged to compare the measured upper limit value that can be borne by the chip to be tested with the determined value of the chip to be tested when the chip to be tested is in the heat dissipation design power consumption TDP, and determine whether the chip to be tested is an abnormal chip, thereby further detecting whether the chip to be tested is an abnormal chip.

A fifth embodiment of the present application provides a chip testing system, configured to test a chip to be tested, as shown in fig. 8, where the chip testing system includes a chip testing device 901 and a device to be tested 902 connected to the chip testing device 901, the chip to be tested is mounted in the device to be tested 902, the device to be tested 902 provides working environment data for the chip to be tested, and the chip testing device 901 executes the chip testing method provided in the foregoing embodiment to test the chip to be tested.

Compared with the prior art, the chip testing system provided by the fifth embodiment of the present application includes the chip testing apparatus provided by the foregoing embodiment, and the chip testing method is run in the chip testing apparatus, so that the same technical effects as those of the foregoing embodiment can be obtained, and specific reference can be made to the specific description of the foregoing embodiment.

An embodiment of the present application provides an electronic device, as shown in fig. 9, including: at least one processor 1001; and memory 1002 communicatively coupled to the at least one processor 1001; the memory 1002 stores instructions executable by the at least one processor 1001, and the instructions are executed by the at least one processor 1001 to enable the at least one processor 1001 to execute the chip testing method as described above.

The Memory 1002 may be a Read-Only Memory 1002 (ROM), a Random Access Memory 1002 (RAM), or other memories 1002. In the embodiment of the present application, the memory 1002 is used for storing data and various algorithms and commands, such as an algorithm for determining an IO voltage (current) range in the embodiment of the present application, an entire process, a final result, and the like.

In the illustrated embodiment, memory 1002 may include physical devices for storing information, typically media that can be electronically, magnetically, or optically digitized, and then stored. The memory 1002 of this embodiment may further include: devices that store information using electrical energy, such as RAM, ROM, etc.; devices that store information using magnetic energy, such as hard disks, floppy disks, tapes, core memory 1002, bubble memory 1002, U-disks; devices for storing information optically, such as CDs or DVDs. Of course, there are other ways of memory 1002, such as quantum memory 1002, graphene memory 1002, and the like.

A processor 1001 configured to read the computer program from the memory 1002 and execute the computer program to implement the chip testing method as provided by the foregoing embodiments.

It should be noted that the Processor 1001 may be a Central Processing Unit (CPU), and the Processor 1001 may also be other processors 1001, a Digital Signal Processor 1001 (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, a discrete hardware component, etc. The processor 1001 may be a microprocessor 1001 or the processor 1001 may be any conventional processor 1001 or the like. The processor 1001 may also be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the IO voltage (current) testing method of the present application may be implemented by an integrated logic circuit of hardware in the processor 1001 or by instructions in the form of software.

In some embodiments of the present application, a driving signal generating device 1003 is further included, where the driving signal generating device 1003 is configured to receive a driving signal adjusting instruction sent by the processor 1001 to adjust a driving signal provided to the device under test, and the device under test adjusts, after receiving the driving signal, the working environment data provided for the chip under test according to the driving signal.

For example, in some embodiments of the present application, the operating environment data is an IO voltage or an IO current of the chip, and the driving signal generating device 1003 is an IO voltage (current) control module mainly composed of a power control IC and a corresponding circuit.

The operation of the IO voltage (current) control module is exemplarily described below.

In some embodiments of the present application, after receiving the driving signal adjustment instruction of the processor 1001, the IO voltage (current) control module constructs a driving signal according to the driving signal adjustment instruction, and sends the driving signal to the device under test to control the device under test to correspondingly adjust the IO voltage (current) provided to the chip under test.

In some embodiments of the present application, the driving signal generating device 1003 may also automatically adjust working environment data such as IO voltage (current) provided by the device under test to the chip under test according to a level classified by the processor 1001 in advance.

As shown in fig. 9, in some embodiments of the present application, the electronic device further comprises: a display module 1004 configured to display the drive signal boundary value and/or receive an input drive signal adjustment step value.

It should be noted that, in some embodiments of the present application, the display module is further configured to display contents in the whole process, including a communication state between the device under test and the chip testing device, a similarity value between the return data and the test data, and the like.

The display module 1004 is not limited to various display modes, and may be, for example, a digital tube display or a liquid crystal screen, an LCD, an OLED, or the like. The connection method is not limited, such as IIC, SPI, UART, MIPI, DP, eDP, HDMI, and the like. The module is mainly used for visually displaying the whole test process and the final result.

As shown in fig. 9, in some embodiments of the present application, the electronic device further comprises: a communication interface 1005. Communication interface 1005 enables communication between a chip test device and a device under test using a transceiver device, such as, but not limited to, a transceiver.

Seventh embodiment of the present application provides a computer storage medium, on which a computer program is stored, and the computer program, when executed by a processor, may implement the method of any of the embodiments included in the method of acquiring a driving signal as described above.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as separate products. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

Claims (11)

1. The chip testing method is characterized by being applied to a chip testing system, wherein the chip testing system comprises a chip testing device and a device to be tested, the device to be tested is loaded with a chip to be tested, and the device to be tested is used for providing working environment data for the chip to be tested and establishing communication with the chip testing device under the working environment data; the method comprises the following steps:

acquiring a communication state between the chip testing device and the device to be tested through the chip testing device; the chip to be tested contained in the device to be tested works in target working environment data;

under the condition that the communication state indication is normal, determining an adjustment step length according to a preset adjustment mode, and updating the target working environment data according to the adjustment step length until the adjustment step length reaches a preset threshold step length and the communication state indication is abnormal;

and the last working environment data when the communication state indication is abnormal is the working environment boundary value of the chip to be tested.

2. The method of claim 1, wherein said obtaining, by the chip test device, a communication status between itself and the device under test comprises:

the chip testing device sends testing data to the device to be tested;

the chip testing device receives return data fed back by the device to be tested, determines that the communication state between the chip testing device and the device to be tested is normal under the condition that the similarity between the test data and the return data is larger than a first threshold value, and determines that the communication state between the chip testing device and the device to be tested is abnormal under the condition that the similarity between the test data and the return data is smaller than the first threshold value.

3. The method of claim 1, wherein said updating the target operating environment data according to the adjustment step size comprises:

gradually reducing the target working environment data by taking the adjusting step length as a step length, and under the condition that the adjusting step length reaches a preset step length threshold and the communication state indication is abnormal, determining that the adjusting step length reaches the preset step length threshold and the last working environment data when the communication state indication is abnormal is a lower limit value which can be borne by the chip to be tested;

and with the adjusting step as a step length, gradually increasing the target working environment data, and under the condition that the adjusting step length reaches a preset step length threshold and the communication state indication is abnormal, determining that the last working environment data when the adjusting step length reaches the preset step length threshold and the communication state indication is abnormal is an upper limit value which can be borne by the chip to be tested.

4. The method of claim 3, wherein the method further comprises:

when the upper limit value which can be borne by the chip to be tested is smaller than the value determined when the chip to be tested is under the heat dissipation design power consumption TDP, determining the chip to be tested as a normal chip;

and when the upper limit value which can be borne by the chip to be tested is greater than or equal to the numerical value determined when the chip to be tested is under the heat dissipation design power consumption TDP, determining that the chip to be tested is an abnormal chip.

5. The method of claim 1, wherein the operating environment data is an operating voltage or an operating current of the chip under test.

6. The utility model provides a chip testing arrangement which characterized in that for testing the chip that awaits measuring, the chip that awaits measuring is carried on in the device that awaits measuring, the device that awaits measuring does the chip that awaits measuring provides operational environment data, chip testing arrangement includes:

a communication module for communicating with the device under test;

the communication state acquisition module is used for acquiring the communication state between the chip testing device and the device to be tested when the chip to be tested works in the target working environment data;

the processing module is used for determining an adjusting step length according to a preset adjusting mode under the condition that the communication state indication is normal, and updating the target working environment data according to the adjusting step length until the preset threshold step length is reached and the communication state indication is abnormal; and the last working environment data when the communication state indication is abnormal is the working environment boundary value of the chip to be tested.

7. The apparatus of claim 6, wherein the communication module comprises a transmit sub-module and a receive sub-module;

the sending submodule is used for sending test data to the device to be tested, and the receiving submodule is used for receiving return data fed back by the device to be tested;

the communication state acquisition module is used for determining that the communication state between the communication state acquisition module and the device to be tested is normal under the condition that the similarity between the test data and the return data is greater than a first threshold value, and determining that the communication state between the communication state acquisition module and the device to be tested is abnormal under the condition that the similarity between the test data and the return data is less than the first threshold value.

8. The apparatus of claim 6, wherein the apparatus further comprises:

the power consumption judgment module is used for determining that the chip to be tested is a normal chip when the chip to be tested is in the numerical value determined under the heat dissipation design power consumption TDP, and determining that the chip to be tested is an abnormal chip when the chip to be tested is in the numerical value determined under the heat dissipation design power consumption TDP.

9. A chip testing system for testing a chip under test, the system comprising the chip testing apparatus according to any one of claims 6 to 8 and a device under test communicatively connected to the chip testing apparatus;

the chip to be tested is carried in a device to be tested, and the device to be tested provides working environment data for the chip to be tested.

10. An electronic device, comprising:

at least one processor; and a memory communicatively coupled to the at least one processor;

wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the chip testing method of any one of claims 1 to 5.

11. A computer storage medium on which a computer program is stored, which, when being executed by a processor, is adapted to carry out the chip testing method according to any one of claims 1 to 5.

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