CN115915612A - Substrate structure for embedded device packaging and manufacturing method thereof - Google Patents

Abstract

The application provides an embedded device packaging substrate structure and a preparation method thereof. The manufacturing method of the embedded device packaging substrate structure comprises the following steps: (a) preparing a carrier plate; (b) Forming a via hole penetrating through the bearing plate on the bearing plate; (c) Carrying out hole filling electroplating and surface electroplating on the bearing plate, forming a conducting column in the conducting hole, and respectively forming a first metal layer and a second metal layer on the upper surface and the lower surface of the bearing plate; (d) Performing pattern etching on the upper surface and the lower surface of the bearing plate to form a frame pattern exposing the insulating layer; (e) Laminating a first dielectric layer and a second dielectric layer on the surfaces of the first metal layer and the second metal layer respectively; (f) And cutting along the opening frame pattern to obtain the substrate structure with the opening frame. The method can improve the warping of the substrate, so that the surface of the dielectric layer is smooth, the subsequent circuit layer manufacturing is convenient, and the yield is improved.

Description

Substrate structure for embedded device packaging and manufacturing method thereof

Technical Field

The present disclosure relates to the field of electronic device packaging technologies, and in particular, to a substrate structure for embedded device packaging and a method for manufacturing the same.

Background

The current embedded device packaging substrate is generally prepared by preparing an opening frame in advance, filling a chip or a capacitance and resistance passive device in the opening frame, packaging by using a resin material, and finally performing layer-adding manufacturing.

In the prior art, the most common preparation methods of the mouth frame are divided into three types: firstly, preparing a mouth frame from a Copper Clad Laminate (CCL) in an initial mode; secondly, adopting a coreless (core) process, and using a copper column as an etching channel to prepare an opening frame; thirdly, a metal material (generally copper) is used as a frame, and the mouth frame is prepared through etching or mechanical means.

The scheme of using the CCL as a starting point is to prepare a port frame on the CCL in advance in a mechanical gong or laser mode. The coreless process adopts a method of forming a through copper column on an insulating frame, then pressing a PP (polypropylene) and other dielectric layers, and then grinding a plate to expose the copper column, and then etching off the ring-shaped copper column through selective etching to obtain a mouth frame. Among these methods, the conventional CCL starting scheme easily causes problems such as unevenness and warpage of the entire substrate; the coreless substrate is complex in flow and high in cost, and meanwhile, due to the fact that the thickness is controlled by the grinding plate after the PP is pressed, the glass fibers in the PP are seriously exposed due to the grinding plate, the manufacturing of a follow-up circuit is influenced, and meanwhile, the whole substrate is warped due to the grinding plate, and the follow-up manufacturing is influenced. The mouth frame prepared by adopting the metal frame has the problems of high manufacturing cost, high processing difficulty and the like.

Disclosure of Invention

In view of the above, the present application aims to provide a method for manufacturing a substrate structure starting from a conventional carrier board such as CCL, but without causing problems such as overall unevenness and warpage of the substrate.

In view of the above, the present application provides a method for manufacturing a substrate structure for embedded device package, comprising the following steps:

(a) Preparing a carrier plate comprising an insulating layer;

(b) Forming a through hole penetrating through the bearing plate on the bearing plate;

(c) Carrying out hole filling electroplating and surface electroplating on the bearing plate, forming a conducting column in the conducting hole, and respectively forming a first metal layer and a second metal layer on the upper surface and the lower surface of the bearing plate;

(d) Performing pattern etching on the upper surface and the lower surface of the bearing plate to form an opening frame pattern exposing the insulating layer;

(e) Laminating a first dielectric layer and a second dielectric layer on the surfaces of the first metal layer and the second metal layer respectively;

(f) And cutting along the opening frame pattern to obtain the substrate structure with the opening frame.

The embodiment of the application also provides an embedded device packaging substrate structure, which is prepared by adopting the manufacturing method for the embedded device packaging substrate structure.

As can be seen from the above, the manufacturing method and the substrate structure for embedded device packaging obtained by the manufacturing method can obtain a relatively flat surface of the dielectric layer while forming the opening frame, the opening frame is not easy to warp in the forming process, the operation difficulty and quality risk caused by the warp can be improved, the subsequent circuit layer manufacturing is facilitated, and the yield is improved; meanwhile, the glass fiber exposure in the thinning process can be prevented by using the glass fiber-free dielectric layer. Compared with a coreless process, the method has the advantages of simple process, low cost and the like, and compared with a metal material, the method has the advantages of low manufacturing process difficulty, low cost, high yield and the like.

Drawings

In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for the embodiments or related technologies in the following description are briefly introduced, and it is obvious that the drawings in the following description are only the embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a cross-sectional view of an exemplary embedded device package substrate structure of an embodiment of the present application;

fig. 2 is yet another cross-sectional view of an exemplary embedded device package substrate structure of an embodiment of the present application;

fig. 3a to fig. 3f are schematic cross-sectional views illustrating intermediate structures of steps of a method for manufacturing a substrate structure of a embedded device package according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below with reference to specific embodiments and the accompanying drawings.

It should be noted that technical terms or scientific terms used in the embodiments of the present application should have a general meaning as understood by those having ordinary skill in the art to which the present application belongs, unless otherwise defined. The use of "first," "second," and similar terms in the embodiments of the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

Fig. 1 illustrates a cross-sectional view of an exemplary embedded device package substrate structure of an embodiment of the present application.

As shown in fig. 1, the embedded device package substrate structure provided in the embodiment of the present application may include a package substrate and an opening frame 60 penetrating through the package substrate. Wherein the opening frame 60 is used for embedding an electronic device. The electronic device may be, for example, a chip or the like, and specifically may be an active chip or a passive device or the like. Generally, the number of the opening frames 60 can be determined according to actual requirements, and only one opening frame 60 is included in the following description of the embodiment, but the embedded device package substrate structure is not limited to include only one opening frame 60. The package substrate is initially manufactured by using a carrier board, such as a Copper Clad Laminate (CCL). The copper-clad plate can be a double-sided copper-clad plate and comprises an insulating layer 11 and a first copper layer 12 and a second copper layer 13 which are respectively arranged on the upper surface and the lower surface of the insulating layer 11. The substrate includes an insulating layer, such as an insulating laminate that may be composed of a polymer synthetic resin and a reinforcing material.

The package substrate comprises an insulating layer 11, a first copper layer 12 arranged on the upper surface of the insulating layer 11, a first metal layer 20 arranged on the upper surface of the first copper layer 12, and a first dielectric layer 30 arranged on the upper surface of the first metal layer 20; a second copper layer 13 disposed on a lower surface of the insulating layer 11, and a second metal layer 40 disposed on a lower surface of the second copper layer 13; a conductive via 50 extending through the first metal layer 20, the first copper layer 12, the insulating layer 11, the second copper layer 13, and the second metal layer 40. The opening frame can be formed by laser or mechanical routing of the first opening frame mark 61, the second opening frame mark 62, the third opening frame mark 63, and the fourth opening frame mark 64. The first and second mouth mark 61 and 62 may penetrate the first dielectric layer 30, the first metal layer 20, and the first copper layer 12, respectively, in this order. A third aperture mark 63 and a fourth aperture mark 64 may extend through the second metal layer 40 and the second copper layer 13, respectively, in that order. The insulating layer 11 after the opening frame is formed may have the first opening frame mark 61, the second opening frame mark 62, the third opening frame mark 63, and the fourth opening frame mark 64 (see fig. 2), or may not have the first opening frame mark 61, the second opening frame mark 62, the third opening frame mark 63, and the fourth opening frame mark 64 (see fig. 1).

Fig. 2 illustrates yet another cross-sectional view of an exemplary embedded device package substrate structure of an embodiment of the present application.

In some embodiments, the embedded device package substrate structure may further include a first opening mark 61 and a second opening mark 62 sequentially penetrating through the first dielectric layer 30, the first metal layer 20 and the first copper layer 12, a third opening mark 63 and a fourth opening mark 64 sequentially penetrating through the second metal layer 40 and the second copper layer 13; wherein, the first mouth frame mark 61 and the second mouth frame mark 62 are respectively arranged at two sides of the mouth frame 60; the third and fourth opening frame marks 63 and 64 are respectively provided on both sides of the opening frame 60. Therefore, the embedded device packaging substrate structure has a relatively flat surface, the operation difficulty and quality risk caused by warping are improved, the subsequent circuit layer manufacturing is facilitated, and the yield is improved; the circuit layer is convenient to manufacture subsequently, and the yield is improved.

The first frame mark 61 comprises a first groove which is concave towards the direction vertical to the conductive via 50 and a first dielectric material arranged in the first groove; the second aperture frame mark 62 comprises a second groove which is concave towards the direction vertical to the conductive via 50 and a first dielectric material arranged in the second groove; the third aperture frame mark 63 comprises a third groove which is concave towards the direction vertical to the conductive via 50 and a second dielectric material arranged in the third groove; the fourth bezel mark 64 includes a fourth groove recessed in a direction perpendicular to the conductive via 50 and a second dielectric material disposed in the fourth groove.

In some embodiments, the first and second mouth frame marks 61 and 62 are symmetrically disposed on both sides of the mouth frame 60; and the third opening frame mark 63 and the fourth opening frame mark 64 are symmetrically arranged at both sides of the opening frame 60. Therefore, the flatness of the surface of the embedded device packaging substrate structure can be further improved, the operation difficulty and quality risk caused by warping are further improved, and the yield is further improved.

In some embodiments, the conductive via 50 may be provided in plurality, and the aperture frame 60 may be provided between adjacent conductive vias 50. The conductive via 50 may be specifically a conductive copper via. The conductive copper pillar mentioned in this embodiment may include at least one copper via pillar as an IO channel to achieve conduction between layers, and the size and/or shape of the via pillars may be the same or different; the copper through hole column can be a solid copper column or a hollow column with copper plated on the surface.

Fig. 3a to fig. 3f are schematic cross-sectional views illustrating intermediate structures of steps of a method for manufacturing a substrate structure of a embedded device package according to an embodiment of the present application.

The manufacturing method comprises the following steps: preparation of a Carrier plate-step (a), as shown in FIG. 3 a. The bearing plate can be a copper-clad plate, the copper-clad plate comprises an insulating layer 11, and a first copper layer 12 and a second copper layer 13 are respectively arranged on the upper surface and the lower surface of the insulating layer 11. The thickness of the first copper layer 12 and the second copper layer 13 can be adjusted according to actual requirements. For example, the thicknesses of the first copper layer 12 and the second copper layer 13 may be determined according to the support requirements, the operation requirements, and the like.

Then, a via hole 51 penetrating the carrier plate is formed by performing a hole opening process on the upper surface and the lower surface of the carrier plate, respectively — step (b), as shown in fig. 3 b. In general, the performing of the hole-forming process on the upper surface and the lower surface of the carrier plate, respectively, may include: and drilling the upper surface and the lower surface of the bearing plate through laser. That is, double-sided laser drilling is performed on both sides of the bearing plate. The number of the via holes 51 may be set to at least one to achieve the conduction between the layers. When the number of the via holes 51 is set to be plural, the size and/or shape of the plural via posts may be the same or different; can be generally determined according to actual requirements. The upper surface and the lower surface of the bearing plate can be stressed simultaneously through the double-sided laser opposite drilling, so that the bearing plate is stressed uniformly, the bearing plate is prevented from warping to a certain extent, and the flatness of the laser rear bearing plate is improved. It can be understood that, when the carrier board is a double-sided copper-clad board, the via hole 51 sequentially penetrates through the first copper layer 12, the insulating layer 11 and the second copper layer 13.

Next, forming a first metal layer 20 and a second metal layer 40 on the upper surface and the lower surface of the carrier board, respectively, forming a first opening and a second opening at positions of the first metal layer 20 and the second metal layer 40 opposite to the via hole 51, respectively, and forming a via hole 50 in the via hole 51, the first opening, and the second opening-step (c), as shown in fig. 3 c. Generally this step may comprise:

a first metal layer 20 is formed on the upper surface of the first copper layer 12. The first metal layer 20 may be formed by surface plating in general. A second metal layer 40 is formed on the lower surface of the second copper layer 13. The second metal layer 40 may be formed by surface plating in general.

A first opening is formed in the surface of the first metal layer 20. The first opening may be formed by etching or the like. The position of the first opening corresponds to the position of the via hole 51. It should be understood that the number of first openings corresponds to the number of via holes 51. A second opening is formed in the surface of the second metal layer 40. The second opening may be formed by etching or the like. The position of the second opening corresponds to the position of the via hole 51. It should be understood that the number of second openings corresponds to the number of via holes 51.

A conductive via 50 is formed within the first via hole 51, the first opening, and the second opening. The conductive vias 50 may be formed by way of via-filling plating. The conductive via 50 may be a conductive copper via. When the conductive via 50 is provided in plural, the size and/or shape of the plural through-hole pillars may be the same or different; the copper through hole column can be a solid copper column or a hollow column with copper plated on the surface.

Then, a first and a second opening frame mark patterns 61 'and 62' are formed through the first metal layer 20 and a third and a fourth opening frame mark patterns 63 'and 64' are formed through the second metal layer 40, as shown in fig. 3 d. Generally, the first, second, third, and fourth mask mark patterns 61', 62', 63', and 64' may be formed by etching or the like. The third opening frame mark pattern 63 'is disposed corresponding to the first opening frame mark pattern 61', and the fourth opening frame mark pattern 64 'is disposed corresponding to the second opening frame mark pattern 62'.

In some embodiments, when the conductive vias 50 are provided in plurality, the first and second aperture frame mark patterns 61', 62' are provided between adjacent conductive vias 50, and the third and fourth aperture frame mark patterns 63', 64' are provided between adjacent conductive vias 50. Further, the first aperture frame mark pattern 61 'may be the same distance from the adjacent via 50 as the second aperture frame mark pattern 62' may be from the adjacent via 50; and the third bezel indicia pattern 63 'may be the same distance from the adjacent conductive via 50 as the fourth bezel indicia pattern 64' may be from the adjacent conductive via 50. Therefore, when the opening frame is formed through the subsequent process, the external force applied to the bearing plate is uniform, and the bearing plate is prevented from warping and the like when the opening frame is formed.

It should be understood that the number of the first, second, third and fourth opening frame mark patterns 61', 62', 63 'and 64' is corresponding and may be set to one or more respectively. The number of the mouth frames to be prepared is determined, for example, one mouth frame corresponds to one first mouth frame mark figure 61', one second mouth frame mark figure 62', one third mouth frame mark figure 63 'and one fourth mouth frame mark figure 64'.

Next, a first dielectric layer 30 and a second dielectric layer are laminated on the upper surfaces of the first metal layer 20 and the second metal layer 40, respectively, and a first opening frame mark 61, a second opening frame mark 62, a third opening frame mark 63 and a fourth opening frame mark 64 are formed in the first opening frame mark pattern 61', the second opening frame mark pattern 62', the third opening frame mark 63 'and the fourth opening frame mark 64', respectively-step (e), as shown in fig. 3 e. Typically, the first dielectric layer 30 material is provided within the first aperture frame indicia 61 and the second aperture frame indicia 62, respectively. The third and fourth aperture frame markings 63 and 64, respectively, have a second dielectric layer material therein. The first dielectric layer 30 and the second dielectric layer may be made of glass-fiber-free epoxy resin, so that the first dielectric layer 30, the first opening frame mark 61, the second opening frame mark 62, the second dielectric layer, the third opening frame mark 63, and the fourth opening frame mark 64 may have relatively flat surfaces by laminating the dielectric layers on both sides. The material of the first dielectric layer 30 may or may not be the same as the material of the second dielectric layer. Preferably, the material of the first dielectric layer 30 is the same as that of the second dielectric layer, so that the uniformity of the bearing plate surface stress during the fabrication of the opening frame can be better improved.

In some embodiments, the material of the first dielectric layer 30 may be an ajinomoto resin (ABF) or a photosensitive resin (PID), and the material may be selected according to different requirements. The material of the second dielectric layer may be ajinomoto resin (ABF) or photosensitive resin (PID), and different materials may be selected according to different requirements.

And then, thinning the second dielectric layer to expose the surface of the second metal layer 40, step (g), as shown in fig. 3 f. Typically, the second dielectric layer can be thinned entirely by lapping, plasma etching or sandblasting to expose the second metal layer 40. In some embodiments, the first dielectric layer 30 may be subjected to a surface roughening treatment to improve the bonding strength between the first dielectric layer 30 and a subsequently fabricated hierarchical structure (e.g., a circuit layer), etc., so as to facilitate the subsequent fabrication of the hierarchical structure.

It should be understood that step (g) may not be performed, and thus subsequent layers (e.g., wiring layers) and the like may be formed on the surfaces of the first dielectric layer 30 and the second dielectric layer, respectively.

Next, an opening frame 60 is cut along the first opening frame mark 61, the second opening frame mark 62, the third opening frame mark 63 and the fourth opening frame mark 64, step (f), as shown in fig. 1 or fig. 2. Generally, a mouth frame can be prepared by laser or mechanical drilling and milling, and the like, and is prepared for embedding a chip subsequently, so as to form the structure shown in fig. 2. In some embodiments, the opening frames may be cut along the middle portions of the first opening frame mark 61, the second opening frame mark 62, the third opening frame mark 63 and the fourth opening frame mark 64, respectively, so as to further improve the stress uniformity of the package substrate during the cutting process.

Then, it is also possible to embed an electronic device in the opening frame, perform insulating layer encapsulation, and form a wiring layer and the like on the first dielectric layer 30. The aperture frame is capable of exposing the insulating layer.

The embedded device packaging substrate structure and the preparation method thereof provided by the embodiment of the application use CCL for initiation, laser is used for filling holes after drilling and electroplating to form the upper and lower conducting holes 51, then the upper and lower layer opening frame mark patterns are made, then the resin medium layer without glass fibers is pressed on the patterns, the double-sided pressing medium layer can obtain relatively flat finished products, the operation difficulty and quality risk caused by warping are improved, meanwhile, the resin layer without glass fibers on the surface can ensure the surface smoothness, the subsequent circuit layer manufacturing is convenient, and the yield is improved. And the laser drilling and hole filling electroplating is adopted, so that the manufacturing process of the coreless substrate is reduced, and the benefit is improved. Through the resin medium layer without glass fiber on the surface, the PP glass fiber exposure problem after board grinding is improved, and the line yield is improved. By CCL initiation, board warpage issues can be improved without the use of machine milling to control thickness.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the context of the present application, technical features in the above embodiments or in different embodiments may also be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application described above, which are not provided in detail for the sake of brevity.

In addition, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown in the provided figures for simplicity of illustration and discussion, and so as not to obscure the embodiments of the application. Furthermore, devices may be shown in block diagram form in order to avoid obscuring embodiments of the application, and this also takes into account the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the embodiments of the application are to be implemented (i.e., specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the application, it should be apparent to one skilled in the art that the embodiments of the application can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative instead of restrictive.

While the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures, such as Dynamic RAM (DRAM), may use the discussed embodiments.

The present embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present application are intended to be included within the scope of the present application.

Claims (8)

1. A method for manufacturing a substrate structure for embedded device packaging is characterized by comprising the following steps:

(a) Preparing a carrier plate comprising an insulating layer;

(b) Forming a via hole penetrating through the bearing plate on the bearing plate;

(c) Carrying out hole filling electroplating and surface electroplating on the bearing plate, forming a conducting column in the conducting hole, and respectively forming a first metal layer and a second metal layer on the upper surface and the lower surface of the bearing plate;

(d) Performing pattern etching on the upper surface and the lower surface of the bearing plate to form a frame pattern exposing the insulating layer of the bearing plate;

(e) Laminating a first dielectric layer and a second dielectric layer on the surfaces of the first metal layer and the second metal layer respectively;

(f) And cutting along the opening frame pattern to obtain the substrate structure with the opening frame.

2. The method of claim 1, wherein step (b) further comprises: and simultaneously drilling the upper surface and the lower surface of the bearing plate by laser or mechanical drilling to form the through hole.

3. The method of claim 1, wherein the first dielectric layer and the second dielectric layer are selected from fiberglass-free insulating materials so that the cut frame has a flat surface.

4. A method according to claim 3, wherein the fiberglass-free insulating material is selected from ABF resins or photosensitive resins.

5. The method of claim 3, further comprising, after step (e) and before step (f), the steps of:

and thinning the second dielectric layer to expose the second metal layer.

6. The method according to claim 1, wherein in step (a), the carrier plate is a double-sided copper-clad plate comprising a first copper layer and a second copper layer respectively covering the upper surface and the lower surface of the insulating layer.

7. The method of claim 1, further comprising:

and forming a circuit layer on the first dielectric layer.

8. A substrate structure for embedded device packaging, wherein the substrate is prepared by the method of any one of claims 1-7.

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