CN115913435A - Clock real-time synchronization device and method - Google Patents

Abstract

The invention provides a clock real-time synchronization device and a method, wherein the clock real-time synchronization device is applied to chip test equipment and comprises the following steps: the synchronization module receives a pulse per second signal sent by the signal transceiver module and the first clock signal sent by the clock source module respectively, the frequency precision of the pulse per second signal is consistent with that of the pulse signal sent by the global navigation satellite system, and the first clock signal is a local clock signal of the chip testing equipment; the control module is used for controlling the synchronization module to perform synchronization processing on the first clock signal and the second pulse signal by taking the second pulse signal as a reference, and controlling the synchronization module to generate a second clock signal according to a synchronization processing result, wherein the second clock signal is used as a reference clock signal of the chip testing equipment. The invention solves the technical problems of higher cost, complex system and low clock source precision in the prior art for calibrating the clock of the chip testing equipment.

Description

Clock real-time synchronization device and method

Technical Field

The invention relates to the technical field of chip test equipment, in particular to a clock real-time synchronization device and method.

Background

The high-precision high-stability clock system is the basis for realizing accurate test of the chip test equipment, and can provide a multi-path clock with high-precision high-stability, low noise and low phase difference for various test units in the chip test equipment.

The frequency precision and the phase precision of a clock system of the traditional chip testing equipment mainly depend on the basic characteristics of a clock source inside the chip testing equipment, and the clock synchronization of various testing modules inside the chip testing equipment is realized through the traditional phase-locked loop technology.

Based on the clock system and the synchronization principle of the traditional chip test equipment, the following problems can be seen:

1) The cost is high, and the frequency offset of the basic clock of the chip testing equipment is continuously increased and the precision is continuously deteriorated due to the characteristics that an ordinary clock source can drift along with the temperature and continuously age along with the time. Therefore, the conventional chip test equipment needs to calibrate the basic clock regularly (usually once calibration in half a year), that is, firstly, a special external measuring instrument detects the clock error on the chip test equipment, and then, the conventional chip test equipment is subjected to frequency error adjustment processing according to the measured error until the frequency error is adjusted to be within the allowable frequency error range, otherwise, the test result of the chip test system is inaccurate, and the cost for purchasing and configuring the special measuring instrument and the test time is increased simultaneously in the regular calibration.

2) The system for calibration is complex to adjust or compensate for the frequency offset of the clock source caused by temperature drift and aging over time.

3) The clock source precision is not high, and the clock system is an independently operated clock system, the clock precision of the clock system only depends on the clock source precision of the chip testing equipment, the precision is not high, and the clock system cannot be synchronized with a clock with higher precision so as to improve the precision and the stability of the clock system of the chip testing equipment.

Therefore, the present invention provides a real-time clock synchronization apparatus and method to solve the above technical problems.

Disclosure of Invention

The invention provides a clock real-time synchronization device and a clock real-time synchronization method, which are used for solving the technical problems in the prior art that the cost for calibrating a clock of chip test equipment is higher, a used system is complex, and the clock source precision is not high.

In a first aspect, the present invention provides a real-time clock synchronization device applied to a chip test apparatus, including: the clock source module comprises a signal transceiving module, a clock source module, a synchronization module and a control module; the signal transceiver module is used for acquiring a pulse per second signal, and transmitting the pulse per second signal to the synchronization module, wherein the frequency precision of the pulse per second signal is consistent with that of a pulse signal transmitted by a global navigation satellite system; the clock source module is used for generating a first clock signal and transmitting the first clock signal to the synchronization module, wherein the first clock signal is a local clock signal of the chip test equipment; the synchronization module receives the pulse per second signal sent by the signal transceiver module and the first clock signal sent by the clock source module respectively; the control module is used for controlling the synchronization module to perform synchronization processing on the first clock signal and the pulse per second signal by taking the pulse per second signal as a reference, and controlling the synchronization module to generate a second clock signal according to a result of the synchronization processing, wherein the second clock signal is used as a reference clock signal of the chip testing equipment.

The beneficial effects are that: according to the invention, by acquiring the pulse-per-second signal with frequency precision consistent with the pulse signal transmitted by the global navigation satellite system, the clock signal of the chip testing equipment can be synchronously processed by the clock signal with ultrahigh precision, so that the precision of the clock source of the chip testing equipment is greatly improved; according to the invention, the control module is used for controlling the synchronization module to perform synchronization processing on the first clock signal and the second pulse signal by taking the second pulse signal as a reference, and controlling the synchronization module to generate the second clock signal according to the result of the synchronization processing, namely, the invention can finish the improvement of the precision of the clock signal of the chip testing equipment and reduce the cost without externally connecting a special testing instrument to measure the clock deviation of the chip testing equipment and directly generating the second clock signal according to the automatic result of the real-time synchronization processing; the structure required by the invention is simpler.

Optionally, the clock real-time synchronization apparatus further includes: the clock distribution module is used for receiving the second clock signal output by the synchronization module and generating a plurality of sub-clock signals according to the second clock signal; and the clock distribution module is further used for reducing the jitter of the sub-clock signals relative to the second clock signal and reducing the phase difference among a plurality of the sub-clock signals to generate the third clock signal, and the third clock signal is used as a working clock signal of the chip testing equipment. The beneficial effects are that: since jitter is inevitably generated during the multi-path distribution of the clock signals, the present invention further ensures the accuracy and phase consistency of the multi-path output clock signals by providing the jitter suppressing unit.

Optionally, the clock distribution module includes: at least one of a multi-output ultra-low additional jitter differential clock buffer and a multi-output low noise clock jitter canceller. The beneficial effects are that: the clock distribution module comprises at least one of a multi-output ultra-low additional jitter differential clock buffer and a multi-output low-noise clock jitter eliminator, so that the multi-path distribution of clock signals has ultra-low additional jitter performance, and the phase difference between the multi-path output clock signals is small.

Optionally, an average frequency jitter of the sub-clock signals with respect to the second clock signal is less than 51fs, and a phase difference between several of the second sub-clock signals is less than 120ps. The beneficial effects are that: and ensuring that the subsequently generated jitter of the third clock signal is in an ultralow range and the phase difference is small.

Optionally, the synchronization module comprises a digital phase locked loop circuit and a frequency divider circuit; the control module regulates and controls the digital phase-locked loop circuit to perform automatic phase tracking and locking on the first clock signal and the pulse per second signal so as to synchronize the first clock signal and the pulse per second signal in real time; and configuring the output frequency divider circuit through the control module to regulate and control the frequency of the first clock signal synchronized with the pulse per second signal to a target set frequency so as to generate the second clock signal. The beneficial effects are that: so as to effectively generate the second clock signal and ensure that the frequency precision of the second clock signal is consistent with the pulse per second signal.

Optionally, the synchronization module further includes a determining unit, where the determining unit is configured to determine whether the first clock signal is consistent with the phase of the pulse per second signal, and if so, the digital phase-locked loop circuit is in a phase-hold state, and the determining unit sends a first control instruction to the control module, where the first control instruction is used to enable the control module to not operate, and use the first clock signal as a reference clock signal of the chip testing device; if the clock signals are inconsistent with the first clock signals, the judging unit sends a second control instruction to the control module, and the second control instruction is used for enabling the control module to control the synchronization module to generate the second clock signals. The beneficial effects are that: the processing efficiency is saved. If the first clock signal meets the requirement, a second clock signal does not need to be generated so as to save the flow, otherwise, the second clock signal needs to be generated so as to improve the detection precision.

Optionally, the signal transceiver module includes a gnss receiving circuit, and the gnss receiving circuit is provided with a gnss receiving chip; the global navigation satellite system receiving chip is used for receiving a time signal sent by a global navigation satellite system, demodulating the time signal, and acquiring a time coordinate carried by the time signal, ground positioning information and position information of the global navigation satellite system so as to generate the pulse per second signal with frequency accuracy consistent with that of the time signal. The beneficial effects are that: by the aid of the receiving circuit of the global navigation satellite system, the precision of the generated pulse per second signal is consistent with that of the global navigation satellite system, ultra-high precision of the pulse per second signal is guaranteed, and frequency precision is better than 1Hz +/-1E-12.

Optionally, the frequency accuracy of the pulse per second signal is 1Hz + -1E-12.

Optionally, the clock source module includes a constant temperature crystal oscillator circuit, and a clock frequency precision range of the constant temperature crystal oscillator circuit is 10MHz ± 2E-7. The beneficial effects are that: the precision and the stability of the clock source module can be improved and the initial precision of the clock source module can be ensured to be in a higher precision range by arranging the constant temperature crystal oscillator circuit; and the daily aging rate of the clock of the constant temperature crystal oscillator circuit is +/-5E-10, the annual aging rate is +/-1E-7, and the clock can be in a high-precision and high-stability range even in the abnormal loss state of the pulse per second signal.

In a second aspect, the present invention provides a clock real-time synchronization method applied to the clock real-time synchronization apparatus according to any one of the first aspect, including: providing a signal receiving and transmitting module, a clock source module, a synchronization module and a control module; the signal transceiver module acquires a pulse per second signal, and transmits the pulse per second signal to the synchronization module, wherein the frequency precision of the pulse per second signal is consistent with that of a pulse signal transmitted by a global navigation satellite system; the clock source module generates a first clock signal and transmits the first clock signal to the synchronization module, wherein the first clock signal is a local clock signal of the chip test equipment; the synchronization module receives the pulse-per-second signal sent by the signal transceiver module and the first clock signal sent by the clock source module respectively; the control module controls the synchronization module to perform synchronization processing on the first clock signal and the second pulse signal by taking the second pulse signal as a reference, and controls the synchronization module to generate a second clock signal according to a result of the synchronization processing, wherein the second clock signal is used as a reference clock signal of the chip testing equipment.

The beneficial effects are that: according to the invention, by acquiring the pulse-per-second signal with frequency precision consistent with the pulse signal transmitted by the global navigation satellite system, the clock signal of the chip testing equipment can be synchronously processed by the clock signal with ultrahigh precision, so that the precision of the clock source of the chip testing equipment is greatly improved; according to the invention, the control module is used for controlling the synchronization module to perform synchronization processing on the first clock signal and the second pulse signal by taking the second pulse signal as a reference, and controlling the synchronization module to generate the second clock signal according to the result of the synchronization processing, namely, the deviation of a clock in the chip test equipment is measured without an external special measuring instrument, and the second clock signal is automatically generated directly according to the result of real-time synchronization processing, so that the improvement of the precision of the clock signal of the chip test equipment can be completed, and the cost is reduced; the structure required by the invention is simpler.

Drawings

Fig. 1 is a schematic structural diagram of an embodiment of a real-time clock synchronization apparatus provided in the present invention;

FIG. 2 is a schematic structural diagram of another embodiment of a real-time clock synchronization apparatus according to the present invention;

FIG. 3 is a flowchart of an embodiment of a method for real-time clock synchronization according to the present invention;

fig. 4 is a schematic structural diagram of a terminal according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present application are described below with reference to the drawings in the embodiments of the present application. In the description of the embodiments of the present application, the terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in the specification of this application and the appended claims, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, such as "one or more", unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" means one or more than two (including two). The term "and/or" is used to describe an association relationship that associates objects, meaning that three relationships may exist; for example, a and/or B, may represent: a alone, both A and B, and B alone, where A, B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather mean "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise. The term "coupled" includes both direct and indirect connections, unless otherwise noted. "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

In the embodiments of the present application, words such as "exemplary" or "for example" are used to mean serving as examples, illustrations or descriptions. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

The invention provides a clock real-time synchronization device and a clock real-time synchronization method, which are used for solving the technical problems in the prior art that the cost for calibrating a clock of chip test equipment is higher, a used system is complex, and the clock source precision is not high. The invention provides a clock real-time synchronization device, which is applied to chip test equipment and comprises the following components as shown in figure 1: the clock source module 102, the signal transceiver module 101, the synchronization module 103 and the control module 104; the signal transceiver module 101 is configured to acquire a pulse per second signal, and transmit the pulse per second signal to the synchronization module 103, where frequency accuracy of the pulse per second signal is consistent with frequency accuracy of a pulse signal transmitted by a global navigation satellite system; the clock source module 102 is configured to generate a first clock signal, and transmit the first clock signal to the synchronization module 103, where the first clock signal is a local clock signal of the chip testing apparatus; the synchronization module 103 receives the pulse-per-second signal sent by the signal transceiver module 101 and the first clock signal sent by the clock source module 102, respectively; the control module 101 is configured to control the synchronization module 103 to perform synchronization processing on the first clock signal and the pulse-per-second signal with reference to the pulse-per-second signal, and control the synchronization module 103 to generate a second clock signal according to a result of the synchronization processing, where the second clock signal is used as a reference clock signal of the chip testing apparatus.

In the present embodiment, the frequency accuracy of the pulse-per-second signal is ultra-high accuracy, which means an accuracy of less than 1 Hz. + -. 1E-12. According to the embodiment, the second pulse signal with the frequency precision consistent with the pulse signal transmitted by the global navigation satellite system is obtained, so that the clock signal of the chip testing equipment can be synchronously processed by the clock signal with ultrahigh precision, and the precision of the clock source of the chip testing equipment is greatly improved; according to the invention, the control module is used for controlling the synchronization module to perform synchronization processing on the first clock signal and the second pulse signal by taking the second pulse signal as a reference, and controlling the synchronization module to generate the second clock signal according to the result of the synchronization processing, namely, the second clock signal is generated directly according to the result of the synchronization processing without measuring the deviation of a clock in the chip testing equipment, so that the precision of the clock signal of the chip testing equipment can be improved, and the cost is reduced; the structure required by the invention is simpler.

In some embodiments, the control module is connected to the synchronization module via a communication connection circuit, the communication connection circuit is a serial peripheral interface, and the serial peripheral interface is a full-duplex, synchronous communication bus.

In some embodiments, as shown in fig. 2, the clock real-time synchronization apparatus further includes: the clock distribution module 201, where the clock distribution module 201 is configured to receive the second clock signal output by the synchronization module, and generate a plurality of sub-clock signals according to the second clock signal; and the clock distribution module is further used for reducing the jitter of the sub-clock signals relative to the second clock signal and reducing the phase difference among a plurality of the sub-clock signals to generate the third clock signal, and the third clock signal is used as a working clock signal of the chip testing equipment. The beneficial effects are that: since jitter is inevitably generated during the multi-path distribution of the clock signal, the present invention further ensures the accuracy of the clock signal by providing the jitter suppressing unit.

In some embodiments, the clock distribution module comprises: at least one of a multi-output ultra-low additional jitter differential clock buffer and a multi-output low noise clock jitter canceller. The multiplexed output ultra-low additional jitter differential clock buffer is also called a level shifter. The beneficial effects are that: the clock distribution module comprises at least one of a multi-output ultra-low additional jitter differential clock buffer and a multi-output low-noise clock jitter eliminator, so that the multi-path distribution of the clock signals has ultra-low additional jitter performance, and the phase difference between the multi-path output clock signals is small.

In some embodiments, under the action of the jitter suppressing unit, the average frequency jitter of the sub-clock signals relative to the second clock signal is less than 51fs, the jitter amplitude is 12 kHz-20 MHz, and the phase difference among a plurality of sub-clock signals is less than 120ps. The beneficial effects are that: and ensuring that the jitter of the third clock signal is in an ultra-low range and the phase difference is small.

In some embodiments, the synchronization module includes a Digital Phase Locked Loop (DPLL) circuit and a frequency divider circuit; the digital phase-locked loop circuit is regulated and controlled by the control module, and automatic phase tracking and locking are carried out on the first clock signal and the pulse per second signal, so that the first clock signal and the pulse per second signal are synchronized in real time; and configuring the output frequency divider circuit through the control module to regulate and control the frequency of the first clock signal synchronized with the pulse per second signal to a target set frequency so as to generate the second clock signal. The beneficial effects are that: so as to effectively generate the second clock signal and ensure that the frequency precision of the second clock signal is consistent with the second pulse signal.

In some embodiments, the synchronization module further includes a determining unit, where the determining unit is configured to determine whether the first clock signal is consistent with the phase of the pulse per second signal, and if so, the digital phase-locked loop circuit is in a phase-hold state, and the determining unit sends a first control instruction to the control module, where the first control instruction is used to enable the control module to not operate and use the first clock signal as a reference clock signal of the chip testing device; if the clock signals are inconsistent with the first clock signals, the judging unit sends a second control instruction to the control module, and the second control instruction is used for enabling the control module to control the synchronization module to generate the second clock signals. The beneficial effects are that: the processing efficiency is saved. If the first clock signal meets the requirement, a second clock signal does not need to be generated so as to save the flow, otherwise, the second clock signal needs to be generated so as to improve the detection precision.

In some embodiments, the signal transceiver module comprises a gnss receiving circuit, which is provided with a gnss receiving chip; the global navigation satellite system receiving chip is used for receiving a time signal sent by a global navigation satellite system, demodulating the time signal, and acquiring a time coordinate carried by the time signal, ground positioning information and position information of the global navigation satellite system so as to generate the pulse per second signal with frequency accuracy consistent with that of the time signal. The beneficial effects are that: by the aid of the receiving circuit of the global navigation satellite system, the precision of the generated pulse per second signal is consistent with that of the global navigation satellite system, ultra-high precision of the pulse per second signal is guaranteed, and frequency precision is better than 1Hz +/-1E-12. The ground positioning information refers to the position information of the satellite used for transmitting the time signal in the global navigation satellite system, which corresponds to the earth, and the position information of the global navigation satellite system refers to the precise position of the satellite used for transmitting the time signal in space at each moment.

In some embodiments, the frequency accuracy of the pulse-per-second signal is 1Hz + -1E-12.

In some embodiments, the clock source module includes an Oven-Controlled Crystal Oscillator (OCXO) circuit having an initial clock frequency accuracy in a range of 10MHz + -2E-7. Optionally, the clock daily aging rate of the constant-temperature crystal oscillator circuit is +/-5E-10, and the annual aging rate of the constant-temperature crystal oscillator circuit is +/-1E-7. The beneficial effects are that: through setting up the constant temperature crystal oscillator circuit can improve the precision and the stability of clock source module, can guarantee that the initial precision of clock source module is in higher precision range. The clock daily aging rate and the annual aging rate of the constant-temperature crystal oscillator circuit are respectively +/-5E-10 and +/-1E-7, so that the constant-temperature crystal oscillator circuit can be in a high-precision and high-stability range even in the abnormal loss state of the pulse per second signal.

In some embodiments, the lock mode comprises a phase-locked loop lock mode. The beneficial effects are that: so as to effectively complete the phase tracking of the first clock signal and the pulse per second signal.

In some embodiments, the digital phase locked loop circuit includes a lock register and the divider circuit includes a divider register. The beneficial effects are that: the second clock signal can be generated efficiently.

In some embodiments, the digital phase-locked loop circuit includes a loop filter, a frequency bandwidth of the loop filter is an adjustable parameter, and the frequency bandwidth of the loop filter ranges from 12 μ Hz to 22kHz. The beneficial effects are that: the invention ensures the frequency precision of the clock signal, and the required frequency bandwidth of the loop filter is smaller. Optionally, the frequency bandwidth of the loop filter is 12 μ Hz.

In some embodiments, the clock output frequency of the digital phase-locked loop circuit ranges from 0.5Hz to 1GHz, the average clock jitter of the digital phase-locked loop circuit is greater than or equal to 0 and less than 150fs, and the jitter amplitude ranges from 10kHz to 20MHz. The beneficial effects are that: the digital phase-locked loop circuit has the advantages of higher clock output frequency adjusting capability and smaller jitter.

Based on the clock real-time synchronization apparatus described in any of the above embodiments, the present invention further provides a clock real-time synchronization method, a flow of which is shown in fig. 3, including:

s301: providing a signal receiving and transmitting module, a clock source module, a synchronization module and a control module;

s302: the signal transceiver module acquires a pulse per second signal, and transmits the pulse per second signal to the synchronization module, wherein the frequency precision of the pulse per second signal is consistent with that of a pulse signal transmitted by a global navigation satellite system;

s303: the clock source module receives a first clock signal and transmits the first clock signal to the synchronization module, wherein the first clock signal is a local clock signal of the chip test equipment;

s304: the synchronization module receives the pulse-per-second signal sent by the signal transceiver module and the first clock signal sent by the clock source module respectively;

s305: the control module controls the synchronization module to perform synchronization processing on the first clock signal and the second pulse signal by taking the second pulse signal as a reference, and controls the synchronization module to generate a second clock signal according to a result of the synchronization processing, wherein the second clock signal is used as a reference clock signal of the chip testing equipment.

The beneficial effects are that: according to the invention, by acquiring the pulse per second signal with the frequency precision consistent with the pulse signal transmitted by the global navigation satellite system, the clock signal of the chip testing equipment can be synchronously processed by the clock signal with ultra-high precision, so that the precision of the clock source of the chip testing equipment is greatly improved; according to the invention, the control module is used for controlling the synchronization module to perform synchronization processing on the first clock signal and the second pulse signal by taking the second pulse signal as a reference, and controlling the synchronization module to generate the second clock signal according to the result of the synchronization processing, namely, the accuracy of the clock signal of the chip testing equipment can be improved and the cost is reduced without measuring the deviation of the clock in the chip testing equipment and directly generating the second clock signal according to the result of the synchronization processing; the structure required by the invention is simpler.

All relevant contents of the steps related to the method embodiment may be referred to the functional description of the corresponding unit module, and are not described herein again.

In other embodiments of the present application, an embodiment of the present application discloses a terminal, as shown in fig. 4, where the terminal may refer to the clock real-time synchronization apparatus in the foregoing embodiment, and the terminal may include: one or more processors 401; a memory 402; a display 403; one or more application programs (not shown); and one or more computer programs 404, which may be connected via one or more communication buses 405. Wherein the one or more computer programs 404 are stored in the memory 402 and configured to be executed by the one or more processors 401, the one or more computer programs 404 comprising instructions which may be used to perform the steps of the respective embodiments described above.

Through the above description of the embodiments, it is clear to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional modules is merely used as an example, and in practical applications, the above function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device may be divided into different functional modules to complete all or part of the above described functions. For the specific working processes of the system, the apparatus and the unit described above, reference may be made to the corresponding processes in the foregoing method embodiments, and details are not described here again.

Each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) or a processor to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: flash memory, removable hard drive, read only memory, random access memory, magnetic or optical disk, and the like.

The above description is only a specific implementation of the embodiments of the present application, but the scope of the embodiments of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the embodiments of the present application should be covered by the scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A real-time clock synchronization device is applied to chip test equipment and comprises: the clock source module comprises a signal transceiving module, a clock source module, a synchronization module and a control module;

the signal transceiver module is used for acquiring a pulse per second signal, and transmitting the pulse per second signal to the synchronization module, wherein the frequency precision of the pulse per second signal is consistent with that of a pulse signal transmitted by a global navigation satellite system;

the clock source module is used for generating a first clock signal and transmitting the first clock signal to the synchronization module, wherein the first clock signal is a local clock signal of the chip test equipment;

the synchronization module receives the pulse-per-second signal sent by the signal transceiver module and the first clock signal sent by the clock source module respectively;

the control module is used for controlling the synchronization module to perform synchronization processing on the first clock signal and the pulse per second signal by taking the pulse per second signal as a reference, and controlling the synchronization module to generate a second clock signal according to a result of the synchronization processing, wherein the second clock signal is used as a reference clock signal of the chip testing equipment.

2. The device for real-time clock synchronization according to claim 1, further comprising: the clock distribution module is used for receiving the second clock signal output by the synchronization module and generating a plurality of sub-clock signals according to the second clock signal;

and the clock distribution module is further used for reducing the jitter of the sub-clock signals relative to the second clock signal and reducing the phase difference among a plurality of the sub-clock signals to generate the third clock signal, and the third clock signal is used as a working clock signal of the chip testing equipment.

3. The clock real-time synchronization apparatus of claim 2, wherein the clock distribution module comprises: at least one of a multi-output ultra-low additional jitter differential clock buffer and a multi-output low noise clock jitter canceller.

4. The apparatus according to claim 2, wherein an average frequency jitter of the sub-clock signals with respect to the second clock signal is less than 51fs, and a phase difference between a number of the sub-clock signals is less than 120ps.

5. The clock real-time synchronization apparatus of claim 1, wherein the synchronization module comprises a digital phase-locked loop circuit and an output frequency divider circuit;

the digital phase-locked loop circuit is regulated and controlled by the control module, and automatic phase tracking and locking are carried out on the first clock signal and the pulse per second signal, so that the first clock signal and the pulse per second signal are synchronized in real time;

and configuring the output frequency divider circuit through the control module to regulate and control the frequency of the first clock signal synchronized with the second pulse signal to a target set frequency so as to generate the second clock signal.

6. The device according to claim 5, wherein the synchronization module further comprises a determining unit, the determining unit is configured to determine whether the first clock signal is in accordance with the phase of the pulse per second signal, if so, the digital phase-locked loop circuit is in a phase-hold state, the determining unit sends a first control instruction to the control module, and the first control instruction is configured to enable the control module to be inoperative and use the first clock signal as a reference clock signal of the chip testing apparatus; if the clock signals are inconsistent with the first clock signals, the judging unit sends a second control instruction to the control module, and the second control instruction is used for enabling the control module to control the synchronization module to generate the second clock signals.

7. The device for real-time clock synchronization according to claim 1, wherein the signal transceiver module comprises a gnss receiver circuit, and the gnss receiver circuit is provided with a gnss receiver chip;

the global navigation satellite system receiving chip is used for receiving a time signal sent by a global navigation satellite system, demodulating the time signal, and acquiring a time coordinate carried by the time signal, ground positioning information and position information of the global navigation satellite system so as to generate the pulse per second signal with frequency accuracy consistent with that of the time signal.

8. The device for real-time synchronization of clocks according to claim 1, wherein said pulse-per-second signal has a frequency accuracy of 1Hz ± 1E "12.

9. The device according to claim 1, wherein the clock source module comprises a constant temperature crystal oscillator circuit, and the initial clock frequency precision range of the constant temperature crystal oscillator circuit is 10MHz ± 2E-7.

10. A method for real-time clock synchronization, applied to the clock real-time synchronization apparatus according to any one of claims 1-9, comprising: providing a signal receiving and transmitting module, a clock source module, a synchronization module and a control module;

the signal receiving and transmitting module acquires a pulse per second signal, and transmits the pulse per second signal to the synchronization module, wherein the frequency precision of the pulse per second signal is consistent with that of a pulse signal transmitted by a global navigation satellite system;

the clock source module generates a first clock signal and transmits the first clock signal to the synchronization module, wherein the first clock signal is a local clock signal of the chip test equipment;

the synchronization module receives the pulse per second signal sent by the signal transceiver module and the first clock signal sent by the clock source module respectively;

the control module controls the synchronization module to perform synchronization processing on the first clock signal and the second pulse signal by taking the second pulse signal as a reference, and controls the synchronization module to generate a second clock signal according to a result of the synchronization processing, wherein the second clock signal is used as a reference clock signal of the chip testing equipment.

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