CN115913224A - Voltage modulation column level single-slope analog-to-digital converter - Google Patents
Voltage modulation column level single-slope analog-to-digital converter Download PDFInfo
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Abstract
The invention discloses a voltage modulation column-level monoclinic analog-to-digital converter, which relates to the technical field of analog-to-digital converters and comprises a bias power supply, a ramp generator, a first capacitor circuit, a second capacitor circuit, a first inverter, a reset switch, an N-bit counter and an N-bit register, wherein N is a positive integer. The invention realizes the comparator in the column-level single-slope analog-to-digital converter through the phase inverter structure, when the comparator does not consume current any more after being turned over, the power consumption of each circuit is low, compared with the traditional operational amplifier type comparator, the power consumption of each circuit is reduced, the structure is simple, and the power consumption reduction effect is more obvious along with the increase of the pixel array.
Description
Technical Field
The invention relates to the technical field of analog-to-digital converters, in particular to a voltage modulation column-level single-slope analog-to-digital converter.
Background
A low-power consumption CMOS image sensor is a core technology for acquiring and transmitting visual information needing battery power supply in the fields of Internet of things, 5G mobile terminal equipment, artificial intelligence and the like. At present, the CMOS image sensor mainly adopts a column parallel architecture, and a main power consumption source of the column parallel architecture is a core module column-level analog-to-digital converter (ADC). There are four column level ADCs in common use: the CMOS image sensor comprises a monoclinic ADC, a cyclic ADC, a successive approximation ADC and an incremental modulation ADC, wherein each column of the monoclinic ADC only comprises one comparator and one counter, and the power consumption is the lowest, so that the low-power-consumption CMOS image sensor is widely in a column-level monoclinic ADC framework.
The comparator in the column-level single-slope ADC is usually realized by adopting an operational amplifier structure, however, 2 bits are needed for quantizing N-bit code values N One clock cycle is completed, and the operational amplifier type comparator is in the whole 2 N In the process of quantizing each clock period, static current is always consumed, so that the power consumption is high.
Disclosure of Invention
The embodiment of the invention provides the voltage modulation column-level single-slope analog-to-digital converter, solves the technical problem of high power consumption of a column-level single-slope ADC (analog-to-digital converter) adopting an operational amplifier type comparator in the prior art, reduces the power consumption of each path of column circuit, and has more remarkable power consumption reduction effect along with the increase of a pixel array.
The invention provides the following technical scheme through one embodiment of the invention:
a voltage modulation column level single-slope analog-to-digital converter comprises a bias power supply, a slope generator, a first capacitor circuit, a second capacitor circuit, a first inverter, a reset switch, an N-bit counter and an N-bit register, wherein N is a positive integer;
the external column analog signal is input through the first capacitor circuit the input of first phase inverter, the output warp of slope generator the second capacitor circuit connects the input of first phase inverter, reset switch's both ends are connected respectively the input of first phase inverter the output of first phase inverter, the output of biasing power is connected the supply terminal of first phase inverter, the output of first phase inverter is connected the input of N bit counter, the output of N bit counter is connected N bit register.
Preferably, the first capacitance circuit comprises a capacitance C1.
Preferably, the second capacitance circuit comprises a capacitance C2.
Preferably, the first inverter includes a pull-up circuit and a pull-down circuit, the pull-up circuit is turned on at a low level, and the pull-down circuit is turned on at a high level;
the column analog signals are respectively input to the input end of the pull-up circuit and the input end of the pull-down circuit through the first capacitor circuit, the output end of the slope generator is respectively connected with the input end of the pull-up circuit and the input end of the pull-down circuit through the second capacitor circuit, the output end of the bias power supply is grounded through the pull-up circuit and the pull-down circuit which are connected in series, the common end of the pull-up circuit and the pull-down circuit is respectively connected with the first end of the reset switch and the input end of the N-bit counter, and the second end of the reset switch is respectively connected with the input end of the pull-up circuit and the input end of the pull-down circuit.
Preferably, the pull-up circuit comprises a first MOS transistor, and the first MOS transistor is a PMOS.
Preferably, the pull-down circuit comprises a second MOS transistor, and the second MOS transistor is an NMOS.
Preferably, the bias power supply is configured to decrease a voltage input to the power supply terminal of the first inverter after a quiescent operating current of the first inverter increases, and to increase a voltage input to the power supply terminal of the first inverter after the quiescent operating current of the first inverter decreases.
Preferably, the bias power supply comprises an operational amplifier and a second inverter, and the second inverter is identical to the first inverter;
the non-inverting input end of the operational amplifier is connected with a reference voltage, the output end of the operational amplifier is respectively connected with the power supply end of the first phase inverter and the power supply end of the second phase inverter, and the input end and the output end of the second phase inverter are both connected with the inverting input end of the operational amplifier.
Preferably, the operational amplifier is powered by a single power supply.
Preferably, the operational amplifier is an error amplifier.
One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:
the comparator in the column-level single-slope analog-to-digital converter is realized through the phase inverter structure, current is not consumed continuously after the comparator is turned, the power consumption of each column circuit is low, compared with a traditional operational amplifier type comparator, the power consumption of each column circuit is reduced, the structure is simple, and the power consumption reduction effect can be more remarkable along with the increase of a pixel array.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a schematic diagram of a column circuit according to the present invention;
FIG. 2 is a schematic diagram of a first inverter according to the present invention;
FIG. 3 is a circuit diagram of a column circuit of the present invention;
FIG. 4 is a schematic diagram of a bias power supply according to the present invention;
fig. 5 is a circuit diagram of a bias power supply of the present invention.
Detailed Description
The embodiment of the invention provides a voltage modulation column-level single-slope analog-to-digital converter, and solves the technical problem that a column-level single-slope ADC adopting an operational amplifier type comparator in the prior art is high in power consumption.
In order to solve the technical problems, the embodiment of the invention has the following general idea:
a voltage modulation column level single-slope analog-to-digital converter is shown in figure 1 and comprises a bias power supply, a slope generator, a first capacitor circuit, a second capacitor circuit, a first inverter, a reset switch, an N-bit counter and an N-bit register, wherein N is a positive integer;
the output end of the bias power supply is connected with the power supply end of the first phase inverter, the output end of the first phase inverter is connected with the input end of the N-bit counter, and the output end of the N-bit counter is connected with the N-bit register.
In order to better understand the technical scheme, the technical scheme is described in detail in the following with reference to the attached drawings of the specification and specific embodiments.
First, it is stated that the term "and/or" appearing herein is merely one type of associative relationship that describes an associated object, meaning that three types of relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
In this embodiment, the first capacitor circuit, the second capacitor circuit, the first inverter, the reset switch, the N-bit counter, and the N-bit register constitute one row of column circuits in the column-level single-slope analog-to-digital converter, the column-level single-slope analog-to-digital converter includes multiple rows of column circuits, and each row of column circuits is respectively configured to receive one row of analog signals in each row of analog signals, convert the analog signals into digital code values, and output the digital code values. The first capacitor circuit and the second capacitor circuit are circuits formed by capacitors and used for charging and discharging, and the first capacitor circuit or the second capacitor circuit can comprise one capacitor or a plurality of capacitors connected in series or in parallel. The bias power supply is used for providing a power supply voltage Vdd _ inv of a first inverter in all the column circuits, the ramp generator is used for providing a ramp signal Vramp required by analog-to-digital conversion of all the column circuits, and the first inverter is used for comparing the power supply voltage Vdd _ inv with the ramp signal Vramp.
As shown in fig. 2, the first inverter includes a pull-up circuit and a pull-down circuit, the pull-up circuit is turned on at a low level, and the pull-down circuit is turned on at a high level; the column analog signals are respectively input into the input end of the pull-up circuit and the input end of the pull-down circuit through the first capacitor circuit, the output end of the slope generator is respectively connected with the input end of the pull-up circuit and the input end of the pull-down circuit through the second capacitor circuit, the output end of the bias power supply is grounded through the pull-up circuit and the pull-down circuit which are connected in series, the common end of the pull-up circuit and the pull-down circuit is respectively connected with the first end of the reset switch and the input end of the N-bit counter, and the second end of the reset switch is respectively connected with the input end of the pull-up circuit and the input end of the pull-down circuit.
The port of the pull-up circuit connected with the output end of the bias power supply is a power supply end of the first phase inverter, the input end of the pull-up circuit and the input end of the pull-down circuit are input ends of the first phase inverter, and the common end of the pull-up circuit and the pull-down circuit is an output end of the first phase inverter. When the input of the first phase inverter is at a high level, the pull-down circuit is conducted, the input end of the N-bit counter is grounded, and the first phase inverter outputs a low level; when the input of the first phase inverter is at low level, the pull-up circuit is conducted, the input end of the N-bit counter is connected with the output end of the bias power supply, and the first phase inverter outputs high level. The pull-up circuit can comprise a low-level conducting switch tube or a plurality of series-connected low-level conducting switch tubes, such as MOS tubes; the pull-down circuit can also comprise a high-level conducting switch tube or a plurality of high-level conducting switch tubes connected in series, such as MOS tubes.
Specifically, as shown in fig. 3, RST is a reset switch; the first capacitive circuit may include only the capacitor C1, and the second capacitive circuit may include only the capacitor C2; the pull-up circuit can comprise a first MOS transistor M1, wherein the first MOS transistor M1 is a PMOS; the pull-down circuit may include a second MOS transistor M2, and the second MOS transistor M2 is an NMOS. An externally input column analog signal Vpixel is respectively connected with a grid of a first MOS tube M1 and a grid of a second MOS tube M2 through a capacitor C1, an output end of a ramp generator is respectively connected with the grid of the first MOS tube M1 and the grid of the second MOS tube M2 through the capacitor C2, an output end of a bias power supply is grounded through the first MOS tube M1 and the second MOS tube M2 which are connected in series, a common end of the first MOS tube M1 and the second MOS tube M2 is respectively connected with a first end of a reset switch RST and an input end of an N-bit counter, and a second end of the reset switch RST is respectively connected with the grid of the first MOS tube M1 and the grid of the second MOS tube M2.
The drain electrode of the first MOS transistor M1 is connected to the drain electrode of the second MOS transistor M2, the source electrode of the second MOS transistor M2 is grounded, the gate electrode of the first MOS transistor M1 is the input end of the pull-up circuit, the gate electrode of the second MOS transistor M2 is the input end of the pull-down circuit, the common end of the drain electrode of the first MOS transistor M1 and the drain electrode of the second MOS transistor M2 is the output end of the first inverter, and the source electrode of the first MOS transistor M1 is the power supply end of the first inverter.
The working principle of the one-way column circuit in the embodiment is as follows: firstly, in a pixel reset voltage output stage, at this time, vpixel voltage is pixel reset voltage Vrst, a reset switch RST is closed, a first inverter is reset, voltage at a point Vi in fig. 2 is first inverter reset voltage Vcm, and Vramp voltage is ramp reset voltage Vramp0; then, in a pixel signal voltage output stage, at this time, the Vpixel voltage is the pixel signal voltage Vsig, the reset switch RST is turned off, the Vramp voltage rises in a ramp form, and since the Vi point floats, there is a step according to the principle of conservation of charge
(Vcm-Vrst)C1+(Vcm-Vramp0)C2＝(Vi-Vsig)C1+(Vi-Vramp)C2；
Can obtain the product
When in use
And when the driving input voltage Vi of the two MOS tubes is larger than the reset voltage Vcm of the first inverter, the second MOS tube M2 is conducted, the output Vo is grounded, the voltage is zero, the first inverter is overturned, the N-bit counter stops counting, and the counting value at the moment is stored in the N-bit register, namely the N-bit quantization code value of the pixel signal.
This embodiment realizes the comparator among the list level monoclinic analog-to-digital converter through the phase inverter structure like this, no longer continues the consumption current after the comparator upset, and every way column circuit's low power dissipation compares in traditional operational amplifier type comparator, has reduced every way column circuit's consumption and simple structure, and along with pixel array's increase, the power dissipation reduction effect can be more showing.
As can be seen from the operation principle of the column circuit, when the flip point of the first inverter is deviated, the N-bit counter counts more or less, which may cause the quantization code value to be deviated. The static working point of the first phase inverter is easy to fluctuate under the influence of process, power supply voltage and temperature, so that the turning point of the first phase inverter is deviated. For this reason, the present embodiment is preferable that the bias power supply is configured to decrease the voltage input to the power supply terminal of the first inverter after the quiescent operating current of the first inverter increases, and to increase the voltage input to the power supply terminal of the first inverter after the quiescent operating current of the first inverter decreases. Thus, when the static working current of the first inverter is increased, the bias power supply can reduce the current of the first inverter, thereby stabilizing the current of the first inverter; the bias supply may increase the first inverter current as the quiescent operating current of the first inverter decreases, also stabilizing the first inverter current. Therefore, when the static working current of the first inverter in the column circuit fluctuates under the influence of the process, the power supply voltage and the temperature, the bias power supply can stabilize the current of the first inverter and stabilize the working point of the array inverter, the first inverter is less influenced by the process, the power supply voltage and the temperature, and the static working point is more stable, so that the application of high-precision occasions can be realized. In addition, since the bias power supply is used to supply the power supply voltage Vdd _ inv of the first inverters in all the column circuits, all the column circuits share one bias power supply, the power consumption of the bias power supply is negligible compared with that of all the column circuits, and the power consumption is not substantially increased.
As shown in fig. 4, the bias power supply includes an operational amplifier U1 and a second inverter, which is identical to the first inverter; the non-inverting input end of the operational amplifier U1 is connected with the reference voltage Vref, the output end of the operational amplifier U1 is respectively connected with the power supply end of the first phase inverter and the power supply end of the second phase inverter, and the input end and the output end of the second phase inverter are both connected with the inverting input end of the operational amplifier U1. The output end of the operational amplifier U1 is the output end of the bias power supply, and the operational amplifier U1 can be an error amplifier, can supply power for a single power supply and can also supply power for double power supplies. Because the second inverter is completely the same as the first inverter, when the static working current of the first inverter fluctuates, the second inverter also synchronously fluctuates; when the static working current of the first inverter is increased, the static working current of the second inverter is also increased, the voltage Vn in fig. 4 is increased, the reference voltage Vref is constant, the output voltage of the operational amplifier U1 is decreased, that is, the power voltage Vdd _ inv of the first inverter is decreased, and negative feedback is formed, so that the current of the first inverter is reduced, and the current of the first inverter is stabilized; similarly, when the static operating currents of the first MOS transistor M1 and the second MOS transistor M2 decrease, the static operating current of the second inverter also decreases, the voltage Vn in fig. 4 decreases, and the reference voltage Vref is constant, so that the output voltage of the operational amplifier U1 increases, that is, the power voltage Vdd _ inv of the first inverter increases, and negative feedback is formed, so that the current of the first inverter is increased, and the current of the first inverter is stabilized.
In this embodiment, if the first phase inverter includes a first MOS transistor M1 and a second MOS transistor M2, the second phase inverter includes a third MOS transistor M3 and a fourth MOS transistor M4, the third MOS transistor M3 is a PMOS, the fourth MOS transistor M4 is an NMOS, the third MOS transistor M3 has the same size as the first MOS transistor M1, and the fourth MOS transistor M4 has the same size as the second MOS transistor M2. As shown in fig. 5, the output end of the operational amplifier U1 is connected to the source of the third MOS transistor M3, the drain of the third MOS transistor M3 is connected to the drain of the fourth MOS transistor M4, the common end of the drain of the third MOS transistor M3 and the drain of the fourth MOS transistor M4 is connected to the inverting input end of the operational amplifier U1, the inverting input end of the operational amplifier U1 is further connected to the gate of the third MOS transistor M3 and the gate of the fourth MOS transistor M4, and the source of the fourth MOS transistor M4 is grounded. The source of the third MOS transistor M3 is a power supply terminal of the second inverter, the gate of the third MOS transistor M3 and the gate of the fourth MOS transistor M4 are input terminals of the second inverter, and a common terminal between the drain of the third MOS transistor M3 and the drain of the fourth MOS transistor M4 is an output terminal of the second inverter.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A voltage modulation column level single-slope analog-to-digital converter is characterized by comprising a bias power supply, a slope generator, a first capacitor circuit, a second capacitor circuit, a first inverter, a reset switch, an N-bit counter and an N-bit register, wherein N is a positive integer;
the analog signal warp is listed as to outside first capacitive circuit input the input of first phase inverter, the output warp of slope generator the second capacitive circuit is connected the input of first phase inverter, reset switch's both ends are connected respectively the input of first phase inverter the output of first phase inverter, bias power's output is connected the feeder ear of first phase inverter, the output of first phase inverter is connected the input of N bit counter, the output of N bit counter is connected N bit register.
2. The voltage modulated column-level monoclinic analog-to-digital converter of claim 1, wherein the first capacitive circuit comprises a capacitor C1.
3. The voltage modulated column-level monoclinic analog-to-digital converter of claim 1, wherein the second capacitive circuit comprises a capacitor C2.
4. The voltage-modulated column-level monoclinic analog-to-digital converter of claim 1, wherein the first inverter comprises a pull-up circuit and a pull-down circuit, the pull-up circuit is turned on at a low level, and the pull-down circuit is turned on at a high level;
the column analog signals are respectively input to the input end of the pull-up circuit and the input end of the pull-down circuit through the first capacitor circuit, the output end of the slope generator is respectively connected with the input end of the pull-up circuit and the input end of the pull-down circuit through the second capacitor circuit, the output end of the bias power supply is grounded through the pull-up circuit and the pull-down circuit which are connected in series, the common end of the pull-up circuit and the pull-down circuit is respectively connected with the first end of the reset switch and the input end of the N-bit counter, and the second end of the reset switch is respectively connected with the input end of the pull-up circuit and the input end of the pull-down circuit.
5. The voltage-modulated column-level monoclinic analog-to-digital converter of claim 4, wherein the pull-up circuit comprises a first MOS transistor, and the first MOS transistor is a PMOS.
6. The voltage modulated column-level monoclinic analog-to-digital converter of claim 4, wherein the pull-down circuit comprises a second MOS transistor, and the second MOS transistor is an NMOS.
7. The voltage-modulated column-level monoclinic analog-to-digital converter of any one of claims 1 to 6, wherein the bias power supply is configured to decrease the voltage input to the supply terminal of the first inverter after the quiescent operating current of the first inverter increases, and to increase the voltage input to the supply terminal of the first inverter after the quiescent operating current of the first inverter decreases.
8. The voltage-modulated column-level monoclinic analog-to-digital converter of claim 7, wherein the bias power supply comprises an operational amplifier and a second inverter, the second inverter being identical to the first inverter;
the non-inverting input end of the operational amplifier is connected with a reference voltage, the output end of the operational amplifier is respectively connected with the power supply end of the first phase inverter and the power supply end of the second phase inverter, and the input end and the output end of the second phase inverter are both connected with the inverting input end of the operational amplifier.
9. The voltage modulated column-level monoclinic analog-to-digital converter of claim 8, wherein the operational amplifier supplies a single power supply.
10. The voltage modulated column-level monoclinic analog-to-digital converter of claim 8, wherein the operational amplifier is an error amplifier.
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| CN202110947681.2A CN115913224A (en) | 2021-08-18 | 2021-08-18 | Voltage modulation column level single-slope analog-to-digital converter |
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| CN202110947681.2A CN115913224A (en) | 2021-08-18 | 2021-08-18 | Voltage modulation column level single-slope analog-to-digital converter |
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