CN115911105A - Solid-state source doping method based on two-dimensional semiconductor and two-dimensional semiconductor transistor - Google Patents
Solid-state source doping method based on two-dimensional semiconductor and two-dimensional semiconductor transistor Download PDFInfo
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- CN115911105A CN115911105A CN202211489343.XA CN202211489343A CN115911105A CN 115911105 A CN115911105 A CN 115911105A CN 202211489343 A CN202211489343 A CN 202211489343A CN 115911105 A CN115911105 A CN 115911105A
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Abstract
The invention provides a solid source doping method based on a two-dimensional semiconductor and a two-dimensional semiconductor transistor, wherein the solid source doping method comprises the following steps: providing a substrate; preparing a two-dimensional semiconductor material layer on the substrate; carrying out surface modification treatment on the surface of the two-dimensional semiconductor material layer away from the substrate; evaporating a solid active source metal layer on the surface of the two-dimensional semiconductor material layer away from the substrate; evaporating a conventional metal layer on the solid active source metal layer; and annealing the solid active source metal layer and the conventional metal layer to obtain a two-dimensional semimetal/metal material layer. The solid source doping method avoids the Fermi pinning effect generated by the conventional metal direct evaporation, can form ohmic contact and solves the problem of high resistance contact with lower cost.
Description
Technical Field
The invention particularly relates to a solid-state source doping method based on a two-dimensional semiconductor and a two-dimensional semiconductor transistor, and belongs to the technical field of two-dimensional semiconductors.
Background
Silicon-based technology is about to reach the physical limit of moore's law, the scaling-down speed of integrated circuit transistors is continuously reduced, the yield is limited by the gradual narrowing of process cost and yield, in addition, the power consumption of a unit area is rapidly improved due to the improvement of unit integration level and the improvement of current density of the silicon-based integrated circuit, the problem of power consumption wall accompanying the scattering problem is more serious, and the problems are more and more acute in sub-10 nm advanced nodes. Due to the atomic-scale ultrathin characteristic of the two-dimensional semiconductor material, the two-dimensional semiconductor material can continue the Moore's law, is expected to break the problem of a power consumption wall, further improves the performance and reduces the power consumption. Since stacked transistors in the form of 3D (three-dimensional) integrated chips can alleviate memory bandwidth problems or "memory walls," it is believed that the future of the half-moore law will be driven by 3D integrated chips, which may also drastically change the design and routing methods. Where two-dimensional semiconductors may be a key solution to creating such 3D integrated chips, as they can be easily grown at low temperatures while keeping the electrical characteristics intact, but high resistance contacts have been an obstacle to the adoption of two-dimensional semiconductors.
For a semiconductor material transistor, a conventional metal is in direct contact with a two-dimensional semiconductor material through a traditional processing technology, so that a Fermi-pinning effect (Fermi-pinning effect) caused by periodic lattice damage and abnormally high contact resistance caused by a Schottky barrier generated by Fermi pinning are difficult to avoid, the performance of the small-sized two-dimensional transistor is almost determined by the contact resistance rather than channel conductance, most of energy is consumed in a metal-semiconductor junction, and a mature solution is not provided at present, so that the performance and the power consumption of the two-dimensional transistor are greatly limited.
There are three main solutions in the field at present: 1) Although the conventional semi-metal (such as Bi) contact mode can improve certain Fermi pinning, the problem of low melting point exists, and the semi-metal (such as Bi) contact mode cannot be compatible with a semiconductor processing technology; 2) Aiming at the phase change contact process of a two-dimensional semiconductor material (such as chemical solution induced phase change containing Li, laser phase change and the like), at present, no scheme which can be compatible with advanced node manufacturing and processing exists, particularly, the current mode of inducing the phase change of the two-dimensional material by chemical solution has high solution molecule diffusivity and poor stability, laser spots in laser induced phase change are often large (micron-scale upward), and nanoscale small-size graphs cannot be made, so that the schemes are not suitable for the manufacturing and processing process of the advanced node of the transistor; 3) The ion implantation method of the silicon-based CMOS process is not yet applied to two-dimensional materials (ion implantation causes more damage to two-dimensional materials and may not be applied to two-dimensional crystal materials at present).
How to eliminate the fermi pinning and realize ohmic contact is the core problem in the whole two-dimensional device field, and the technical scheme that the ohmic contact of a two-dimensional semiconductor transistor is realized and the contact resistance is reduced is urgently needed at present.
Disclosure of Invention
The invention aims to realize ohmic contact of a two-dimensional semiconductor transistor and reduce contact resistance so as to widen the application potential of the two-dimensional semiconductor transistor.
In order to achieve the above object, the present invention adopts the following technical means.
A solid source doping method based on a two-dimensional semiconductor comprises the following steps: providing a substrate; preparing a two-dimensional semiconductor material layer on the substrate; carrying out surface modification treatment on the surface of the two-dimensional semiconductor material layer away from the substrate; evaporating a solid active source metal layer on the surface of the two-dimensional semiconductor material layer away from the substrate; evaporating a conventional metal layer on the solid active source metal layer; and annealing the solid active source metal layer and the conventional metal layer.
Wherein the surface modification treatment comprises bombarding the surface of the two-dimensional semiconductor material layer far away from the substrate by using ultra-low power (1-100 w) soft plasma.
Wherein the annealing treatment adopts a rapid annealing mode of annealing at 250-600 ℃ for 2-60 s.
Wherein the two-dimensional semiconductor material layer comprises any one of indium selenide (I nSe), molybdenum disulfide (MoS 2), indium diselenide (MoSe 2), tungsten disulfide (WS 2), tungsten diselenide (WSe 2), molybdenum telluride (MoTe 2), black Phosphorus (BP), silylene (Si lene), germene (germane), telluriene (Te lene), ionic layered semiconductor material (Bi 2O2X, X = S or Se), or a combination thereof.
Wherein the thickness of the solid active source metal layer is 0.5-5nm.
Wherein the solid active source metal layer comprises any one or a combination of yttrium (Y), scandium (Sc), vanadium (V), iron (Fe), molybdenum (Mo), tantalum (Ta), rhenium (Re).
Wherein the conventional metal layer comprises any one or combination of Au, ti, al, ni, pd, ag and TiNx.
The present invention also provides a two-dimensional semiconductor transistor, comprising: a substrate; a two-dimensional semiconductor material layer disposed on the substrate; the two-dimensional semi-metal/metal material layer is arranged on the surface of the two-dimensional semiconductor material layer far away from the substrate; a solid-state source active metal layer disposed on a surface of the two-dimensional semi-metal/metal material layer distal from the two-dimensional semiconductor material layer; a conventional metal layer disposed on a surface of the solid source active metal layer remote from the two-dimensional semi-metallic/metallic material layer.
The two-dimensional semi-metal/metal material layer is obtained by inducing phase change of the two-dimensional semiconductor material layer by metal atoms in the solid source active metal layer.
Wherein the solid active source metal layer comprises any one or combination of yttrium (Y), scandium (Sc), vanadium (V), iron (Fe), molybdenum (Mo), tantalum (Ta), rhenium (Re).
The invention has the following advantages and technical effects:
the invention adopts a solid source doping induced phase change technology based on a two-dimensional semiconductor to change the two-dimensional semiconductor material induced phase of a contact area into a two-dimensional semi-metal material or a two-dimensional metal material, and the induced two-dimensional semi-metal material (2D semimetal l) or the induced two-dimensional metal material (2D meta l) is directly contacted with the two-dimensional semiconductor material, thereby avoiding the Fermi pinning effect generated by the direct evaporation of conventional metal, forming ohmic contact and solving the problem of high resistance contact with lower cost.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and it will be apparent to those skilled in the art that several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be construed as the protection scope of the present invention.
Fig. 1-5 are schematic structural diagrams obtained from steps in a process of preparing a two-dimensional semi-metal/metal material layer according to a two-dimensional semiconductor-based solid-state source doping method provided by the invention.
Fig. 6-12 are schematic structural diagrams obtained from steps in a process of manufacturing a two-dimensional semiconductor transistor according to the solid-state source doping method based on a two-dimensional semiconductor provided by the present invention.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
Example one
This embodiment specifically describes a solid-state source doping method based on a two-dimensional semiconductor, which includes the following steps: providing a substrate 100; preparing a two-dimensional semiconductor material layer 101 on the substrate; performing surface modification treatment on the surface of the two-dimensional semiconductor material layer 101 away from the substrate; evaporating a solid active source metal layer 102 on the surface of the two-dimensional semiconductor material layer far away from the substrate; evaporating a conventional metal layer 103 on the solid active source metal layer; and annealing the solid active source metal layer and the conventional metal layer to obtain a two-dimensional semimetal/metal material layer 104.
A two-dimensional semiconductor-based solid-state source doping method is described in detail below with reference to fig. 1 to 5, and includes the following steps:
s1-1, providing a substrate 100, wherein the substrate is an insulating substrate such as silicon, silicon oxide, sapphire, mica and the like;
s1-2, preparing a two-dimensional semiconductor material layer 101 on the substrate 101, and obtaining a structure as shown in fig. 1, wherein the two-dimensional semiconductor material layer includes any one of indium selenide (I nSe), molybdenum disulfide (MoS 2), indium diselenide (MoSe 2), tungsten disulfide (WS 2), tungsten diselenide (WSe 2), molybdenum telluride (MoTe 2), black Phosphorus (BP), silylene (Si l ene), germanene (Germanene), telluriene (Te l urea), ionic layered semiconductor material (Bi 2O2X, X = S or Se), or a combination thereof, but the present invention is not limited thereto;
s1-3, performing a surface modification treatment on a surface of the two-dimensional semiconductor material layer 101 away from the substrate 100, as shown in fig. 2, where the surface modification treatment includes bombarding the surface of the two-dimensional semiconductor material layer away from the substrate with soft plasma, specifically, bombarding the surface of the two-dimensional semiconductor material layer 101 away from the substrate 100 with ultra-low power soft plasma (such as nitrogen, argon, hydrogen, etc.) of 1-100w for 5-300 seconds, so that lattice defects, distortions, etc. are generated on the surface of the two-dimensional semiconductor material layer 101, the surface thereof is modified and implantation active sites are generated, so that it is easier to implant active metal atoms subsequently;
s1-4, evaporating a solid active source metal layer 102 on the surface of the two-dimensional semiconductor material layer 101 away from the substrate 100 to obtain a structure as shown in FIG. 3, wherein the thickness of the solid active source metal layer is 0.5-5nm, the metal in the solid active source metal layer is a metal which is easy to react with the two-dimensional semiconductor material, and the category of the metal can include any one or combination of yttrium (Y), scandium (Sc), vanadium (V), iron (Fe), molybdenum (Mo), tantalum (Ta), rhenium (Re) and the like;
s1-5, evaporating a conventional metal layer 103 on the solid active source metal layer 102 to obtain a structure as shown in FIG. 4, wherein the thickness of the conventional metal layer is more than 5nm, and the metal in the conventional metal layer is usually inert metal such as Au, ti, al, ni, pd, ag, tiNx and the like, and has the function of passivation to prevent the active metal layer from being oxidized;
s1-6, performing annealing treatment on the solid active source metal layer 102 and the conventional metal layer 103 to obtain a structure as shown in fig. 5, where metal atoms in the solid active source metal layer 102 are injected into the two-dimensional semiconductor material layer 101 to generate substitutional doping, and the substitutional doped two-dimensional semiconductor material layer is induced to undergo phase transition to be converted into a two-dimensional semi-metal/metal material layer or a two-dimensional metal material layer 104, the annealing treatment may adopt a rapid annealing manner of annealing at 250 ℃ to 600 ℃ for 2-60S, or a conventional annealing manner of annealing at 150 ℃ to 250 ℃ for 15min to 4h under high vacuum, the annealing time and temperature have an influence on the number of substitutional doped atoms, and the longer the annealing time or the higher the temperature, the more the number of atoms doped into the two-dimensional semiconductor material layer, and the higher the concentration of metal atoms in the formed two-dimensional metal material layer.
The two-dimensional semiconductor-based solid-state source doping method provided by the embodiment can be used for inducing the phase of the two-dimensional semiconductor material in the contact area to be changed into the two-dimensional semi-metal material or the two-dimensional metal material, the induced two-dimensional semi-metal material or the induced two-dimensional metal material layer 104 is directly contacted with the two-dimensional semiconductor material 101, the Fermi pinning effect generated by conventional metal direct evaporation is avoided, ohmic contact can be formed, the contact resistance is lower than 200 omega-mum, the Schottky barrier height is close to 0meV of the physical limit, the on-state current of the two-dimensional ballistic transistor is larger than 1 mA/mum, and the contact resistance of the two-dimensional semiconductor material is greatly improved.
Example two
This embodiment describes a two-dimensional semiconductor transistor provided by the present invention, which includes: a substrate 200; a two-dimensional semiconductor material layer 201 disposed on the substrate 100; a two-dimensional semi-metal/metal material layer 204 disposed on a surface of the two-dimensional semiconductor material layer remote from the substrate 200; a solid-state source active metal layer 202 disposed on a surface of the two-dimensional semi-metal/metal material layer 204 remote from the two-dimensional semiconductor material layer 201; a conventional metal layer 203 disposed on a surface of the solid source active metal layer 202 distal from the two-dimensional semi-metallic/metallic material layer 204.
The process of manufacturing a two-dimensional semiconductor transistor is described in detail below with reference to fig. 6-12, and includes the following steps:
s2-1, providing a substrate 200, wherein the substrate is an insulating substrate such as silicon, silicon oxide, sapphire, mica and the like;
s2-2, preparing a two-dimensional semiconductor material layer 201 on the substrate 200, where the resulting structure is shown in fig. 6, where the two-dimensional semiconductor material layer includes any one of indium selenide (InSe), molybdenum disulfide (MoS 2), indium diselenide (MoSe 2), tungsten disulfide (WS 2), tungsten diselenide (WSe 2), molybdenum telluride (MoTe 2), black Phosphorus (BP), silylene (Siliene), germanene (Germanene), telluriene (telluriene), ionic layered semiconductor material (Bi 2O2X, X = S or Se), or a combination thereof, but the present invention is not limited thereto;
s2-3, forming a photoresist layer 210 on the two-dimensional semiconductor material layer 201, and forming a photoresist pattern 211 in the photoresist layer 201 to expose a part of the surface of the two-dimensional semiconductor material layer 201, wherein the obtained structure is shown in FIG. 7;
s2-3, as shown in FIG. 8, performing plasma treatment, specifically, bombarding the semiconductor structure for 5-300 seconds by using 1-100w of ultra-low power soft plasma (such as nitrogen, argon, hydrogen, and the like), so that lattice defects, distortion, and the like are generated on the surface of the exposed two-dimensional semiconductor material layer 201, and active metal atoms are injected more easily subsequently;
s2-4, evaporating a solid active source metal layer 102 and a conventional metal layer 103 to obtain a structure as shown in fig. 9, wherein the solid active source metal layer has a thickness of 0.5-5nm, the metal in the solid active source metal layer is a metal that is easily reactive with a two-dimensional semiconductor material, and the metal can include any one or a combination of yttrium (Y), scandium (Sc), vanadium (V), iron (Fe), molybdenum (Mo), tantalum (Ta), rhenium (Re), etc., and the conventional metal layer has a thickness of 5nm or more, and the metal in the conventional metal layer is often an inert metal such as Au, ti, al, ni, pd, ag, tiNx, etc., and has a function of passivation and preventing oxidation of the active metal layer;
s2-5, stripping the photoresist layer 210 to obtain a structure as shown in FIG. 10;
s2-6, performing annealing treatment on the solid active source metal layer 202 and the normal metal layer 203, injecting metal atoms in the solid active source metal layer 102 into the two-dimensional semiconductor material layer 101, generating substitutional doping, and inducing phase transition of the substitutional doped two-dimensional semiconductor material layer into a two-dimensional semi-metal/metal material layer 204, so as to obtain a basic structure of the two-dimensional semiconductor transistor provided in this embodiment, as shown in fig. 11, the two-dimensional semiconductor transistor includes: a substrate 200; a two-dimensional semiconductor material layer 201 disposed on the substrate 100; a two-dimensional semi-metal/metal material layer 204 disposed on a surface of the two-dimensional semiconductor material layer remote from the substrate 200; a solid-state source active metal layer 202 disposed on a surface of the two-dimensional semi-metal/metal material layer 204 remote from the two-dimensional semiconductor material layer 201; a regular metal layer 203 disposed on a surface of the solid source active metal layer 202 remote from the two-dimensional semi-metallic/metallic material layer 204;
and S2-7, preparing other conventional structures of the transistor, including forming a high-k gate dielectric layer 205 and a top gate metal 206, wherein the preparation process is a conventional process for preparing the conventional transistor and is not repeated here, and the obtained structure is shown in FIG. 12.
According to the two-dimensional semiconductor transistor, the two-dimensional semi-metal material layer is in direct contact with the two-dimensional semiconductor material in the contact area, the two-dimensional semi-metal/metal material layer is a semi-metal material/metal layer obtained by inducing phase change of the two-dimensional semiconductor material layer through metal atoms in the solid source active metal layer, the Fermi pinning effect generated by conventional metal direct evaporation is avoided, ohmic contact can be formed, contact resistance is reduced, and the requirement of a semiconductor technical route is met at an advanced node.
The above-mentioned embodiments are merely illustrative of the technical concepts and features of the present invention, and are preferred embodiments, which are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (10)
1. A solid source doping method based on a two-dimensional semiconductor is characterized by comprising the following steps:
providing a substrate;
preparing a two-dimensional semiconductor material layer on the substrate;
carrying out surface modification treatment on the surface of the two-dimensional semiconductor material layer away from the substrate;
evaporating a solid active source metal layer on the surface of the two-dimensional semiconductor material layer away from the substrate;
evaporating a conventional metal layer on the solid active source metal layer;
and annealing the solid active source metal layer and the conventional metal layer to obtain a two-dimensional semimetal/metal material layer.
2. The two-dimensional semiconductor-based solid-state source doping method according to claim 1, wherein the surface modification treatment comprises bombarding the surface of the two-dimensional semiconductor material layer away from the substrate with ultra-low power (1-100 w) soft plasma.
3. The two-dimensional semiconductor-based solid-state source doping method according to claim 1, wherein the annealing treatment adopts a rapid annealing mode of annealing from 250 ℃ to 600 ℃ for 2-60 s.
4. A two-dimensional semiconductor-based solid-state source doping method according to any one of claims 1 to 3, wherein the two-dimensional semiconductor material layer comprises indium selenide (InSe), molybdenum disulfide (MoS) 2 ) Indium diselenide (MoSe) 2 ) Tungsten disulfide (WS) 2 ) Tungsten diselenide (WSe) 2 ) Molybdenum telluride (MoTe) 2 ) Black Phosphorus (BP), silylene (Siliene), germane (germane), telluriene (telluriene), ionic layered semiconductor material (Bi) 2 O 2 X, X = S or Se) or a combination thereof.
5. The two-dimensional semiconductor-based solid state source doping method according to any one of claims 1 to 3, wherein the thickness of the solid state active source metal layer is 0.5-5nm.
6. A method as claimed in any one of claims 1 to 3, wherein the solid active source metal layer comprises any one or a combination of yttrium (Y), scandium (Sc), vanadium (V), iron (Fe), molybdenum (Mo), tantalum (Ta), rhenium (Re).
7. A two-dimensional semiconductor based solid-state source doping method according to any one of claims 1 to 3, wherein the normal metal layer comprises any one of gold (Au), titanium (Ti), aluminum (Al), nickel (Ni), palladium (Pd), silver (Ag), titanium nitride (TiNx) or a combination thereof.
8. A two-dimensional semiconductor transistor, comprising:
a substrate;
a two-dimensional semiconductor material layer disposed on the substrate;
the two-dimensional semi-metal/metal material layer is arranged on the surface of the two-dimensional semiconductor material layer far away from the substrate;
a solid-state source active metal layer disposed on a surface of the two-dimensional semi-metal/metal material layer distal from the two-dimensional semiconductor material layer;
a conventional metal layer disposed on a surface of the solid source active metal layer remote from the two-dimensional semi-metallic/metallic material layer.
9. The two-dimensional semiconductor transistor according to claim 8, wherein the two-dimensional semi-metal/metal material layer is a semi-metal/metal material layer obtained by inducing a phase transition of the two-dimensional semiconductor material layer by metal atoms in the solid-state source active metal layer.
10. A two-dimensional semiconductor transistor according to claim 8 or 9, wherein the solid active source metal layer comprises any one or any combination of yttrium (Y), scandium (Sc), vanadium (V), iron (Fe), molybdenum (Mo), tantalum (Ta), rhenium (Re).
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