CN115910986A - Three-dimensional heterogeneous integrated radio frequency micro-system - Google Patents
Three-dimensional heterogeneous integrated radio frequency micro-system Download PDFInfo
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- CN115910986A CN115910986A CN202211568466.2A CN202211568466A CN115910986A CN 115910986 A CN115910986 A CN 115910986A CN 202211568466 A CN202211568466 A CN 202211568466A CN 115910986 A CN115910986 A CN 115910986A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention discloses a three-dimensional heterogeneous integrated radio frequency microsystem, which comprises a silicon-based packaging layer and a high/low temperature co-fired ceramic packaging layer; the low-power radio frequency chip is placed on the silicon-based switching layer, and the connection of radio frequency signals, power signals and control signals is completed through a rewiring layer on the top of the silicon-based switching layer and a silicon-based packaging bonding wire; the high-power radio frequency chip is placed on the high/low temperature co-fired ceramic base, and the connection of radio frequency signals, power signals and control signals is completed through the high/low temperature co-fired ceramic packaging bonding wire and the high/low temperature co-fired ceramic base. The invention adopts a mode of combining a silicon-based packaging technology and a high/low temperature co-fired ceramic technology to realize the three-dimensional packaging of a multi-chip stacking completion system, and the heterogeneous integration mode can fully optimize the chip layout in the packaging according to the characteristics of packaging materials and chip materials by comprehensively considering the radio frequency performance and the physical performance of the packaging materials and the chip materials, thereby reducing the volume of a radio frequency micro-system and improving the reliability of the system.
Description
Technical Field
The invention relates to the technical field of radio frequency microsystem packaging, in particular to a three-dimensional heterogeneous integrated radio frequency microsystem.
Background
The traditional integrated circuit package mainly adopts a two-dimensional structure single chip package or a simple IC stacking technology, the utilization rate of an internal space of the traditional package is extremely low, the interconnection is long, and complicated interconnection parasitic effects are easily caused, so that signal distortion is caused, and the performance of a chip is seriously influenced. In order to achieve miniaturization, light weight, thinning, integration, multiple functions, low power consumption, high reliability and low cost of system equipment, engineers propose system packaging technologies and methods such as chip stacking technology and vertical interconnection technology.
The high/low temperature co-fired ceramic packaging technology and the silicon-based packaging technology can perform three-dimensional stacking of chips to realize three-dimensional packaging of a system, the two packaging technologies have advantages and disadvantages respectively, and the high/low temperature co-fired ceramic packaging technology is low in price but low in process precision; the silicon-based packaging process has higher cost, but higher process precision and can be better compatible with a silicon-based chip.
With the development of radio frequency microsystem technology, the volume of the system is smaller and smaller, the power density in the unit volume of the system is higher and higher, the requirement on the processing precision of the process is higher and higher, the high/low temperature co-fired ceramic packaging technology and the silicon-based packaging technology are comprehensively applied, the advantages of the two packaging technologies can be fully exerted, and the performance of the radio frequency microsystem is improved.
Patent 1 (application number: 201810340528.1 application date: 2018-04-17) provides a ceramic double-sided three-dimensional integrated architecture of an ultra-wideband radio frequency micro-system, cavity grooves are formed in both sides of a ceramic substrate, a metal micro-frame is welded on the front side of the ceramic substrate, a front cover plate is welded on the metal micro-frame, a back cover plate is welded on the back cavity groove of the ceramic substrate, BGA bonding pads are arranged on the back side of the ceramic substrate except for the back cover plate, the BGA bonding pads are welded on the back side of the ceramic substrate through the BGA bonding pads, the internal integration density of the radio frequency micro-system is improved by nearly one time, the volume occupancy rate of an external interconnection interface and airtight packaging is greatly reduced, but the thermal expansion coefficient and the thermal conductivity of the system are poor, and the thermal reliability is not good enough. Patent 2 (application No. 201610626411.0 application No. 2016-08-02) provides an rf microsystem package module and a manufacturing method thereof, which reduces the package size and improves the electrical performance of the rf microsystem package module through vertical stacking and electrical interconnection of chips, but also does not solve the thermal expansion coefficient and thermal conductivity problems of the system.
Disclosure of Invention
The invention aims to provide a three-dimensional heterogeneous integrated radio frequency micro-system which is high in integration level, small in size, low in power, high in stability and low in production cost.
The technical solution for realizing the purpose of the invention is as follows: a three-dimensional heterogeneous integrated radio frequency microsystem comprises a silicon-based packaging layer and a high/low temperature co-fired ceramic packaging layer;
the silicon-based packaging layer comprises a solder ball, a silicon-based cover layer top rewiring layer, a silicon-based cover layer insulating layer, a silicon-based cover layer silicon through hole, a silicon-based cavity, a low-power radio frequency chip, a silicon-based packaging bonding wire, a silicon-based switching layer top rewiring layer, a silicon-based switching layer silicon through hole and a silicon-based switching layer bottom rewiring layer which are arranged in sequence;
the high/low temperature co-fired ceramic packaging layer comprises heterogeneous interlayer solder balls, a high/low temperature co-fired ceramic cover plate, a high/low temperature co-fired ceramic cavity, a high/low temperature co-fired ceramic vertical through hole, a high-power radio frequency chip, a high/low temperature co-fired ceramic packaging bonding wire and a high/low temperature co-fired ceramic base which are sequentially arranged;
the low-power radio frequency chip is placed on the silicon-based switching layer, and connection of radio frequency signals, power signals and control signals is completed through a rewiring layer on the top of the silicon-based switching layer and a silicon-based packaging bonding wire; the high-power radio frequency chip is placed on the high/low temperature co-fired ceramic base, and the connection of radio frequency signals, power signals and control signals is completed through the high/low temperature co-fired ceramic packaging bonding wire and the high/low temperature co-fired ceramic base.
Further, the high-power radio frequency chip is placed on the high/low temperature co-fired ceramic base, signals are led to the top of the high/low temperature co-fired ceramic packaging layer through the high/low temperature co-fired ceramic packaging bonding wire, the high/low temperature co-fired ceramic base and the high/low temperature co-fired ceramic vertical through hole, and then the high-power radio frequency chip and the silicon-based packaging layer form signal interconnection.
Furthermore, the bottom of the high/low temperature co-fired ceramic base is free of ball planting.
Furthermore, solder balls are implanted on the redistribution layer on the top of the silicon-based cover layer in the silicon-based packaging layer, and the solder balls are interconnected with an external motherboard.
Furthermore, a pad is arranged on a rewiring layer at the bottom of the silicon-based switching layer in the silicon-based packaging layer and is connected with the high/low temperature co-fired ceramic packaging layer through a heterogeneous interlayer welding ball to form signal interconnection.
Furthermore, the silicon-based packaging layer comprises N layers of silicon-based packaging, wherein the N layers of silicon-based packaging are formed by N layers of solder balls, a silicon-based cover layer top rewiring layer, a silicon-based cover layer insulating layer, a silicon-based cover layer silicon through hole, a silicon-based cavity, a low-power radio-frequency chip, a silicon-based packaging bonding wire, a silicon-based transfer layer top rewiring layer, a silicon-based transfer layer silicon through hole and a silicon-based transfer layer bottom rewiring layer, signal interconnection is achieved among the layers through solder, and N is larger than or equal to 1.
Furthermore, the high/low temperature co-fired ceramic packaging layer is formed by N layers of heterogeneous interlayer welding balls, a high/low temperature co-fired ceramic cover plate, a high/low temperature co-fired ceramic cavity, a high/low temperature co-fired ceramic vertical through hole, a high-power radio frequency chip, a high/low temperature co-fired ceramic packaging bonding wire and a high/low temperature co-fired ceramic base to form N layers of high/low temperature co-fired ceramic packaging, signal interconnection is realized among the layers through welding materials, and N is more than or equal to 1.
Compared with the prior art, the invention has the remarkable advantages that: (1) By adopting the combination of the high/low temperature co-fired ceramic packaging process and the silicon-based packaging process, the chip with thicker thickness can be integrated by adopting the high/low temperature co-fired ceramic packaging process, so that the integration level of the system is improved; (2) Compared with a silicon-based material, the high/low temperature co-fired ceramic has higher thermal expansion coefficient and thermal conductivity, and the two packaging processes are combined for use, so that the problem of reduced thermal reliability caused by a high-power radio frequency chip is solved, and the reliability of a system is improved.
Drawings
Fig. 1 is a schematic structural diagram of a three-dimensional heterogeneous integrated radio frequency microsystem according to the present invention.
Fig. 2 is a schematic structural diagram of a 2-layer silicon-based package + 1-layer high/low temperature co-fired ceramic package in the embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a 1-layer silicon-based package + 2-layer high/low temperature co-fired ceramic package in the embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and the specific embodiments.
Referring to fig. 1, the three-dimensional heterogeneous integrated radio frequency microsystem of the present invention includes a silicon-based package layer 120 and a high/low temperature co-fired ceramic package layer 121;
the silicon-based packaging layer 120 comprises a solder ball 101, a silicon-based cover layer top rewiring layer 102, a silicon-based cover layer insulating layer 103, a silicon-based cover layer 104, a silicon-based cover layer silicon through hole 105, a silicon-based cavity 106, a low-power radio-frequency chip 107, a silicon-based packaging bonding wire 108, a silicon-based transfer layer top rewiring layer 109, a silicon-based transfer layer 110, a silicon-based transfer layer silicon through hole 111 and a silicon-based transfer layer bottom rewiring layer 112 which are sequentially arranged;
the high/low temperature co-fired ceramic packaging layer comprises heterogeneous interlayer solder balls 113, a high/low temperature co-fired ceramic cover plate 114, a high/low temperature co-fired ceramic cavity 115, high/low temperature co-fired ceramic vertical through holes 116, a high-power radio frequency chip 117, a high/low temperature co-fired ceramic packaging bonding wire 118 and a high/low temperature co-fired ceramic base 119 which are arranged in sequence;
the low-power radio frequency chip 107 is placed on a silicon-based switching layer 110, and connection of radio frequency signals, power signals and control signals is completed through a rewiring layer 109 on the top of the silicon-based switching layer and a silicon-based packaging bonding wire 108; the high-power radio frequency chip 117 is placed on the high/low temperature co-fired ceramic base 119, and the connection of radio frequency signals, power signals and control signals is completed through the high/low temperature co-fired ceramic packaging bonding wire 118 and the high/low temperature co-fired ceramic base 119.
Further, the high-power radio frequency chip 117 is placed on the high/low temperature co-fired ceramic base 119, and a signal is introduced to the top of the high/low temperature co-fired ceramic packaging layer 121 through the high/low temperature co-fired ceramic packaging bonding wire 118, the high/low temperature co-fired ceramic base 119 and the high/low temperature co-fired ceramic vertical through hole 116, and then forms signal interconnection with the silicon-based packaging layer 120.
Furthermore, the bottom of the high/low temperature co-fired ceramic base 119 is free of a ball, and can be fully contacted with the cold plate unit, so that the high-power radio frequency chip 117 and the cold plate unit are guaranteed to have the best heat conduction effect.
Furthermore, solder balls 101 are implanted on the redistribution layer 102 on the top of the silicon-based cap layer in the silicon-based packaging layer 120, and the solder balls 101 are interconnected with an external motherboard.
Furthermore, a pad is arranged on the silicon-based interposer bottom redistribution layer 112 in the silicon-based packaging layer 120, and can form signal interconnection with the high/low temperature co-fired ceramic packaging layer 121 through a heterogeneous inter-layer solder ball 113.
Further, the silicon-based packaging layer 120 may be composed of 1 layer of solder balls 101, a silicon-based cap layer top redistribution layer 102, a silicon-based cap layer insulating layer 103, a silicon-based cap layer 104, a silicon-based cap layer silicon via 105, a silicon-based cavity 106, a low-power radio frequency chip 107, a silicon-based packaging bonding wire 108, a silicon-based interposer 109, a silicon-based interposer 110, a silicon-based interposer 111, and a silicon-based interposer bottom redistribution layer 112, or may be composed of N layers of solder balls 101, a silicon-based cap layer top redistribution layer 102, a silicon-based cap layer insulating layer 103, a silicon-based cap layer 104, a silicon-based cap layer silicon via 105, a silicon-based cavity 106, a low-power radio frequency chip 107, a silicon-based packaging bonding wire 108, a silicon-based interposer top redistribution layer 109, a silicon-based interposer 110, a silicon-based interposer silicon via layer silicon via 111, and a silicon-based interposer bottom redistribution layer 112, where signal interconnection is realized by solder between layers, where N > 1.
Further, the high/low temperature co-fired ceramic package layer 121 may be composed of 1 heterogeneous interlayer solder ball 113, a high/low temperature co-fired ceramic cover plate 114, a high/low temperature co-fired ceramic cavity 115, a high/low temperature co-fired ceramic vertical through hole 116, a high power radio frequency chip 117, a high/low temperature co-fired ceramic package bonding wire 118, and a high/low temperature co-fired ceramic base 119, or may be composed of N heterogeneous interlayer solder balls 113, a high/low temperature co-fired ceramic cover plate 114, a high/low temperature co-fired ceramic cavity 115, a high/low temperature co-fired ceramic vertical through hole 116, a high power radio frequency chip 117, a high/low temperature co-fired ceramic package bonding wire 118, and a high/low temperature co-fired ceramic base 119 to form N high/low temperature co-fired ceramic packages, signal interconnection is realized between layers by solder, and N is greater than 1.
Further, the silicon-based packaging layer 120 adopts a silicon-based packaging process, so that the integration level of the system is improved.
Further, the high/low temperature co-fired ceramic package layer 121 adopts a high/low temperature co-fired ceramic package process, so that the thermal expansion coefficient and the thermal conductivity of the system are improved.
Furthermore, the silicon-based packaging process and the high/low temperature co-fired ceramic packaging process are combined, so that the problem of reduced thermal reliability caused by a high-power radio frequency chip is solved while the system volume is smaller.
Example 1
The three-dimensional heterogeneous integrated radio frequency microsystem of the present embodiment is packaged by using 2 layers of silicon-based package +1 layer of high/low temperature co-fired ceramic package structure, as shown in fig. 2, the three-dimensional heterogeneous integrated radio frequency microsystem is composed of a silicon-based package layer 220 and a high/low temperature co-fired ceramic package layer 221, from top to bottom, the silicon-based packaging layer 220 sequentially comprises 1 layer of solder balls 201,1 layer of silicon-based cover layer top rewiring layer 202,1 layer of silicon-based cover layer insulating layer 203,1 layer of silicon-based cover layer 204,1 layer of silicon-based cover layer silicon through hole 205,1 layer of silicon-based cavity 206,1 layer of low-power radio- frequency chip 207,1 layer of silicon-based packaging bonding wire 208,1 layer of silicon-based transfer layer top rewiring layer 209,1 layer of silicon-based transfer layer 210,1 layer of silicon-based transfer layer silicon through hole 211,1 layer of silicon-based transfer layer bottom rewiring layer 212,2 layer of solder balls 222,2 layer of silicon-based cover layer top rewiring layer 223,2 layer of silicon-based cover layer insulating layer 224,2 layer of silicon-based cover layer 225,2 layer of silicon-based cover layer silicon through hole 226,2 layer of silicon-based cavity 227,2 layer of low-power radio-frequency chip 228,2 layer of silicon-based packaging wire 229,2 layer of silicon-based transfer layer top rewiring layer 230,2 layer silicon-based transfer layer 231,2 layer silicon-based transfer layer silicon through hole 232, and 2 layer silicon-based transfer layer bottom rewiring layer 233; the high/low temperature co-fired ceramic packaging layer 221 sequentially comprises heterogeneous interlayer solder balls 213, a high/low temperature co-fired ceramic cover plate 214, a high/low temperature co-fired ceramic cavity 215, a high/low temperature co-fired ceramic vertical through hole 216, a high-power radio frequency chip 217, a high/low temperature co-fired ceramic packaging bonding wire 218 and a high/low temperature co-fired ceramic base 219. The packaging structure can integrate more low-power radio frequency chips and improve the integration level of a system.
Example 2
The three-dimensional heterogeneous integrated radio frequency microsystem of the embodiment is packaged by adopting a 1-layer silicon-based packaging + 2-layer high/low temperature co-fired ceramic packaging structure, as shown in fig. 3, the three-dimensional heterogeneous integrated radio frequency microsystem is composed of a silicon-based packaging layer 320 and a high/low temperature co-fired ceramic packaging layer 321, from top to bottom, the silicon-based packaging layer 320 sequentially comprises solder balls 301, a silicon-based cover layer top redistribution layer 302, a silicon-based cover layer insulating layer 303, a silicon-based cover layer 304, a silicon-based cover layer silicon through hole 305, a silicon-based cavity 306, a low-power radio frequency chip 307, a silicon-based packaging bonding wire 308, a silicon-based transfer layer top redistribution layer 309, a silicon-based transfer layer 310, a silicon-based transfer layer silicon through hole 311 and a silicon-based transfer layer bottom redistribution layer 312; the high/low temperature co-fired ceramic package layer 321 sequentially comprises 2 layers of solder balls 313,2 layers of high/low temperature co-fired ceramic cover plates 314,2 layers of high/low temperature co-fired ceramic cavities 315,2 layers of high/low temperature co-fired ceramic vertical through holes 316,2 layers of high-power radio frequency chips 317,2 layers of high/low temperature co-fired ceramic package bonding wires 318,2 layers of high/low temperature co-fired ceramic bases 319,1 layer of solder balls 322,1 layer of high/low temperature co-fired ceramic cover plate 323,1 layer of high/low temperature co-fired ceramic cavities 324,1 layer of high/low temperature co-fired ceramic vertical through holes 325,1 layer of low power radio frequency chips 326,1 layer of high/low temperature co-fired ceramic package bonding wires 327 and 1 layer of high/low temperature co-fired ceramic bases 328. The layer 1 low power rf chip 326 may be a chip that is too thick to be integrated by using a silicon-based process, thereby expanding the variety of integrated chips.
According to the invention, a high/low temperature co-fired ceramic packaging process and a silicon-based packaging process are combined, so that a chip with a thicker thickness can be integrated by adopting the high/low temperature co-fired ceramic packaging process, and the integration level of the system is improved; compared with a silicon-based material, the high/low temperature co-fired ceramic has higher thermal expansion coefficient and thermal conductivity, and the two packaging processes are combined for use, so that the problem of reduced thermal reliability caused by a high-power radio frequency chip is solved, and the reliability of a system is improved.
The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the claims of the present invention.
Claims (7)
1. A three-dimensional heterogeneous integrated radio frequency microsystem is characterized by comprising a silicon-based packaging layer (120) and a high/low temperature co-fired ceramic packaging layer (121);
the silicon-based packaging layer (120) comprises a solder ball (101), a silicon-based cover layer top rewiring layer (102), a silicon-based cover layer insulating layer (103), a silicon-based cover layer (104), a silicon-based cover layer silicon through hole (105), a silicon-based cavity (106), a low-power radio-frequency chip (107), a silicon-based packaging bonding wire (108), a silicon-based switching layer top rewiring layer (109), a silicon-based switching layer (110), a silicon-based switching layer silicon through hole (111) and a silicon-based switching layer bottom rewiring layer (112) which are sequentially arranged;
the high/low temperature co-fired ceramic packaging layer (121) comprises heterogeneous interlayer solder balls (113), a high/low temperature co-fired ceramic cover plate (114), a high/low temperature co-fired ceramic cavity (115), high/low temperature co-fired ceramic vertical through holes (116), a high-power radio frequency chip (117), a high/low temperature co-fired ceramic packaging bonding wire (118) and a high/low temperature co-fired ceramic base (119) which are arranged in sequence;
the low-power radio frequency chip (107) is placed on a silicon-based switching layer (110), and connection of radio frequency signals, power signals and control signals is completed through a rewiring layer (109) on the top of the silicon-based switching layer and a silicon-based packaging bonding wire (108); the high-power radio frequency chip (117) is placed on the high/low temperature co-fired ceramic base (119), and the connection of radio frequency signals, power signals and control signals is completed through a high/low temperature co-fired ceramic packaging bonding wire (118) and the high/low temperature co-fired ceramic base (119).
2. The three-dimensional heterogeneous integrated radio frequency microsystem according to claim 1, wherein the high power radio frequency chip (117) is placed on a high/low temperature co-fired ceramic base (119), and signals are introduced on top of a high/low temperature co-fired ceramic encapsulation layer (121) through a high/low temperature co-fired ceramic encapsulation bonding wire (118), the high/low temperature co-fired ceramic base (119) and a high/low temperature co-fired ceramic vertical via (116), and then form signal interconnection with a silicon-based encapsulation layer (120).
3. The three-dimensional heterogeneous integrated radio frequency microsystem according to claim 1, wherein the high/low temperature co-fired ceramic submount (119) is free of ball-planting at the bottom.
4. The three-dimensional heterogeneous integrated radio frequency microsystem according to claim 1, characterized in that solder balls (101) are planted on the silicon-based cover layer top redistribution layer (102) in the silicon-based encapsulation layer (120), and the solder balls (101) are interconnected with an external motherboard.
5. The three-dimensional heterogeneous integrated radio frequency microsystem according to claim 1, wherein the silicon-based interposer bottom redistribution layer (112) in the silicon-based packaging layer (120) is provided with pads, and forms signal interconnection with the high/low temperature co-fired ceramic packaging layer (121) through heterogeneous inter-layer solder balls (113).
6. The three-dimensional heterogeneous integrated radio frequency microsystem as claimed in claim 1, wherein the silicon-based packaging layer (120) comprises N layers of solder balls (101), a silicon-based cover layer top redistribution layer (102), a silicon-based cover layer insulating layer (103), a silicon-based cover layer (104), a silicon-based cover layer through silicon via (105), a silicon-based cavity (106), a low-power radio frequency chip (107), a silicon-based packaging bonding wire (108), a silicon-based transition layer top redistribution layer (109), a silicon-based transition layer (110), a silicon-based transition layer through silicon via (111), and a silicon-based transition layer bottom redistribution layer (112), wherein signal interconnection is realized among the layers through solder, and N is greater than or equal to 1.
7. The three-dimensional heterogeneous integrated radio frequency microsystem according to claim 1, wherein the high/low temperature co-fired ceramic package layer (121) comprises N layers of heterogeneous inter-layer solder balls (113), a high/low temperature co-fired ceramic cover plate (114), a high/low temperature co-fired ceramic cavity (115), a high/low temperature co-fired ceramic vertical through hole (116), a high power radio frequency chip (117), a high/low temperature co-fired ceramic package bonding wire (118), and a high/low temperature co-fired ceramic base (119) to form an N layer of high/low temperature co-fired ceramic package, signal interconnection is realized between layers through solder, and N is greater than or equal to 1.
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