CN115910929A - Method for manufacturing CMOS integrated device - Google Patents
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Abstract
The invention provides a manufacturing method of a CMOS integrated device, which is applied to the technical field of semiconductors. Specifically, aiming at the problem that in the process that a 3.3VN/PwellPH and LDDPH4 layer photomask is removed in order to save photomasks (1P4M, 19ML) by an L90 process platform in the prior art, namely, 1.5V/3.3VCMOS tubes share a well photomask and an ion implantation IMP condition, and 1.5 VPLMVdd0pocketIMP (As 160 KeV) is used for penetrating GPL (gateply) to improve the device speed, the problem that the device stability of a CMOS integrated device is poor due to poor uniformity of a grid polysilicon film layer is provided, and the length of a side wall structure along the direction parallel to the surface of a semiconductor substrate can be flexibly adjusted by adopting an etching compensation process in the process of forming the side wall structure on the side wall of the grid structure, so that the effective length of a channel of the CMOS integrated device can be dynamically adjusted, and the stability of the CMOS integrated device is further stabilized.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semi-CMOS integrated device.
Background
With the continuous development of integrated circuit manufacturing technology, the requirement for the integration level of chips is also increasing, and a core MOS device (core MOS devices) and an input/output MOS device (I/o MOS devices) are required to be integrated in a chip manufactured by a CMOS process platform. Especially for input/output MOS devices, a plurality of input/output MOS devices are required to be integrated in a chip manufactured by a CMOS process platform, and the plurality of input/output MOS devices need to have different operating voltages to meet the requirement of chip adaptability. For example, it is necessary to provide input/output MOS devices having operating voltages of 1.5V and 3.3V at the same time. Also, in the integrated circuit sub-micron and deep sub-micron era, as the gate length/channel length decreases, major problems that need to be faced in the art include punch-through and channel electric fields, which can lead to hot carrier effects (HCI). Namely, the width of the depletion region extends into the channel, so that the effective channel length is narrowed, the equivalent electric field applied to the channel is increased, and channel carriers collide to increase and generate new electron-hole pairs, thereby forming a hot carrier doping effect. To suppress HCI, a depletion region width of a channel region is reduced by forming a Lightly Doped Drain (LDD) and a halo implant (PocketImplant) on a highly doped source/Drain.
However, for the above input/output MOS devices with different operating voltages, the requirements for the manufacturing processes are different, and if the compatibility between the processes is poor, the number of times of photolithography is increased, and the process cost is increased if the devices are manufactured separately. Therefore, in the prior art, in order to reduce the manufacturing cost of the input/output MOS devices with different operating voltages, the L90 process platform proposed to eliminate the 3.3VN/pwell ph and LDDPH4 layer masks in order to save masks (1p4m, 19ml), i.e., 1.5V/3.3VCMOS tubes share well masks and ion implantation IMP conditions, and the 3.3VNMOS uses 1.5 vplmdd0pocketimp (As 160 KeV) punch-through GPL (gateploy) to increase the device speed.
In particular, in the process of adjusting the threshold voltage and saturation current of the CMOS device by ion implantation through a halo ion implantation mask (PocketImplant) of the 1.5V PMOS device shared by the 3.3V NMOS device and the 1.5V PMOS device, which is proposed, since the ions of the halo ion implantation performed by the halo ion implantation pass through the gate and enter the channel, and the uniformity and thickness of the gate polysilicon film layer have an influence on the concentration of the ion implantation, the uniformity and thickness of the gate polysilicon film layer are particularly important for the device stability of the CMOS device, especially the 1.5V PMOS device.
Therefore, in the prior art, a method for forming a gate of a CMOS device at only one position of a furnace tube with poor uniformity can be used when forming an L90 platform, and the stability of the device of the formed CMOS integrated device cannot be guaranteed to meet the design requirements.
Disclosure of Invention
The invention aims to provide a manufacturing method of a CMOS integrated device, which aims to solve the technical problem that the stability of the CMOS integrated device is poor due to the fact that the thickness of a grid layer of a grid structure in the CMOS integrated device is not uniform by adopting a furnace tube in the prior art.
In order to solve the above technical problem, the present invention provides a method for manufacturing a CMOS integrated device, comprising the steps of:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first CMOS device area with low threshold voltage working voltage and a second CMOS device area with normal threshold voltage working voltage, each CMOS device area comprises a PMOS area and an NMOS area, and corresponding gate structures are formed on the semiconductor substrate of each PMOS area and each NMOS area;
forming a side wall material layer for burying each grid structure inside on the surface of the semiconductor substrate, and performing an etching compensation process on the side wall material layer to form corresponding side wall structures on the side walls of two sides of each grid structure, wherein the etching compensation process comprises main etching and over-etching with different etching duration;
forming a patterned photoresist layer on the surface of the semiconductor substrate, wherein a first injection window aligned with the PMOS region of the first CMOS device region and a second injection window aligned with the NMOS region of the second CMOS device region are formed in the photoresist layer;
and taking the photoresist layer and the grid structure as masks, and adopting N-type ions to carry out ion implantation on the semiconductor substrate below the first implantation window and the second implantation window so as to form an N-type halo ion implantation area in a PMOS area of the first CMOS device area and an N-type shallow doped ion implantation area in an NMOS area of the second CMOS device area.
Further, the operating voltage of the first CMOS device region may be 1.5V, and the operating voltage of the second CMOS device region may be 3.3V.
Further, the side wall material layer may be a combined film layer of an oxide layer, a nitride layer and an oxide layer, which are stacked in sequence.
Further, the step of performing an etching compensation process on the sidewall spacer material layer to form corresponding sidewall spacer structures on the sidewalls of the two sides of each gate structure may include:
determining a formula according to the thickness of a gate layer in the gate structure and preset etching compensation parameters, and determining main etching time and over-etching time required for forming the side wall structures on the side walls of the two sides of the gate structure;
and carrying out an etching compensation process on each grid structure according to the main etching time and the over-etching time, and forming corresponding side wall structures on the side walls of the two sides of each grid structure.
Further, the preset etching compensation parameter determination formula may be:
P i ×3+S i ×X％
wherein, P i The thickness of the grid layer of the MOS tube can be set as
The first influence factor of the grid layer on the device performance of the MOS tube is determined; s i The second influence factor of the etching compensation process on the device performance of the MOS transistor may be a ratio of the over-etching time in the etching compensation process to the total etching time of 1%, and X% may be a ratio of the over-etching time in the etching compensation process to the total etching time, where i is used to distinguish NMOS transistors or PMOS transistors corresponding to different operating voltages.
Further, the step of performing an etching compensation process on the sidewall spacer material layer to form corresponding sidewall spacer structures on the sidewalls of the two sides of each gate structure may include:
aiming at a PMOS region with working voltage of 1.5V, determining a first slope of a linear relation curve graph of saturation current of a PMOS tube and different thicknesses of a gate layer of the PMOS tube and a second slope of the linear relation curve graph of the saturation current and over-etching duration, and taking the first slope and the second slope as a first influence factor and a second influence factor to be substituted into a preset etching compensation parameter determination formula so as to determine a parameter value of X% when the value of the preset etching compensation parameter determination formula is zero;
and determining the main etching time and the over-etching time by utilizing the X% parameter value determined by the MOS tube of the PMOS region with the working voltage of 1.5V, and performing an etching compensation process on the side wall material layer so as to form corresponding side wall structures on the side walls of two sides of each grid structure.
Further, after the side wall structures are formed, a source region and a drain region are formed in the semiconductor substrate on two sides of each gate structure by using the side wall structures and the gate structures as masks.
Further, in the step of performing ion implantation on the semiconductor substrate below the first implantation window and the second implantation window by using N-type ions with the photoresist layer and the gate structure as masks, implantation energy of the N-type ion implantation may be: 150KeV to 190KeV, and the implantation dose can be 1E13 to 8E13.
Further, the N-type ions may include at least one of phosphorus, arsenic, and antimony.
Further, the thickness range of the gate layer in the gate structure may specifically be:
compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
in the manufacturing method of the CMOS integrated device, provided by the invention, aiming at the problem that in the process that an L90 process platform in the prior art shares a trap well photomask and an ion implantation IMP (ion implantation IMP) condition for saving photomasks (1P4M, 19ML), a scheme of removing a photomask with 3.3VN/PwellPH and an LDDPH4 layer photomask is provided, namely 1.5V/3.3VCMOS tubes, and 1.5 VPLD0pocketIMP (As 160 KeV) is used for punching through GPL (gateply) to improve the speed of the device, the problem of poor stability of the device of the CMOS integrated device is caused by poor uniformity of a grid polysilicon film layer.
Furthermore, because the side wall structure is formed by the specific etching compensation process, the channel length of the CMOS integrated device is effectively shortened, and the execution speed of the CMOS integrated device is accelerated.
Drawings
FIG. 1 is a flow chart illustrating a method for fabricating a CMOS integrated device in accordance with an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a gate structure formed in each MOS transistor in the L90 device platform and a sidewall structure located on two side walls thereof according to an embodiment of the present invention;
fig. 3 is a linear relationship graph of a mapping relationship between the saturation current and the thickness of the gate material layer of a PMOS transistor (abbreviated as 1.5VPMOS transistor) with an operating voltage of 1.5V according to an embodiment of the present invention;
fig. 4 is a linear relationship graph of a mapping relationship between the saturation current and the thickness of the gate material layer of an NMOS transistor (abbreviated as 1.5VNMOS transistor) with a working voltage of 1.5V according to an embodiment of the present invention;
fig. 5 is a linear relationship graph of a mapping relationship between the saturation current of a PMOS transistor with a 3.3V operating voltage (referred to as a 3.3VPMOS transistor for short) and the thickness of a gate material layer according to an embodiment of the present invention;
fig. 6 is a linear relationship graph of a mapping relationship between the saturation current and the thickness of the gate material layer of an NMOS transistor with a 3.3V operating voltage (referred to as a 3.3VNMOS transistor for short) according to an embodiment of the present invention;
fig. 7 is a linear relationship graph of a thickness mapping relationship between a saturation current and an over-etching time parameter of a PMOS transistor (referred to as a 1.5VPMOS transistor for short) having a working voltage of 1.5V according to an embodiment of the present invention;
fig. 8 is a linear relationship graph of a thickness mapping relationship between a saturation current and an over-etching time parameter of an NMOS transistor (abbreviated as a 1.5VNMOS transistor) with a working voltage of 1.5V according to an embodiment of the present invention;
fig. 9 is a linear relationship graph of a mapping relationship between saturation current and over-etching time parameters of a PMOS transistor (referred to as a 3.3VPMOS transistor for short) having a working voltage of 3.3V according to an embodiment of the present invention;
fig. 10 is a linear relationship graph of saturation current and over-etching time parameter of an NMOS transistor (abbreviated as 3.3VNMOS transistor) with a working voltage of 3.3V according to an embodiment of the present invention.
Detailed Description
As described in the background, in the prior art, in order to reduce the manufacturing cost of input/output MOS devices with different operating voltages, the L90 process platform proposed to eliminate the 3.3VN/pwell ph and LDDPH4 layer masks in order to save masks (1p4m, 19ml), i.e., 1.5V/3.3VCMOS transistors share well mask and IMP conditions for ion implantation, and the 3.3VNMOS used 1.5vpl dd0pocketimp (As 160 KeV) punch-through GPL (gateploy) to increase the device speed.
In particular, in the process of adjusting the threshold voltage and saturation current of the CMOS device by ion implantation through a halo ion implantation mask (PocketImplant) of the 1.5V PMOS device shared by the 3.3V NMOS device and the 1.5V PMOS device, which is proposed, since the ions of the halo ion implantation performed by the halo ion implantation pass through the gate and enter the channel, and the uniformity and thickness of the gate polysilicon film layer have an influence on the concentration of the ion implantation, the uniformity and thickness of the gate polysilicon film layer are particularly important for the device stability of the CMOS device, especially the 1.5V PMOS device.
Therefore, in the prior art, a method for forming a gate of a CMOS device at only one position of a furnace tube with poor uniformity can be used when forming an L90 platform, and the stability of the device of the formed CMOS integrated device cannot be guaranteed to meet the design requirements.
Therefore, the invention provides a manufacturing method of a CMOS integrated device, which aims to solve the technical problem that the stability of the device of the CMOS integrated device is poor due to the fact that the thickness of a grid layer of a grid structure in the CMOS integrated device is not uniform by adopting a furnace tube in the prior art.
The method for fabricating a CMOS integrated device according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided for the purpose of facilitating and clearly illustrating embodiments of the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" are intended to cover only the explicitly identified steps or elements as not constituting an exclusive list and that the method or apparatus may comprise further steps or elements. In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Referring specifically to fig. 1, fig. 1 is a schematic flow chart of a method for manufacturing a CMOS integrated device according to an embodiment of the present invention; the manufacturing method of the CMOS integrated device can comprise the following steps:
step S100, providing a semiconductor substrate, where the semiconductor substrate may include a first CMOS device region with a low threshold voltage and a second CMOS device region with a normal threshold voltage, and each CMOS device region may include one or more PMOS regions and NMOS regions, and corresponding gate structures are formed on the semiconductor substrate of each PMOS region and NMOS region. In particular, the semiconductor substrate may be any suitable substrate known in the art, and may be, for example, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, and further includes a multilayer structure composed of these semiconductors, or may be Silicon On Insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or may be double-side polished silicon wafers (double side polished wafers (DSP), or may be a ceramic substrate such as alumina, quartz, or a glass substrate. Illustratively, the semiconductor substrate in this embodiment is, for example, a silicon wafer. And the working voltage of the first CMOS device area is 1.5V, and the working voltage of the second CMOS device area is 3.3V.
It should be noted that, in practical applications, a plurality of chips manufactured by the CMOS process platform are required to be integrated, and a plurality of input/output CMOS devices are required to have different operating voltages to meet the requirement of chip adaptability. Among them, there are some chip designs that require a special 1.5V CMOS device, which is called a low threshold voltage CMOS device in the embodiment of the present invention, wherein the threshold voltage of the low threshold voltage CMOS device is 200mV to 300mV smaller than that of a normal 3.3V CMOS device (called a normal threshold voltage CMOS device), so as to meet the actual design requirements.
In this embodiment, a plurality of N-type wells (not shown) for subsequently forming PMOS regions and P-type wells (not shown) for forming NMOS regions in the respective CMOS device regions may be formed in the semiconductor substrate, and adjacent N-type wells and P-type wells are isolated by shallow trenches (not shown). In the forming process of the L90 device, the semiconductor substrate used for integrally forming the CMOS tube containing the working voltage of 1.5V and the CMOS tube containing the working voltage of 3.3V shares the conditions of a well mask and IMP when forming the N-type well and the P-type well of a PMOS area and an NMOS area. Also, the 3.3VNMOS uses 1.5vpl dd0pocketimp (As 160 KeV) punch-through GPL (gateploy) to boost speed.
Then, forming corresponding gate structures on the semiconductor substrate of each PMOS region and each NMOS region by using a deposition process and an etching process based on the existing furnace tube, wherein the thickness ranges of the gate material layers in the corresponding gate structures formed on the semiconductor substrate of each PMOS region and each NMOS region formed by using the method along the direction vertical to the surface of the semiconductor substrate are as follows:
that is, it may be specifically
Preferably, in the forming process of the L90 device, the target thickness of the gate structure correspondingly formed in each MOS transistor region is ^ greater or less>
However, the current L90 platform can only utilize one position of the furnace tube to improve the uniformity of the thickness of the gate material layer in the gate structure, and therefore, in the semiconductor process of the current L90 device platform, the thickness of the gate material layer of the formed gate structure is not uniform, which does not meet the design requirement.
Based on this, the inventor of the present invention proposes that after the gate structures of each MOS transistor region are formed, when the sidewall structures on the sidewalls of each of the gate structures are formed, an etching compensation process with controllable main etching time and over etching time is used, and by controlling etching parameters of the etching compensation process, the lengths of the sidewall structures formed on the sidewalls of the gate structures in the direction parallel to the surface of the semiconductor substrate are controlled, as shown in a in fig. 2, so as to control the source/drain regions of each MOS transistor and the Overlap of the gate (where the source/drain regions of the MOS transistor and the projection of the gate in the semiconductor substrate Overlap), for example, as shown in b in fig. 2. Due to the short channel effect, the length spacer of the C-side wall structure in the direction parallel to the surface of the semiconductor substrate is smaller, the position where the source-drain region of the MOS tube and the projection part of the grid electrode in the semiconductor substrate are overlapped is larger, the effective length of the grid electrode gate is reduced, and the device runs fast, namely, the purpose of ensuring the performance of the device is achieved.
Step S200, forming a side wall material layer for burying each grid structure inside on the surface of the semiconductor substrate, and carrying out an etching compensation process on the side wall material layer to form corresponding side wall structures on the side walls of two sides of each grid structure, wherein the etching compensation process comprises main etching and over-etching with different etching duration.
In this embodiment, after the gate structure of each MOS transistor is formed in step S100, a sidewall material layer with a certain thickness may be deposited on the surface of the entire semiconductor substrate, where the sidewall material layer may be a three-layer film structure composed of an oxide, a nitride, and an oxide, and then the etching compensation process provided by the present invention is performed on the sidewall material layer, so that a sidewall structure with a preset target length, which is the length spacer in a direction parallel to the surface of the semiconductor substrate, is formed on the sidewalls of both sides of the gate structure of each MOS transistor. The etching compensation process specifically includes main etching and over-etching with different etching durations, for example, main etching with an etching duration of T1 and over-etching OE with an etching duration of T2.
As an example, in an embodiment of the present invention, a specific implementation manner of forming each sidewall structure by using the etching compensation process proposed in the present invention is provided, and the following steps may be specifically performed:
step S201, determining a formula according to the thickness of the gate layer in the gate structure and a preset etching compensation parameter, and determining the main etching time and the over-etching time required for forming the side wall structures on the two side walls of the gate structure.
In this embodiment, when the inventor researches device performance of an L90 device platform, the inventor finds that, in order to save a mask and simplify a process flow in the existing process of the L90 device platform, in the process of adjusting a threshold voltage and a saturation current of a CMOS device by using a PLDD0 ion implantation process of a PMOS transistor with an operating voltage of 1.5V, ions implanted by halo ions of the L90 device platform penetrate through a gate and enter a channel, and uniformity and thickness of a gate polysilicon film layer influence concentration of the ion implantation, so that the uniformity and thickness of the gate polysilicon film layer are particularly important for device stability of a CMO S device, especially a PMOS device with an operating voltage of 1.5V. Therefore, when the device performance of the PMOS transistor with the operating voltage of 1.5V is affected by the thickness of the gate material layer in the gate structure to be eliminated to 0, the device performance of the remaining three devices (1.5V NMOS, 3.3V PMOS, and 3.3V NMOS) is also affected by the thickness of the gate material layer in the gate structure to be reduced accordingly, and becomes more stable.
Based on this, the inventor of the present invention proposes a manner that a main etching time parameter and an over-etching time parameter, which are also determined by an etching compensation process for forming sidewall structures on both side walls of a gate structure of a PMOS device with a working voltage of 1.5V, are used as specific parameters of an etching compensation process for three other device devices (1.5V NMOS, 3.3V PM OS, and 3.3V NMOS), so as to eliminate the influence of the thickness of a gate material layer on the device performance.
Specifically, the thickness range of the gate material layer of the gate structure of each MOS transistor formed based on the existing L90 device platform
The invention will pick the thickness>
The first gear is used as feed forward, the thickness range of the grid material layer is divided into 9 gears, and then, the determination is proposedA preset etching compensation parameter determination formula for reflecting an influence factor of the thickness range on the MOS transistor is specifically as follows:
P i ×3+S i ×X％(1)
wherein, P i The thickness of the grid layer of the MOS tube is
The first influence factor of the grid layer on the device performance of the MOS tube is determined; s i When the proportion of the over-etching time in the etching compensation process to the total etching time is 1%, the etching compensation process has a second influence factor on the device performance of the MOS tube, and X% is the proportion of the over-etching time in the etching compensation process to the total etching time, wherein i is used for distinguishing NMOS tubes or PMOS tubes corresponding to different working voltages.
It should be noted that, as can be seen from the above formula description, in the embodiment of the present invention, when the over-etching time parameter in the respective etching compensation process of the PMOS transistor and the NMOS transistor with the 1.5V operating voltage and the PMOS transistor and the NMOS transistor with the 3.3V operating voltage in the L90 platform is solved, the above formula (1) is used to solve the overall problem, but for each MOS transistor with different operating voltages, the corresponding P transistor is used to solve the over-etching time parameter i And S i All being different, i.e. P for PMOS tubes with an operating voltage of 1.5V i And S i Are each K P And K s P of NMOS tube with 1.5V working voltage i And S i Are respectively A P And A s P of NMOS tube with 3.3V working voltage i And S i Are respectively B P And B s P of PMOS tube with 3.3V working voltage i And S i Are each C P And C s . The preset etching compensation parameter determination formulas of the PMOS tube and the NMOS tube with 1.5V working voltage and the PMOS tube and the NMOS tube with 3.3V working voltage in the L90 platform, which are further obtained and reflect the influence factors of the thickness range on the MOS tube, are also different.
The following formulas for determining the preset etching compensation parameters of each MOS transistor, which reflect the influence factors of the thickness range on the MOS transistor, may be:
K P ×3+K S ×X％(2)
A P ×3+A S ×X％(3)
B P ×3+B S ×X％(4)
C P ×3+C S ×X％(5)
wherein, K P 、A P 、B P And C P The thickness of the grid layer of the 1.5VPMOS tube, the 1.5VNMOS tube, the 3.3VNMOS tube and the 3.3VPMOS tube is equal to
When the MOS transistor is used, a first influence factor corresponding to the device performance of each MOS transistor is influenced by the gate layer; k s 、A s 、B s And C s When the proportion of the over-etching time in the etching compensation process to the total etching time is 1%, the etching compensation process has a second influence factor corresponding to the device performance of the 1.5VPMOS tube, the 1.5VNMOS tube, the 3.3VNMOS tube and the 3.3VPMOS tube, and X% is the proportion of the over-etching time in the etching compensation process to the total etching time.
As an example, in the embodiment of the present invention, it is specifically provided how to solve the first influence factor (K) corresponding to each MOS transistor described above P 、A P 、B P And C P ) And said second influencing factor (K) s 、A s 、B s And C s ) The implementation method specifically comprises the following steps:
the thickness values of the gate material layers of different gate structures of each MOS transistor and the current values of the saturation currents of the corresponding MOS devices are respectively collected, and then the linear relationship curve graphs of the mapping relationships between the saturation currents of the devices corresponding to the 1.5VPMOS transistor, the 1.5VNMOS transistor, the 3.3VNMOS transistor, and the 3.3VPMOS transistor and the thickness of the gate material layers are respectively drawn by using the collected values, as shown in fig. 3 to 6. Fig. 3 is a linear relationship graph of a mapping relationship between a saturation current of a PMOS transistor (referred to as a 1.5VPMOS transistor for short) having a working voltage of 1.5V and a thickness of a gate material layer according to an embodiment of the present invention; fig. 4 is a linear relationship graph of a mapping relationship between the saturation current and the thickness of the gate material layer of an NMOS transistor (abbreviated as 1.5VNMOS transistor) with a working voltage of 1.5V according to an embodiment of the present invention; fig. 5 is a linear relationship graph of a mapping relationship between the saturation current and the thickness of the gate material layer of a PMOS transistor (referred to as 3.3VPMOS transistor) with an operating voltage of 3.3V according to an embodiment of the present invention; fig. 6 is a linear relationship graph of the saturation current of the NMOS transistor with 3.3V operating voltage (referred to as 3.3VNMOS transistor for short) and the thickness mapping relationship of the gate material layer according to an embodiment of the present invention.
Further, after the linear graphs of the mapping relationship between the saturation current and the thickness of the gate material layer as shown in fig. 3 to 6 are plotted, the slope of each of the linear graphs, i.e., the first slope, i.e., the first influence factor (K) can be obtained P 、A P 、B P And C P )。
Similarly, the values of the overetching time parameter of each MOS transistor with different sidewall structures and the current value of the saturation current of the corresponding MOS device may be respectively collected, and then the linear relationship curve of the mapping relationship between the saturation current and the overetching etching time of the corresponding device of each of the 1.5VPMOS transistor, the 1.5VNMOS transistor, the 3.3VNMOS transistor, and the 3.3VPMOS transistor may be respectively drawn by using the collected values, as shown in fig. 7 to fig. 10. Fig. 7 is a linear relationship graph of a thickness mapping relationship between saturation current and over-etching time parameter of a PMOS transistor (referred to as a 1.5VPMOS transistor for short) with a working voltage of 1.5V according to an embodiment of the present invention; fig. 8 is a linear relationship graph of a thickness mapping relationship between a saturation current and an over-etching time parameter of an NMOS transistor (abbreviated as a 1.5VNMOS transistor) with a working voltage of 1.5V according to an embodiment of the present invention; fig. 9 is a linear relationship graph of a mapping relationship between saturation current and over-etching time parameters of a PMOS transistor (referred to as a 3.3VPMOS transistor for short) with a working voltage of 3.3V according to an embodiment of the present invention; fig. 10 is a linear relationship graph of saturation current and over-etching time parameter of an NMOS transistor (abbreviated as 3.3VNMOS transistor) with a working voltage of 3.3V according to an embodiment of the present invention.
Further, the saturation current is plotted as shown in FIGS. 7 to 10After the linear relation curve graphs of the mapping relation with the over-etching time parameters are obtained, the slope of each linear relation curve graph, namely the second slope, namely the second influence factor (K) can be obtained s 、A s 、B s And C s )。
Further, the first influence factor (K) included in the equations (2) to (5) is solved by the above-mentioned steps P 、A P 、B P And C P ) And said second influencing factor (K) s 、A s 、B s And C s ) Then, under the condition that the value of the equation of the preset etching compensation parameter determination formula (2) corresponding to the PMOS region with the working voltage of 1.5V is set to be zero, the parameter value of the percentage of the over-etching time OE in the etching compensation process for forming the sidewall structures on the sidewalls at the two sides of the gate structure, which is provided by the invention, to the total etching time, which is X%, can be solved. Then, the X% parameter value is substituted into the formulas (3) to (5), so that the influence on the devices of the PMOS transistor and the NMOS transistor with the working voltage of 1.5V and the PMOS transistor and the NMOS transistor with the working voltage of 3.3V in the L90 platform can be determined under the condition that different X% parameter values are adopted, and accordingly, when the number of the X% parameter values obtained by the PMOS transistors with the working voltage of 1.5V is too small, the influence on the device performance caused by the thickness fluctuation of the gate material layer in the gate structure can be compensated by the corresponding etching compensation process. Illustratively, according to the above principle, the inventor of the present invention has found that when the parameter X% of the PMOS transistor with 1.5V operating voltage is 2%, it can compensate
The device performance improvement ratio improvement is 100%. When the parameter value is adopted, the device performance improvement rates of the devices of other three devices are respectively as shown in the following table 1:
TABLE 1
As can be seen from Table 1, K is found when the parameter X% is 2% P ＝-1.43，A P ＝-2.3，B P ＝-2.7，C P ＝-0.47，K s ＝2.31，A s ＝4.45，B s ＝2.3，C s =1.14. Therefore, by substituting the parameter values into the above equations (2) to (5), K can be obtained P ×3+K S ×X％＝0，A P ×3+A S ×X％＝0.67，B P ×3+B S ×X％＝1.17，C P ×3+C S X% =0.29, so that the improvement rates of the device performance of each MOS transistor by the method provided by the present invention are respectively as follows: 100% (1.5 VPMOS), 71% (1.5 VNMOS), 38% (3.3 VPMOS) and 57% (3.3 VNMOS).
Obviously, by using the method provided by the invention, namely, by adopting the etching compensation process mode in the process of forming the side wall structure on the side wall of the gate structure, the length of the side wall structure along the direction parallel to the surface of the semiconductor substrate is flexibly adjusted, so that the purposes of dynamically adjusting the effective length of the channel of the CMOS integrated device and finally stabilizing the stability of the CMOS integrated device are achieved. In addition, the side wall structure is formed by a specific etching compensation process, so that the channel length of the CMOS integrated device is effectively shortened, and the execution speed of the CMOS integrated device is accelerated.
Step S202, etching compensation process is carried out on each grid structure according to the main etching time and the over-etching time, and corresponding side wall structures are formed on the two side walls of each grid structure.
In this embodiment, when the parameter X% is determined in step S201, it is determined that the percentage of the over-etching time in the etching compensation process to the total etching time is a percentage, so that only in the actual etching process, the percentage of the over-etching time performed by the sidewall material layer to be etched and removed and the total etching time satisfy the percentage, which is not specifically limited in the present invention.
It should be noted that, in the embodiments of the present invention, the material of the sidewall structure is only exemplarily selected to be an ONO stacked film layer composed of an oxide-nitride-oxide, and in other embodiments, the sidewall structure may also be a sidewall material layer composed of an oxide or a nitride alone, for example, silicon dioxide or silicon nitride. In addition, the parameter X% described in the present invention is only an exemplary percentage of the over-etching time in the etching compensation process to the total etching time, and may also be other parameters of the etching process in other embodiments, for example, the percentage of the thickness of the over-etched removed spacer material layer in the etching compensation process to the thickness of the total etched removed spacer material layer.
Step S300, forming a patterned photoresist layer on the surface of the semiconductor substrate, where a first injection window aligned with the PMOS region of the first CMOS device region and a second injection window aligned with the NMOS region of the second CMOS device region are formed in the photoresist layer.
Step S400, taking the photoresist layer and the grid structure as masks, and adopting N-type ions to carry out ion implantation on the semiconductor substrate below the first implantation window and the second implantation window so as to form an N-type halo ion implantation area in a PMOS area of the first CMOS device area and an N-type shallow doped ion implantation area in an NMOS area of the second CMOS device area.
In this embodiment, after the sidewall structures on both sides of the gate structure in each MOS transistor are formed in step S200, the lightly doped drain LDD and halo ion doped region Pocket of each MOS transistor, and the source/drain region S/D may be correspondingly formed. In the L90 platform, in order to save the masks (1p4m, 19ml), a solution of removing 3.3VN/PwellPH and LDDPH4 layer masks is proposed, i.e., 1.5V/3.3VCMOS tubes share well masks and ion implantation IMP conditions, and 3.3VNMOS uses 1.5vpl dd0pocketimp (As 160 KeV) to punch through GPL (gateploy) to increase the device speed. For example, the proposed process for performing ion implantation through a halo ion implantation mask (Pocket Implant) of a PMOS device with 1.5V shared by an NMOS device with 3.3V and a PMOS device with 1.5V may specifically be: a patterned photoresist layer (not shown) is formed on the surface of the semiconductor substrate, and a first implantation window aligned with the 1.5V PMOS region and a second implantation window aligned with the 3.3V NMOS region are formed in the photoresist layer. And then, taking the photoresist layer and the grid structure as masks, and carrying out ion implantation on the semiconductor substrate below the first implantation window and the second implantation window by adopting N-type ions so as to form an N-type halo ion implantation area in the 1.5V PMOS area and an N-type shallow doped ion implantation area in the 3.3V NMOS area. Of course, there are other LDD and Pocket regions that form other devices, and the invention will not be described in detail.
Further, in the step of performing ion implantation on the semiconductor substrate below the first implantation window and the second implantation window by using N-type ions with the photoresist layer and the gate structure as masks, implantation energy of the N-type ion implantation may be: 150KeV to 190KeV, and preferably 160KeV, and the implantation dose may be 1E13 to 8E13, and specifically it may be 1E13, 2E13, 3E13, 4E13, 5E13, 6E13, 7E13 and 8E13. And the N-type ions may include at least one of phosphorus, arsenic, and antimony. Preferably, the N-type ion is arsenic.
In summary, in the manufacturing method of the CMOS integrated device provided by the present invention, for saving the masks (1p4m, 19ml) in the L90 process platform in the prior art, a scheme of removing the masks with 3.3VN/PwellPH and LDDPH4 layers is proposed, that is, the 1.5V/3.3VCMOS tube shares the well mask and the IMP condition, and the 3.3VNMOS tube uses 1.5 vplmdpolycket IMP (As 160 KeV) to punch through GPL (gateploy) to increase the device speed, because the uniformity of the gate polysilicon film layer is poor, the device stability of the CMOS integrated device is poor, and a method of using an etching compensation process in the process of forming the sidewall structure on the sidewall of the gate structure is proposed to flexibly adjust the length of the sidewall structure along the direction parallel to the surface of the semiconductor substrate, so As to dynamically adjust the effective length of the channel of the CMOS integrated device, and further stabilize the stability of the CMOS integrated device.
Furthermore, the side wall structure is formed by a specific etching compensation process, so that the channel length of the CMOS integrated device is effectively shortened, and the execution speed of the CMOS integrated device is accelerated.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art that many changes and modifications can be made, or equivalents employed, to the presently disclosed embodiments without departing from the intended scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.
Claims (10)
1. A method for manufacturing a CMOS integrated device, comprising the steps of:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first CMOS device area with low threshold voltage working voltage and a second CMOS device area with normal threshold voltage working voltage, each CMOS device area comprises a PMOS area and an NMOS area, and corresponding gate structures are formed on the semiconductor substrate of each PMOS area and each NMOS area;
forming a side wall material layer for burying each grid structure inside on the surface of the semiconductor substrate, and performing an etching compensation process on the side wall material layer to form corresponding side wall structures on the side walls of two sides of each grid structure, wherein the etching compensation process comprises main etching and over-etching with different etching duration;
forming a patterned photoresist layer on the surface of the semiconductor substrate, wherein a first injection window aligned with the PMOS area of the first CMOS device area and a second injection window aligned with the NMOS area of the second CMOS device area are formed in the photoresist layer;
and taking the photoresist layer and the grid structure as masks, and adopting N-type ions to carry out ion implantation on the semiconductor substrate below the first implantation window and the second implantation window so as to form an N-type halo ion implantation area in a PMOS area of the first CMOS device area and an N-type shallow doped ion implantation area in an NMOS area of the second CMOS device area.
2. The method of fabricating the CMOS integrated device of claim 1, wherein the operating voltage of the first CMOS device region is 1.5V and the operating voltage of the second CMOS device region is 3.3V.
3. The method for manufacturing the CMOS integrated device according to claim 1, wherein the spacer material layer is a combined film of an oxide layer-a nitride layer-an oxide layer that are stacked in sequence.
4. The method for manufacturing the CMOS integrated device according to claim 2, wherein the step of performing an etching compensation process on the spacer material layer to form corresponding spacer structures on sidewalls on both sides of each of the gate structures comprises:
determining a formula according to the thickness of a gate layer in the gate structure and preset etching compensation parameters, and determining main etching time and over-etching time required for forming the side wall structures on the side walls of the two sides of the gate structure;
and carrying out etching compensation process on each grid structure according to the main etching time and the over-etching time, and forming corresponding side wall structures on the side walls of the two sides of each grid structure.
5. The method for manufacturing a CMOS integrated device according to claim 4, wherein the preset etch compensation parameter determination formula is:
P i ×3+S i ×X％
wherein, P i The thickness of the grid layer of the MOS tube is
When the MOS transistor is used, a first influence factor of the grid layer on the device performance of the MOS transistor is generated; s i When the proportion of the over-etching time in the etching compensation process to the total etching time is 1%, the etching compensation process has a second influence factor on the device performance of the MOS tube, and X% is the proportion of the over-etching time in the etching compensation process to the total etching time, wherein i is used for distinguishing NMOS tubes or PMOS tubes corresponding to different working voltages.
6. The method for manufacturing the CMOS integrated device according to claim 5, wherein the step of performing an etching compensation process on the spacer material layer to form corresponding spacer structures on sidewalls of both sides of each of the gate structures comprises:
aiming at a PMOS region with working voltage of 1.5V, determining a first slope of a linear relation curve graph of saturation current of a PMOS tube and different thicknesses of a gate layer of the PMOS tube and a second slope of the linear relation curve graph of the saturation current and over-etching duration, and taking the first slope and the second slope as a first influence factor and a second influence factor to be substituted into a preset etching compensation parameter determination formula so as to determine a parameter value of X% when the value of the preset etching compensation parameter determination formula is zero;
and determining the main etching time and the over-etching time by utilizing the X% parameter value determined by the MOS tube of the PMOS region with the working voltage of 1.5V, and performing an etching compensation process on the side wall material layer so as to form corresponding side wall structures on the side walls of two sides of each grid structure.
7. The method for manufacturing the CMOS integrated device according to claim 6, wherein after the sidewall structures are formed, a source region and a drain region are formed in the semiconductor substrate on both sides of each of the gate structures, using the sidewall structures and the gate structures as masks.
8. The method of manufacturing a CMOS integrated device according to claim 1, wherein in the step of performing ion implantation on the semiconductor substrate under the first and second implantation windows using N-type ions with the photoresist layer and the gate structure as a mask, implantation energy of the N-type ion implantation is: 150 KeV-190 KeV, and the implantation dosage is 1E 13-8E 13.
9. The method of fabricating the CMOS integrated device of claim 8, wherein the N-type ions comprise at least one of phosphorus, arsenic, and antimony.
10. The method of fabricating the CMOS integrated device of claim 1, wherein a thickness of the gate layer in the gate structure ranges from:
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