CN115910795A - Shielding gate power device and preparation method thereof - Google Patents
Shielding gate power device and preparation method thereof Download PDFInfo
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- CN115910795A CN115910795A CN202211527863.5A CN202211527863A CN115910795A CN 115910795 A CN115910795 A CN 115910795A CN 202211527863 A CN202211527863 A CN 202211527863A CN 115910795 A CN115910795 A CN 115910795A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention provides a shielded gate power device and a preparation method thereof, wherein the shielded gate power device comprises a semiconductor layer, a dielectric layer, a shielded gate layer, a gate dielectric layer, a gate conducting layer, an interlayer dielectric layer, a blocking layer, a contact hole and a source electrode, wherein the upper surface layer of the semiconductor layer is provided with a plurality of grooves which are arranged at intervals; the dielectric layer is positioned on the inner wall and the bottom surface of the groove; the shielding gate layer is positioned in the groove; the gate dielectric layer covers the inner wall of the groove, the upper surface of the dielectric layer and the exposed surface of the shielding gate layer; the grid conducting layer fills the groove; the interlayer dielectric layer covers the upper surfaces of the gate dielectric layer and the gate conducting layer, and a plurality of first through holes penetrating through the interlayer dielectric layer are formed in the interlayer dielectric layer; the plugging layer plugs the opening of the first through hole, and the bottom surface of the plugging layer is away from the upper surface of the interlayer dielectric layer by a preset distance; the contact hole penetrates through the interlayer dielectric layer; and the source electrode fills the contact hole. According to the invention, the cavity structure is arranged in the interlayer dielectric layer, so that the gate-source parasitic capacitance of the device is reduced, and the switching speed of the device is increased.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a shielded gate power device and a preparation method thereof.
Background
In a power MOSFET device, due to the advantages of a shielded gate trench MOSFET, such as lower on-resistance and faster switching speed, compared to a conventional trench MOSFET, more and more attention is paid. As shown in fig. 1 and 2, each of the cross-sectional structure diagrams of the shielded gate trench MOSFET and the other cross-sectional structure diagram of the shielded gate trench MOSFET includes a semiconductor Layer 01, a trench 011, a Dielectric Layer 012, a shielded gate Layer 013, a gate Dielectric Layer 02, an isolation Dielectric Layer 03, a gate conductive Layer 04, an interlayer Dielectric Layer 05, a contact hole 051 and a source 06, wherein the source of the shielded gate trench MOSFET covers the upper surface of the interlayer Dielectric Layer (Inter Layer Dielectric, abbreviated as ILD) above the gate conductive Layer, that is, the interlayer Dielectric Layer is located between the source and the gate, so that the facing area between the gate and the source is increased, and the gate-source parasitic capacitance C between the gate and the source is caused gs The input capacitance of the device is increased, so that the switching speed of the device is reduced, and the switching loss of the device is increased.
At present, the gate-source parasitic capacitance between a gate and a source is usually reduced by increasing the thickness of an interlayer dielectric layer, but as the interlayer dielectric layer is thickened, the aspect ratio of a contact hole is increased, the difficulty of a filling process of the contact hole is increased, the quality of the source for filling the contact hole is reduced, and the reliability of a device is also reduced.
Therefore, a shielded gate power device which does not need to reduce the gate-source parasitic capacitance of the device by increasing the thickness of the interlayer dielectric layer is urgently needed to be found.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a shielded gate power device and a manufacturing method thereof, for solving the problem of difficulty in filling a contact hole due to reduction of gate-source parasitic capacitance by increasing the thickness of an interlayer dielectric layer in the shielded gate power device in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a method for manufacturing a shielded gate power device, including the steps of:
providing a semiconductor layer, wherein the upper surface layer of the semiconductor layer is provided with a plurality of grooves with upward openings and arranged at intervals along the X direction;
sequentially forming a dielectric layer positioned on the inner wall and the bottom surface of the groove and the shielding gate layer positioned in the groove, wherein the dielectric layer wraps the side wall and the bottom surface of the shielding gate layer, and the upper surface of the dielectric layer is lower than the upper surface of the shielding gate layer;
forming a gate dielectric layer covering the inner wall of the groove, the upper surface of the dielectric layer and the exposed surface of the shielding gate layer, and forming a gate conducting layer filling the groove, wherein the gate dielectric layer wraps the side wall and the bottom surface of the gate conducting layer;
forming an interlayer dielectric layer covering the gate dielectric layer and the upper surface of the gate conducting layer, and forming a plurality of first through holes and a plurality of second through holes penetrating through the interlayer dielectric layer, wherein the bottom surfaces of the first through holes expose the upper surface of the gate conducting layer, and the bottom surfaces of the second through holes expose the upper surface of the semiconductor layer between two adjacent grooves;
forming a blocking layer on the exposed surface of the interlayer dielectric layer to obtain a cavity structure consisting of the blocking layer, the first through hole and the gate conductive layer, extending the bottom surface of the blocking layer in the first through hole to a position away from the upper surface of the interlayer dielectric layer by a preset distance, and thinning the blocking layer;
forming a contact hole based on the second through hole, and forming a source electrode filling the contact hole.
Optionally, after the gate conductive layer is formed and before the interlayer dielectric layer is formed, a step of forming a first conductive type source region and a second conductive type base region on the upper surface of the semiconductor layer between two adjacent trenches is further included, where the source region is located on the upper surface of the base region.
Optionally, a lower surface of the gate conductive layer is lower than a lower surface of the base region.
Optionally, the method for forming the first through hole includes dry etching.
Optionally, the method for forming the blocking layer comprises chemical vapor deposition and physical vapor deposition.
The present invention also provides a power MOSFET comprising:
the upper surface layer of the semiconductor layer is provided with a plurality of grooves with upward openings and arranged at intervals along the X direction;
the dielectric layer is positioned on the inner wall and the bottom surface of the groove;
the shielding grid layer is positioned in the groove, the dielectric layer wraps the side wall and the bottom surface of the shielding grid layer, and the upper surface of the dielectric layer is lower than the upper surface of the shielding grid layer;
the gate dielectric layer covers the inner wall of the groove, the upper surface of the dielectric layer and the exposed surface of the shielding gate layer;
the grid conducting layer is filled in the groove, and the side wall and the bottom surface of the grid conducting layer are wrapped by the grid dielectric layer;
the interlayer dielectric layer covers the upper surfaces of the gate dielectric layer and the gate conducting layer, and a plurality of first through holes which penetrate through the interlayer dielectric layer and expose the upper surface of the gate conducting layer are formed in the interlayer dielectric layer;
the blocking layer blocks the opening of the first through hole, the bottom surface of the blocking layer is away from the upper surface of the interlayer dielectric layer by a preset distance, and the blocking layer, the first through hole and the grid conducting layer form a cavity structure;
the contact hole penetrates through the interlayer dielectric layer positioned above the semiconductor layer between every two adjacent grooves;
and the source electrode fills the contact hole.
Optionally, an aspect ratio of the first via is greater than an aspect ratio of the trench, and the aspect ratio of the first via is greater than an aspect ratio of the contact hole.
Optionally, the opening shape of the first through hole includes a circle and a quadrangle.
Optionally, the first through holes are arranged in an array.
Optionally, a first conductivity type source region and a second conductivity type base region are further disposed on the upper surface of the semiconductor layer between two adjacent trenches, and the source region is located on the upper surface of the base region.
As described above, according to the shielded gate power device and the manufacturing method thereof of the invention, the plurality of first through holes penetrating through the interlayer dielectric layer and having a high aspect ratio are arranged in the interlayer dielectric layer region above the gate conductive layer, and the blocking layer for blocking the opening of the first through hole is formed, the blocking layer, the first through hole and the gate conductive layer surround the cavity structure, and the cavity part of the cavity structure is a vacuum cavity or an air cavity, so that the dielectric property of the interlayer dielectric layer above the gate conductive layer is reduced, and then the effective dielectric constant value of the dielectric medium between the source electrode and the gate electrode is reduced, and the gate source parasitic capacitance of the device is reduced, thereby increasing the switching speed of the device and reducing the switching loss of the device; due to the cavity structure, the gate-source parasitic capacitance of the device is reduced, the distance between the gate conducting layer and the source electrode is increased without increasing the thickness of the interlayer dielectric layer, so that the gate-source parasitic capacitance of the device is reduced, the depth-to-width ratio of the contact hole is ensured, the filling difficulty of the source electrode for filling the contact hole is reduced, the quality of the source electrode for filling the contact hole is improved, the reliability of the device is improved, and the cavity structure has high industrial utilization value.
Drawings
Fig. 1 is a schematic cross-sectional view of a trench portion of a shielded gate trench MOSFET.
Fig. 2 shows another cross-sectional structure schematic of the trench portion of a shielded gate trench MOSFET.
Fig. 3 is a process flow diagram of a method for manufacturing a shielded gate power device according to the present invention.
Fig. 4 is a schematic cross-sectional view of a semiconductor layer of the method for manufacturing a shielded gate power device according to the present invention.
Fig. 5 is a schematic cross-sectional view illustrating a dielectric material layer formed in the method for manufacturing a shielded gate power device according to the present invention.
Fig. 6 is a schematic cross-sectional structure diagram of the method for manufacturing a shielded gate power device according to the present invention after forming a shielded gate material layer.
Fig. 7 is a schematic cross-sectional view illustrating a dielectric layer formed after the manufacturing method of the shielded gate power device according to the present invention.
Fig. 8 is a schematic cross-sectional structural view after a gate dielectric layer is formed according to the method for manufacturing a shielded gate power device of the present invention.
Fig. 9 is a schematic cross-sectional view illustrating a gate conductive material layer formed by the method for manufacturing a shielded gate power device according to the present invention.
Fig. 10 is a schematic cross-sectional view illustrating a gate conductive layer formed by the method for manufacturing a shielded gate power device according to the present invention.
Fig. 11 is a schematic cross-sectional view illustrating a first through hole formed by the method for manufacturing a shielded gate power device according to the present invention.
Fig. 12 is a schematic top view of an interlayer dielectric layer located above a gate conductive layer after a first via hole is formed according to the method for manufacturing a shielded gate power device of the present invention.
Fig. 13 is a schematic cross-sectional view illustrating a contact hole formed in the method for manufacturing a shielded gate power device according to the present invention.
Fig. 14 is a schematic cross-sectional view illustrating a source electrode formed by the method for manufacturing a shielded gate power device according to the present invention.
Description of the reference numerals
01. Semiconductor layer
011. Groove
012. Dielectric layer
013. Shielding gate layer
02. Gate dielectric layer
03. Isolation dielectric layer
04. Grid conductive layer
05. Interlayer dielectric layer
051. Contact hole
06. Source electrode
1. Semiconductor layer
11. Groove
12. Dielectric layer
13. Shielding gate layer
14. Dielectric material layer
15. Layer of shielding grid material
2. Gate dielectric layer
3. Grid conductive layer
31. Layer of gate conductive material
4. Interlayer dielectric layer
41. First through hole
42. Second through hole
5. Plugging layer
51. Contact hole
6. Source electrode
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 3 to 14. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
The embodiment provides a method for manufacturing a shielded gate power device, as shown in fig. 3, which is a process flow diagram of the method for manufacturing the shielded gate power device, and includes the following steps:
s1: providing a semiconductor layer, wherein the upper surface layer of the semiconductor layer is provided with a plurality of grooves with upward openings and arranged at intervals along the X direction;
s2: sequentially forming a dielectric layer positioned on the inner wall and the bottom surface of the groove and the shielding gate layer positioned in the groove, wherein the dielectric layer wraps the side wall and the bottom surface of the shielding gate layer, and the upper surface of the dielectric layer is lower than the upper surface of the shielding gate layer;
s3: forming a gate dielectric layer covering the inner wall of the groove, the upper surface of the dielectric layer and the exposed surface of the shielding gate layer, and forming a gate conducting layer filling the groove, wherein the gate dielectric layer wraps the side wall and the bottom surface of the gate conducting layer;
s4: forming an interlayer dielectric layer covering the gate dielectric layer and the upper surface of the gate conducting layer, and forming a plurality of first through holes and a plurality of second through holes penetrating through the interlayer dielectric layer, wherein the bottom surfaces of the first through holes expose the upper surface of the gate conducting layer, and the bottom surfaces of the second through holes expose the upper surface of the semiconductor layer between two adjacent grooves;
s5: forming a blocking layer on the exposed surface of the interlayer dielectric layer to obtain a cavity structure consisting of the blocking layer, the first through hole and the grid conducting layer, extending the bottom surface of the blocking layer in the first through hole to a position away from the upper surface of the interlayer dielectric layer by a preset distance, and thinning the blocking layer;
s6: forming a contact hole based on the second through hole, and forming a source electrode filling the contact hole.
Referring to fig. 4 to 7, the step S1 and the step S2 are executed: providing a semiconductor layer 1, wherein the upper surface layer of the semiconductor layer 1 is provided with a plurality of grooves 11 with upward openings and arranged at intervals along the X direction; form in proper order and be located the dielectric layer 12 of the inner wall and the bottom surface of slot 11 and be located in the slot 11 shielding grid layer 13, dielectric layer 12 parcel shielding grid layer 13's lateral wall and bottom surface, the upper surface of dielectric layer 12 is less than shielding grid layer 13's upper surface.
Specifically, as shown in fig. 4, a schematic cross-sectional structure of the semiconductor layer 1 is shown, and the semiconductor layer 1 includes a first conductive type substrate (not shown) and a first conductive type drift region (not shown).
Specifically, the first conductive type includes one of an N type or a P type, the second conductive type includes one of an N type or a P type, and the first conductive type is opposite to the second conductive type. In this embodiment, the first conductive type is an N-type, and the second conductive type is a P-type.
Specifically, the doping concentration of the substrate is greater than that of the drift region, and under the condition that the device performance is ensured and the doping concentration of the substrate is greater than that of the drift region, the doping concentration of the substrate can be selected according to actual conditions, and is not limited herein; the doping concentration of the drift region can be selected according to practical conditions and is not limited here.
Specifically, the material of the substrate includes silicon, silicon germanium, silicon carbide or other suitable semiconductor materials.
Specifically, the thickness of the substrate may be selected according to actual conditions without limitation, and the thickness of the drift region may be selected according to actual conditions without limitation.
Specifically, the trench 11 is located in the drift region, and under the condition of ensuring the device performance, the depth and the opening size of the trench 11 may be selected according to practical situations, which are not limited herein. The depth here refers to a distance from the bottom surface of the trench 11 to the opening of the trench 11 (i.e., the upper surface of the semiconductor layer 1).
Specifically, in the case of ensuring the device performance, the distance between two adjacent grooves 11 in the X direction may be selected according to practical situations, and is not limited here.
Specifically, the method further includes a step of forming a dielectric material layer 14 covering the upper surface of the semiconductor layer 1 and the inner wall and the bottom surface of the trench 11 before forming the dielectric layer 12.
Specifically, as shown in fig. 5, in order to schematically illustrate the cross-sectional structure after the dielectric material layer 14 is formed, the method for forming the dielectric material layer 14 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
Specifically, the material of the dielectric material layer 14 includes silicon oxide, silicon nitride, or other suitable dielectric materials.
Specifically, the thickness of the dielectric material layer 14 covering the inner wall of the trench 11 may be selected according to practical situations without limitation, while ensuring device performance.
Specifically, as shown in fig. 6, for a schematic cross-sectional structure diagram after the formation of the shielding gate material layer 15, after the formation of the dielectric material layer 14 and before the formation of the dielectric layer 12, the method further includes a step of forming the shielding gate material layer 15 covering the upper surface of the dielectric material layer 14 and filling the trench 11.
Specifically, the method for forming the shielding gate material layer 15 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
Specifically, the material of the shielding gate material layer 15 includes polysilicon or other suitable conductive material.
Specifically, the forming of the dielectric layer 12 and the shielding gate layer 13 includes the following steps: removing the shielding gate material layer 15 covering the upper surface of the dielectric material layer 14 and the top of the trench 11 to obtain the shielding gate layer 13 with a preset height; and removing the dielectric material layer 14 covering the upper surface of the semiconductor layer 1 and the inner wall of the top of the trench 11 to obtain the dielectric layer 12 with the upper surface lower than that of the shielding gate layer 13.
Specifically, the method for removing the shielding gate material layer 15 covering the upper surface of the dielectric material layer 14 includes chemical mechanical polishing, dry etching, wet etching or other suitable methods; the method for removing the shielding gate material layer 15 on the top of the trench 11 includes dry etching, wet etching or other suitable methods.
Specifically, in the case of ensuring the device performance, the height of the shielding gate layer 13 may be selected according to practical situations, and is not limited here. The height herein refers to a distance between a bottom surface of the shield gate layer 13 and an upper surface of the shield gate layer 13.
Specifically, the method for removing the dielectric material layer 14 covering the upper surface of the semiconductor layer 1 includes chemical mechanical polishing, dry etching, wet etching or other suitable methods; the method for removing the dielectric material layer 14 on the top inner wall of the trench 11 includes dry etching, wet etching or other suitable methods
Specifically, as shown in fig. 7, for the schematic cross-sectional structure after the dielectric layer 12 is formed, under the condition that the device performance is ensured, the distance between the upper surface of the dielectric layer 12 and the upper surface of the shielding gate layer 13 may be selected according to actual situations, and is not limited here.
Referring to fig. 8 to 12 again, the step S3 and the step S4 are executed: forming a gate dielectric layer 2 covering the inner wall of the trench 11, the upper surface of the dielectric layer 12 and the exposed surface of the shielding gate layer 13, forming a gate conductive layer 3 filling the trench 11, wherein the gate dielectric layer 2 wraps the side wall and the bottom surface of the gate conductive layer 3; forming an interlayer dielectric layer 4 covering the gate dielectric layer 2 and the upper surface 3 of the gate conductive layer, and forming a plurality of first through holes 41 and a plurality of second through holes 42 penetrating through the interlayer dielectric layer 4, wherein the bottom surfaces of the first through holes 41 are exposed out of the upper surface of the gate conductive layer 3.
Specifically, as shown in fig. 8, for a schematic cross-sectional structure diagram after the gate dielectric layer 2 is formed, a method for forming the gate dielectric layer 2 includes a thermal oxidation method, a chemical vapor deposition method, a physical vapor deposition method, or another suitable method.
Specifically, the thickness of the gate dielectric layer 2 may be selected according to actual conditions, and is not limited herein, while ensuring device performance.
Specifically, the material of the gate dielectric layer 2 includes silicon oxide, silicon nitride, or other suitable dielectric materials.
Specifically, the forming of the gate conductive layer 3 includes the following steps: forming a gate conductive material layer 31 covering the upper surface of the gate dielectric layer 2 and filling the trench 11; and removing the gate conductive material layer 31 covering the upper surface of the gate dielectric layer 2 to obtain the gate conductive layer 3 located in the trench 11.
Specifically, as shown in fig. 9, in order to form a schematic cross-sectional structure of the gate conductive material layer 31, a method for forming the gate conductive material layer 31 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
Specifically, the method for removing the gate conductive material layer 31 covering the upper surface of the gate dielectric layer 2 includes chemical mechanical polishing, dry etching, wet etching or other suitable methods.
As an example, after the gate conductive layer 3 is formed and before the interlayer dielectric layer 4 is formed, a step of forming a first conductive type source region (not shown) and a second conductive type base region (not shown) on the upper surface of the semiconductor layer 1 between two adjacent trenches 11 is further included, where the source region is located on the upper surface of the base region.
Specifically, the method for forming the base region includes ion implantation or other suitable methods.
Specifically, under the condition of ensuring the device performance, the doping concentration and the thickness of the base region can be selected according to practical situations, and are not limited here. The thickness here refers to the distance between the lower surface of the base region and the upper surface of the base region.
Specifically, the method for forming the source region includes ion implantation or other suitable methods.
Specifically, the doping concentration of the source region is greater than that of the drift region, and the doping concentration, size, thickness and shape of the source region can be selected according to actual conditions under the condition that the device performance is ensured, which is not limited herein. The thickness here refers to the distance between the lower surface of the source region and the upper surface of the source region.
As an example, the lower surface of the gate conductive layer 3 is lower than the lower surface of the base region, that is, the lower surface of the gate conductive layer 3 has a position height smaller than the position height of the lower surface of the base region, where the position height of the lower surface of the gate conductive layer 3 refers to a distance between the gate conductive layer 3 and the bottom surface of the semiconductor layer 1, and the position height of the lower surface of the base region refers to a distance between the lower surface of the base region and the bottom surface of the semiconductor layer 1.
Specifically, the lower surface of the gate conductive layer 3 is lower than the lower surface of the base region, so that the gate conductive layer 3 controls the opening and closing of the conductive channel in the base region.
Specifically, the method for forming the interlayer dielectric layer 4 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
For example, as shown in fig. 11 and 12, a schematic cross-sectional structure after forming the first via 41 and a schematic top surface structure of the interlayer dielectric layer 4 located above the gate conductive layer 3 after forming the first via 41 are respectively shown, and a method for forming the first via 41 includes dry etching or other suitable methods. In this embodiment, since the dry etching has good anisotropy, the first through hole 41 is formed by the dry etching.
Specifically, the method for forming the second through hole 42 includes dry etching, wet etching, or other suitable methods. In this embodiment, in order to save cost, the first through hole 41 and the second through hole 42 are formed simultaneously by dry etching.
Specifically, the first through hole 41 has a high aspect ratio, so that the blocking layer is difficult to fill into the bottom of the first through hole 41 during the formation of the blocking layer (see the following fig. 12), and only the top of the first through hole 41 can be filled to block the opening of the first through hole 41. The aspect ratio herein refers to a ratio of the depth of the first through hole 41 to the opening size of the first through hole 41.
Referring to fig. 13 to 14, the steps S5 and S6 are executed: forming a blocking layer 5 on the exposed surface of the interlayer dielectric layer 4 to obtain a cavity structure consisting of the blocking layer 5, the first through hole 41 and the gate conductive layer 3, wherein the bottom surface of the blocking layer 5 in the first through hole 41 extends to a position away from the upper surface of the interlayer dielectric layer 4 by a preset distance, and thinning and covering the blocking layer 5; a contact hole 51 is formed based on the second via hole 42, and a source electrode 6 filling the contact hole 51 is formed.
As an example, the method of forming the blocking layer 5 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
Specifically, the material of the blocking layer 5 includes silicon oxide, silicon nitride, or other suitable dielectric materials.
Specifically, since the first through hole 41 has a high aspect ratio, in the process of forming the blocking layer 5, the blocking layer 5 is difficult to fill into the first through hole 41, and only the top of the first through hole 41 is filled, and then the upper surface layer of the first through hole 41 is blocked, so that the blocking layer 5, the first through hole 41 and the gate conductive layer 3 surround a plurality of cavity structures.
Specifically, since the cavity portion in the cavity structure is a vacuum cavity or an air cavity filled with air, and the dielectric constant values of vacuum and air are smaller than the dielectric constant values of the interlayer dielectric layer 4 and the blocking layer 5, the formation of the cavity structure in the interlayer dielectric layer 4 above the gate conductive layer 3 causes the dielectric performance of the region of the interlayer dielectric layer 4 above the gate conductive layer 3 to be lowered.
Specifically, the method for thinning the blocking layer 5 includes chemical mechanical polishing, dry etching, wet etching, or other suitable methods.
Specifically, the thickness of the thinned plugging layer 5 can be selected according to actual conditions under the condition of ensuring the performance of the device, and is not limited herein.
Specifically, the device performance is guaranteed, the blocking layer 5 can block the opening of the first through hole 41, the blocking layer 5 can be thinned, and meanwhile the upper surface layer of the interlayer dielectric layer 4 can be thinned.
Specifically, when thinning the plugging layer 5, the plugging layer 5 covering the bottom surface of the second through hole 42 (i.e., the exposed upper surface of the semiconductor layer 1) is removed to expose the upper surface of the conductor layer 1, and the opening size of the through hole of the second through hole 42 is adjusted by using the plugging layer 5, so that a part of the contact hole 51 located in the interlayer dielectric layer 4 with a suitable size is obtained.
Specifically, the semiconductor layer 1 at the bottom of the second via hole 42 is etched based on the second via hole 42 with the via hole opening size adjusted to form the contact hole 51.
Specifically, the method for etching the semiconductor layer 1 at the bottom of the second through hole 42 includes dry etching, wet etching, or other suitable methods.
Specifically, as shown in fig. 13, for a schematic cross-sectional structure diagram after the contact hole 51 is formed, the contact hole 51 penetrates through the source region, and the base region is exposed at a bottom surface.
Specifically, a second conductive type contact region (not shown) is further formed at the bottom of the contact hole 51, and the doping concentration of the contact region is greater than that of the base region.
Specifically, the method for forming the contact region includes ion implantation or other suitable methods.
Specifically, the method for forming the source electrode 6 includes a sputtering method, a physical vapor deposition method, a chemical vapor deposition method, a metal compound vapor deposition method, a molecular beam epitaxy method, an atomic vapor deposition method, an atomic layer deposition method, or another suitable method.
Specifically, as shown in fig. 14, in order to form the cross-sectional structure of the source electrode 6, the material of the source electrode 6 includes titanium, titanium nitride, silver, gold, copper, aluminum, tungsten, or other suitable conductive materials.
Specifically, the source electrode 6 also covers the upper surface of the interlayer dielectric layer 4 above the gate conductive layer 3.
Specifically, the method further includes a step (not shown) of forming a gate electrode (not shown) and a drain electrode after forming the source electrode 6.
Specifically, the gate electrode is electrically connected to the gate conductive layer 3, and the drain electrode is electrically connected to the lower surface of the semiconductor layer 1.
Specifically, the method for forming the gate electrode includes a sputtering method, a physical vapor deposition method, a chemical vapor deposition method, a metal compound vapor deposition method, a molecular beam epitaxy method, an atomic vapor deposition method, an atomic layer deposition method, or other suitable methods; the method for forming the drain electrode includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.
Specifically, the gate electrode is made of titanium, titanium nitride, silver, gold, copper, aluminum, tungsten or other suitable conductive materials; the drain electrode is made of titanium, titanium nitride, silver, gold, copper, aluminum, tungsten or other suitable conductive materials.
Specifically, the source electrode 6 covers the upper surface of the interlayer dielectric layer 4 above the gate conductive layer 3, and the blocking layer 5, the first through hole 41 and the interlayer dielectric layer 4 surround to form the cavity structure, so that the dielectric property of the interlayer dielectric layer 4 above the gate conductive layer 3 is reduced.
Specifically, since the gate conductive layer 3 is electrically connected to the gate electrode, the gate-source parasitic capacitance of the device
Wherein S is the effective area of the source electrode 6 opposite to the grid electrode, k is the constant of vacuum electrostatic force, d is the distance between the source electrode 6 and the grid electrode of the device, and the effective dielectric constant epsilon of the dielectric medium between the source electrode 6 and the grid electrode is caused by the reduction of the dielectric property of the interlayer dielectric layer 4 r The gate-source parasitic capacitance C between the source electrode 6 and the gate electrode is reduced, in turn gs . The effective permittivity of the dielectric herein refers to an equivalent permittivity of the interlayer dielectric layer 4 and the cavity structure region between the gate conductive layer 3 and the source electrode 6.
Specifically, due to the formation of the cavity structure in the interlayer dielectric layer 4 above the gate conductive layer 3, the effective dielectric constant of the dielectric between the gate and the source 6 is reduced, the dielectric performance of the dielectric between the gate and the source 6 is reduced without increasing the thickness of the interlayer dielectric layer 4 (i.e., increasing the distance between the source 6 and the gate), and under the condition that the opening size of the contact hole 51 is fixed, the aspect ratio of the contact hole 51 is not required to be increased, so that the process difficulty in forming the source 6 for filling the contact hole 51 is reduced, the quality of the source 6 for filling the contact hole 51 is ensured, and the reliability of the source 6 is improved.
In the preparation method of the shielded gate power device of the embodiment, after the interlayer dielectric layer 4 is formed and before the contact hole 51 is formed, a plurality of first through holes 41 penetrating through the interlayer dielectric layer 4 are formed in the interlayer dielectric layer 4 covering the upper part of the gate conductive layer 3, and the first through holes 41 have a high aspect ratio, so as to form the blocking layer 5 for blocking the opening of the first through hole 41, and the blocking layer 5 blocks the opening of the first through hole 41, so that a plurality of cavity structures surrounded by the blocking layer 5, the first through hole 41 and the gate conductive layer 3 are formed in the interlayer dielectric layer, and since the cavity part of the cavity structures is air or vacuum, the dielectric property of the interlayer dielectric layer 4 is reduced, the dielectric constant of a dielectric medium between the gate and the source 6 is reduced, and the gate-source parasitic capacitance of the device is reduced; due to the formation of the cavity structure, the reduction of the gate-source parasitic capacitance of the device by increasing the thickness of the interlayer dielectric layer 4 is avoided, under the condition that the opening size of the contact hole 51 is fixed, the increase of the depth-to-width ratio of the contact hole 51 cannot be caused, the process difficulty of forming the source electrode 6 for filling the contact hole 51 is reduced, the quality of the source electrode 6 for filling the contact hole 51 is ensured, and the reliability of the source electrode 6 is improved.
Example two
The embodiment provides a shielded gate power device, as shown in fig. 14, which is a schematic cross-sectional structure diagram of the shielded gate power device, and includes a semiconductor layer 1, a dielectric layer 12, a shielded gate layer 13, a gate dielectric layer 2, a gate conductive layer 3, an interlayer dielectric layer 4, a blocking layer 5, a contact hole 51, and a source electrode 6, wherein the upper surface of the semiconductor layer 1 is provided with a plurality of trenches 11 with upward openings and arranged at intervals along an X direction; the dielectric layer 12 is located on the inner wall and the bottom surface of the trench 11; the shielding gate layer 13 is located in the trench 11, the dielectric layer 12 wraps the side wall and the bottom surface of the shielding gate layer 13, and the upper surface of the dielectric layer 12 is lower than the upper surface of the shielding gate layer 13; the gate dielectric layer 2 covers the inner wall of the trench 11, the upper surface of the dielectric layer 12 and the exposed surface of the shielding gate layer 13; the groove 11 is filled with the gate conducting layer 3, and the side wall and the bottom surface of the gate conducting layer 3 are wrapped by the gate dielectric layer 2; the interlayer dielectric layer 4 covers the upper surfaces of the gate dielectric layer 2 and the gate conducting layer 3, and a plurality of first through holes 41 which penetrate through the interlayer dielectric layer 4 and expose the upper surface of the gate conducting layer 3 are arranged in the interlayer dielectric layer 4; the blocking layer 5 blocks the opening of the first through hole 41, the bottom surface of the blocking layer 5 is away from the upper surface of the interlayer dielectric layer 4 by a preset distance, and the blocking layer 5, the first through hole 51 and the gate conductive layer 3 form a cavity structure; the contact hole 51 penetrates through the interlayer dielectric layer 4 above the semiconductor layer 1 between two adjacent trenches 11; the source electrode 6 fills the contact hole 51.
Specifically, the semiconductor layer 1 includes a first conductive type substrate and a first conductive type drift region stacked in sequence, and the doping concentration of the drift region is less than that of the substrate.
As an example, a first conductive type source region and a second conductive type base region are further disposed on the upper surface of the semiconductor layer 1 between two adjacent trenches 11, and the source region is located on the upper surface of the base region.
Specifically, the doping concentration of the source region is greater than the doping concentration of the drift region.
Specifically, the height of the bottom surface of the base region is greater than that of the bottom surface of the gate conductive layer 3, so that a conductive channel is formed in the base region.
As an example, the aspect ratio of the first via hole 41 is greater than the aspect ratio of the trench 11, and the aspect ratio of the first via hole 41 is greater than the aspect ratio of the contact hole 51.
Specifically, the first through hole 41, the blocking layer 5 and the gate conductive layer 3 are sealed by the blocking layer 5 to form a cavity structure, and the cavity of the cavity structure is a vacuum cavity or an air cavity.
Specifically, since the dielectric constant value of the cavity portion (i.e., the vacuum cavity and the air cavity) in the interlayer dielectric layer 4 is smaller than the dielectric constant value of the material of the interlayer dielectric layer 4, the dielectric property of the interlayer dielectric layer 4 between the gate conductive layer 3 and the source electrode 6 is reduced.
As an example, the opening shape of the first through hole 41 includes a circle, a quadrangle, or other suitable shape.
Specifically, the arrangement of the first through holes 41 may be irregular under the condition of ensuring the performance of the device.
As an example, the first through holes 41 are arranged in an array so as to make the dielectric properties of the interlayer dielectric layer 4 above the gate conductive layer 3 uniform.
Specifically, a gate and a drain are further arranged in the shielded gate power device, the gate is electrically connected with the gate conductive layer 3, and the drain is electrically connected with the bottom surface of the semiconductor layer 1.
Specifically, the source electrode covers the upper surface of the interlayer dielectric layer 4 above the gate conductive layer 3.
Specifically, the base region is exposed from the bottom surface of the contact hole 51, a second conductive type contact region is further arranged in the base region on the bottom surface of the contact hole 51, and the doping concentration of the contact region is greater than that of the base region.
Specifically, the source electrode 6 filling the contact hole 51 forms an ohmic contact with the source region.
Specifically, due to the arrangement of the cavity structure in the interlayer dielectric layer 4 above the gate conductive layer 3, the effective dielectric constant value of the interlayer dielectric layer 4 between the gate conductive layer 3 and the source electrode 6 is reduced, the gate conductive layer 3 is electrically connected with the gate electrode, and thus the gate electrode and the source electrode are reducedParasitic capacitance C of gate and source between poles gs 。
Specifically, due to the reduction of the gate-source parasitic capacitance, the input capacitance of the device is reduced, so that the switching speed of the device is increased, and the switching loss of the device is reduced.
In the shielding gate power device of this embodiment, the cavity structure surrounded by the first through hole 41, the blocking layer 5, and the gate conductive layer 3 is disposed in the interlayer dielectric layer 4 above the gate conductive layer 3, so that the dielectric property of the interlayer dielectric layer 4 between the gate conductive layer 3 and the source electrode 6 is reduced, the gate-source parasitic capacitance of the device is reduced, the switching speed of the device is increased, and the switching loss of the device is reduced.
In summary, in the shielded gate power device and the manufacturing method thereof of the invention, the plurality of first through holes penetrating through the interlayer dielectric layer are arranged in the interlayer dielectric layer above the gate conductive layer, and the blocking layer for blocking the openings of the first through holes is formed at the top of the first through holes, so that the first through holes, the blocking layer and the gate conductive layer surround to form the cavity structure, and through the arrangement of the cavity structure, the gate-source parasitic capacitance between the gate and the source is reduced, the switching speed of the device is increased, and the switching loss of the device is reduced. In addition, due to the arrangement of the cavity structure in the interlayer dielectric layer, the gate-source parasitic capacitance of the device is not required to be reduced by increasing the thickness of the interlayer dielectric layer, the depth-width ratio of the formed contact hole is ensured, the process difficulty of filling the contact hole is reduced, the quality of the source electrode of the contact hole is ensured, and the reliability of the source electrode is improved. Therefore, the present invention effectively overcomes various disadvantages of the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A preparation method of a shielded gate power device is characterized by comprising the following steps:
providing a semiconductor layer, wherein the upper surface layer of the semiconductor layer is provided with a plurality of grooves with upward openings and arranged at intervals along the X direction;
sequentially forming a dielectric layer positioned on the inner wall and the bottom surface of the groove and the shielding gate layer positioned in the groove, wherein the dielectric layer wraps the side wall and the bottom surface of the shielding gate layer, and the upper surface of the dielectric layer is lower than the upper surface of the shielding gate layer;
forming a gate dielectric layer covering the inner wall of the groove, the upper surface of the dielectric layer and the exposed surface of the shielding gate layer, and forming a gate conductive layer filling the groove, wherein the gate dielectric layer wraps the side wall and the bottom surface of the gate conductive layer;
forming an interlayer dielectric layer covering the gate dielectric layer and the upper surface of the gate conducting layer, and forming a plurality of first through holes and a plurality of second through holes which penetrate through the interlayer dielectric layer, wherein the bottom surfaces of the first through holes expose the upper surface of the gate conducting layer;
forming a blocking layer on the exposed surface of the interlayer dielectric layer to obtain a cavity structure consisting of the blocking layer, the first through hole and the gate conductive layer, extending the bottom surface of the blocking layer in the first through hole to a position away from the upper surface of the interlayer dielectric layer by a preset distance, and thinning the blocking layer;
forming a contact hole based on the second through hole, and forming a source electrode filling the contact hole.
2. The method of manufacturing a shielded gate power device according to claim 1, wherein: after the gate conductive layer is formed and before the interlayer dielectric layer is formed, a step of forming a first conductive type source region and a second conductive type base region on the upper surface of the semiconductor layer between two adjacent trenches is further included, and the source region is located on the upper surface of the base region.
3. The method for manufacturing a shielded gate power device according to claim 2, wherein: the lower surface of the gate conductive layer is lower than the lower surface of the base region.
4. The method of manufacturing a shielded gate power device according to claim 1, wherein: the method for forming the first through hole comprises dry etching.
5. The method for manufacturing a shielded gate power device according to claim 1, wherein: the method for forming the blocking layer comprises chemical vapor deposition and physical vapor deposition.
6. A shielded gate power device, comprising:
the upper surface of the semiconductor layer is provided with a plurality of grooves with upward openings and arranged at intervals along the X direction;
the dielectric layer is positioned on the inner wall and the bottom surface of the groove;
the shielding grid layer is positioned in the groove, the dielectric layer wraps the side wall and the bottom surface of the shielding grid layer, and the upper surface of the dielectric layer is lower than the upper surface of the shielding grid layer;
the gate dielectric layer covers the inner wall of the groove, the upper surface of the dielectric layer and the exposed surface of the shielding gate layer;
the grid conducting layer is filled in the groove, and the side wall and the bottom surface of the grid conducting layer are wrapped by the grid dielectric layer;
the interlayer dielectric layer covers the upper surfaces of the gate dielectric layer and the gate conducting layer, and a plurality of first through holes which penetrate through the interlayer dielectric layer and expose the upper surface of the gate conducting layer are formed in the interlayer dielectric layer;
the blocking layer blocks the opening of the first through hole, the bottom surface of the blocking layer is away from the upper surface of the interlayer dielectric layer by a preset distance, and the blocking layer, the first through hole and the grid conducting layer form a cavity structure;
the contact hole penetrates through the interlayer dielectric layer positioned above the semiconductor layer between every two adjacent grooves;
and the source electrode fills the contact hole.
7. The shielded gate power device of claim 6, wherein: the depth-to-width ratio of the first through hole is larger than that of the groove, and the depth-to-width ratio of the first through hole is larger than that of the contact hole.
8. The shielded gate power device of claim 6, wherein: the opening shape of the first through hole comprises a circle and a quadrangle.
9. The shielded gate power device of claim 6, wherein: the first through holes are arranged in an array.
10. The shielded gate power device of claim 6, wherein: the upper surface layer of the semiconductor layer between every two adjacent grooves is further provided with a first conduction type source region and a second conduction type base region, and the source region is located on the upper surface layer of the base region.
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