CN115910768A - Etching method of semiconductor structure - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 111
- 238000005530 etching Methods 0.000 title claims abstract description 107
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000010410 layer Substances 0.000 claims abstract description 163
- 239000012792 core layer Substances 0.000 claims abstract description 124
- 239000000463 material Substances 0.000 claims abstract description 78
- 239000011241 protective layer Substances 0.000 claims abstract description 43
- 230000008569 process Effects 0.000 claims description 70
- 238000000151 deposition Methods 0.000 claims description 7
- 229920000642 polymer Polymers 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910003902 SiCl 4 Inorganic materials 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000000059 patterning Methods 0.000 description 20
- 239000000758 substrate Substances 0.000 description 8
- 239000011162 core material Substances 0.000 description 6
- 230000002829 reductive effect Effects 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 5
- 230000009471 action Effects 0.000 description 4
- 229910003481 amorphous carbon Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910003910 SiCl4 Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000013077 target material Substances 0.000 description 2
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
The invention discloses an etching method of a semiconductor structure, which comprises the following steps: providing a material layer to be etched, wherein a plurality of discrete core layers are formed on the material layer to be etched; forming a mask layer on the material layer to be etched exposed among the core layers and on the top and the side wall of the core layers; forming a protective layer on the mask layer; carrying out anisotropic etching on the protective layer and part of the mask layer until the protective layer is completely removed and the top of the core layer and part of the material layer to be etched between the adjacent core layer spacing regions are exposed; removing the core layer; and etching the material layer to be etched by taking the residual mask layer as a mask, and forming a target pattern in the material layer to be etched. The invention can improve the CD odd-even loading problem and depth loading problem of the target graph.
Description
Technical Field
The invention belongs to the field of semiconductor device manufacturing, and particularly relates to an etching method of a semiconductor structure.
Background
With the continuous development of very large integrated circuits, the Critical Dimension (CD) of a semiconductor device is continuously decreasing, and the manufacturing process thereof also faces many limitations and challenges, and under the condition that the critical dimension is smaller, how to improve the accuracy and stability of small-sized patterns becomes a research hotspot in the industry.
A self-aligned double patterning (SADP) method and a self-aligned quadruple patterning (SAQP) method are popular patterning methods in recent years. The density of the pattern formed on the substrate by the self-aligned double patterning method is twice of the density of the pattern formed on the substrate by the photoetching process, namely 1/2 minimum pitch (1/2 pitch) can be obtained, and the density of the pattern formed on the substrate by the self-aligned quadruple patterning method is four times of the density of the pattern formed on the substrate by the photoetching process on the premise of not changing the current photoetching technology (namely the size of a photoetching window is not changed), namely 1/4 minimum pitch (1/4 pitch) can be obtained, so that the density of a semiconductor integrated circuit can be greatly improved, the characteristic size of the pattern is reduced, and the improvement of the performance of a device is facilitated.
However, the introduction of the self-aligned dual and quadruple patterning processes leads to different etching rates and micro-loading effect (also called depth loading) due to different etching gas collection angles in the mask manufacturing process, so that the etched substrate surface has a height difference (pitch walking) problem, or the difference between CDs of adjacent openings of the mask pattern causes CD parity loading, resulting in still poor quality of the target pattern formed after etching.
Disclosure of Invention
The invention aims to provide an etching method of a semiconductor structure, which can be used for improving the CD odd-even loading problem and depth loading problem of a target pattern.
In order to achieve the above object, the present invention provides an etching method for a semiconductor structure, including:
providing a material layer to be etched, wherein a plurality of discrete core layers are formed on the material layer to be etched;
forming a mask layer on the material layer to be etched exposed among the core layers and on the top and the side wall of the core layers;
forming a protective layer on the mask layer;
anisotropic etching is carried out on the protective layer and part of the mask layer until the protective layer is completely removed and the top of the core layer and part of the material layer to be etched between the adjacent core layers are exposed;
removing the core layer;
and etching the material layer to be etched by taking the residual mask layer as a mask, and forming a target pattern in the material layer to be etched.
Optionally, the mask layer on the side wall of the core layer and the protective layer form a side wall, and a transverse distance between outer walls of adjacent side walls is smaller than a width of the core layer.
Optionally, the forming a protection layer on the mask layer includes:
depositing a protective layer with a set thickness on the mask layer through first process gas, wherein the first process gas is one or more of CH3F, CH2F2, HBr, CH4 and SiCl4 and O2;
the protective layer is silicon oxide, CF polymers or Si-O-Br polymers.
Optionally, the set thickness is
Optionally, the first process gas comprises SiCl4 and O2;
the process parameters adopted for depositing the protective layer with the set thickness on the mask layer through the first process gas comprise:
the upper radio frequency power range is 100W-2000W;
the lower radio frequency power range is 10W-1500W;
the pressure range of the process chamber is 3 mT-100 mT;
the temperature range of the process chamber is 10-90 ℃;
the flow range of SiCl4 is: 1 sccm-100 sccm;
the flow range of O2 is: 1sccm to 100sccm.
Optionally, the performing anisotropic etching on the protection layer and part of the mask layer includes:
starting upper radio frequency power and lower radio frequency power, and removing the protective layer and part of the mask layer above the part of the material layer to be etched, which is positioned above the top of the core layer and between the adjacent core layers, by using first etching gas;
wherein, the upper radio frequency power range is: 100W-3000W; the lower rf power range is: 50W to 1000W.
Optionally, the first etching gas comprises CF4 and CHF3.
Optionally, the process parameters for performing the anisotropic etching on the protection layer and the mask layer further include:
the process chamber pressure ranges are: 3 mT-100 mT;
the process chamber temperature range is: 10-90 ℃;
the flow range of the CF4 is as follows: 10sccm to 200sccm;
the flow range of CHF3 is: 10sccm to 200sccm.
Optionally, in the step of removing the core layer, only upper rf power is turned on;
wherein, the upper radio frequency power range is: 100W to 6000W.
Optionally, the etching the material layer to be etched by using the remaining mask layer as a mask includes:
starting upper radio frequency power and lower radio frequency power, taking the residual mask layer as a mask, and etching the material layer to be etched by using second etching gas;
wherein, the upper radio frequency power range is: 100W-6000W; the lower rf power range is: 10W to 2000W.
The invention has the beneficial effects that:
the invention firstly forms a mask layer covering a core layer, then forms a protective layer on the mask layer, adjusts the CD between the side walls through the protective layer, can avoid the transverse etching of the outer wall of the mask layer through the action of the protective layer when the top of the core layer is opened by etching, reduces the CD loss between the side walls, ensures that the CD between the side walls is smaller than the CD of the core layer after the top of the core layer is opened by etching, when the target pattern etching is carried out after the core layer is removed, the region with small CD between the side walls can not be drawn away in time because of the product of plasma etching, the method has the advantages that the etching rate is lower than that of the region with the large CD of the prokaryotic core layer, so that the loss of materials to be etched between the two side walls caused in the step of opening the side wall can be compensated, the depth loading problem is effectively solved, and further the pitch walking problem is improved.
The system of the present invention has other features and advantages which will be apparent from or are set forth in detail in the accompanying drawings and the following detailed description, which are incorporated herein, and which together serve to explain certain principles of the invention.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail exemplary embodiments thereof with reference to the attached drawings, in which like reference numerals generally represent like parts.
Fig. 1 is a schematic diagram illustrating a structure corresponding to each step in a semiconductor structure forming method according to a related art.
Fig. 2 is a schematic structural diagram illustrating steps in a method for forming a self-aligned double patterning structure according to a second related art.
Fig. 3-7 are schematic structural diagrams illustrating steps in a method for forming a semiconductor structure according to an embodiment of the present invention.
FIG. 8a shows an etch profile obtained using a conventional self-aligned double patterning method.
FIG. 8b shows an etching profile obtained by a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As shown in fig. 1, a related art method for forming a semiconductor structure includes: forming a patterned core layer 200 on the material layer 100 to be etched; forming a sidewall film 300 on the top and sidewall surfaces of the core layer 200 and the material layer 100 to be etched; performing at least one top treatment on the side wall film 300, removing the side wall film 300 higher than the top of the core layer 200, keeping the side wall film 300 on the side wall of the core layer 200 as a first part mask layer 320, and keeping the side wall film 300 on the material layer 100 to be etched as a second part mask layer 330; wherein the top treatment step comprises: forming a sacrificial layer 400 on the sidewall film 300, the sacrificial layer 400 covering the surface of the sidewall film 300 on the sidewall and top of the core layer 200; etching to remove the sacrificial layer 400 higher than the top of the core layer 200 and the side wall film 300 with partial thickness or full thickness; removing the remaining sacrificial layer 400; after the first part of the masking layer 320 and the second part of the masking layer 330 are formed, the core layer 200 is removed; removing the second mask layer 330 after removing the core layer 200; after the second mask layer 330 is removed, the material layer to be etched 100 is etched by using the first mask layer 320 as a mask.
Compared with the scheme that a sacrificial layer is not formed and a maskless etching process is adopted to etch the side wall film, the problem that the top surface of the formed first part of the mask layer is an inclined surface can be avoided, namely the top surface of the formed first part of the mask layer is a flat surface; after the core layer is removed, removing the second part of the mask layer, wherein correspondingly, the etching environments at the two top corners of the first part of the mask layer are the same when the second part of the mask layer is removed, so that the appearance of the first part of the mask layer is symmetrical after the second part of the mask layer is removed; therefore, when the first part of the mask layer is used as a mask to etch a material layer to be etched, the problem of different etching gas collection angles (etch species collection angle) can be avoided, the problem of pitch walking of the formed target pattern is correspondingly improved or eliminated, the target pattern with better appearance is obtained, and the performance and the yield of a semiconductor device are improved.
However, the first related art has the following disadvantages:
1. the process is complex, multiple sacrificial layer forming and side wall etching processes are needed, WPH (wafers per hour) is low, and cost is increased.
2. And etching the top side sacrificial layer and part of the side wall and simultaneously etching the bottom of the side wall film and the sacrificial layer, so that part of the material to be etched is etched before the core layer is removed. Finally, the etching depth of the material to be etched between the mask layers is larger than that of the material to be etched of the core layer, namely depth loading; this solution only improves the depth-loading problem (also referred to as micro-loading) of the material to be etched during the etching process to a limited extent. There is no effect on the CD parity loading formed in the process.
3. The related art can only be used for the process after the mask of the core layer is removed, and is not suitable for the core layer mask residue, so that the processing steps are increased, and the cost is increased.
As shown in fig. 2, the second related art provides a method for forming a self-aligned dual patterning structure, which includes: a substrate 100 is provided, a bottom core material layer 103 is formed on the substrate and a discrete first core layer is formed on the bottom core material layer. 102 is a mask residue when the core layer 103 is formed. The side walls 101 are formed on the surface of the core layer 103. After the etching of the side wall 101 is completed, the core layer 103 is removed, and the substrate is patterned by using the side wall head 101 as a mask to form a target pattern.
The second related art has the following disadvantages:
before the core layer 103 is removed, the core layer top needs to be completely exposed, otherwise the core layer cannot be completely removed, and the formation of the target pattern is influenced. Therefore, when the sidewall etching is performed, in order to ensure that the mask residue 102 on the top of the core layer is completely removed, the over-etching amount is increased, which results in the loss of the material 101 to be etched. And due to the action of the plasma transverse etching, the CD loss of one side of the side walls far away from the core layers causes that the CD a between the core layers is smaller than the space CD b1 between the adjacent side walls (note: the CD b between the core layers CD a and the adjacent side walls is equal at the beginning). Similarly, after the core layer is removed, space CD b2 is larger than a1, space CD b3 is larger than a2 after the pattern to be etched is formed, and the difference value between b3 and a2 is the CD parity loading in the self-aligned multi-pattern process (note that the CD parity loading is the difference value between b3 and a 2).
The invention provides an etching method of a semiconductor structure, which is characterized in that a protective layer with a certain thickness is deposited on the surface of a graph before the current graph is etched so as to adjust CD between side walls, thereby improving the odd-even loading and depth loading problems of the CD.
The invention will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
Fig. 3-7 are schematic structural diagrams illustrating steps in a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 1, a material 1 to be etched is provided, and a plurality of discrete core layers 2 are formed on the material layer 1 to be etched;
the material layer 1 to be etched is used for forming a target pattern after a subsequent patterning process. The material layer 1 to be etched may be silicon, silicon dioxide, silicon nitride, photoresist, amorphous carbon, or the like, and in this embodiment, the material layer 1 to be etched is polysilicon.
The core layer 2 provides a process basis for the subsequent formation of an etching mask for patterning the material layer 1 to be etched. The material of the core layer 2 is a material which is easy to remove, and the material of the core layer 2 is different from the material of the material layer 1 to be etched, so that the damage to the material layer 1 to be etched caused by the process for removing the core layer 2 can be reduced. Thus, the material of the core layer 2 may be amorphous carbon, polysilicon, an ODL (organic dielectric layer) material, a BARC (bottom anti-reflection coating) material, a DARC (dielectric anti-reflection coating) material, or a Si-ARC (selective silicon anti-reflection coating) material. In this embodiment, the material of the core layer 2 is amorphous carbon.
Specifically, the step of forming the patterned core layer 2 includes: forming a core material layer on the material layer 1 to be etched; forming a patterned photoresist layer (not shown) on the core material layer; etching the core material layer by using the photoresist layer as a mask, and forming a plurality of discrete core layers 2 by remaining the core material layer; after the core layer 2 is formed, the photoresist layer is removed.
In the embodiment, an etching mask for patterning the material layer 1 to be etched is formed by adopting a self-aligned double patterning process; the CD (width dimension) of the core layer 2 is determined according to the CD required for the subsequent target pattern.
In other embodiments, a self-aligned quadruple patterning process may be further employed to form an etching mask for patterning the material layer 1 to be etched; accordingly, the CD of the core layer is determined according to the CD required by the subsequent etching of the target pattern.
With continued reference to fig. 3, a mask layer 3 is formed on the material layer 2 to be etched exposed between the core layers 2 and on the top and sidewalls of the core layers 2; on top of the core layer 2 in fig. 3 is the residual mask layer 4 when the core layer 2 is formed.
Because the mask layer 3 on the side wall of the core layer 2 needs to be subsequently reserved to be used as an etching mask for patterning the material layer 1 to be etched, the material of the mask layer 3 needs to be different from the material of the core layer 2 and the material layer 1 to be etched, so that the influence of the subsequent process for removing the core layer 2 on the remaining mask layer 3 can be reduced, and the mask layer 3 on the side wall of the core layer 2 can be used as the etching mask for subsequently etching the material layer 1 to be etched.
The mask layer may be made of SiN or SiO 2 In this embodiment, the mask layer is made of SiN.
The process of forming the mask layer 3 may be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In the embodiment, the mask layer 3 is formed by adopting an atomic layer deposition process, so that the step coverage capability of the formed mask layer 3 is better, and the coverage capability of the mask layer 3 on the corner of the material layer 1 to be etched and the core layer 2 is better.
The mask layer 3 on the sidewall of the core layer 2 is used as an etching mask for subsequently etching the material layer 1 to be etched to form a target pattern, so that the thickness of the mask layer 3 on the sidewall of the core layer 2 is determined according to the CD of the target pattern to be formed subsequently.
In addition, after the mask layer 3 is formed in this step, it is preferable that the CD between the vertical mask layers 3 at the sidewalls of the adjacent two core layers 2 may substantially coincide with the CD of the core layer 2, i.e., a = b in fig. 3.
Referring to fig. 4, a protective layer 5 is formed on the mask layer 3;
preferably, the mask layer 3 and the protective layer 5 on the side wall of the core layer 2 form a side wall, and the transverse spacing size between the outer walls of the adjacent side walls is smaller than the width size of the core layer 2;
specifically, before the core layer 2 is removed, the top of the core layer 2 needs to be completely exposed, otherwise, the core layer 2 is not completely removed, which affects the formation of the target pattern. Therefore, when etching is performed to open the top of the core layer 2, in order to ensure that the residual mask 4 on the top of the core layer is completely removed, the over-etching amount is increased, which results in the loss of the material 1 to be etched exposed in the space region between the core layers 2. And the bottom, the side wall and the material to be etched are simultaneously etched while the top of the core layer is opened, so that depth loading and odd-even loading of CD can be caused when the target material etching is carried out after the core layer is subsequently removed.
Therefore, in order to avoid the problems of depth loading and odd-even loading of CD when the core layer is subsequently removed and the target material etching is performed, in this step, a protective layer 104 with a certain thickness is deposited on the mask layer 3, the mask layer 3 and the protective layer 5 on the side wall of the core layer 2 together form a side wall, the mask layer 3 on the side wall of the core layer 3 can be effectively protected from being transversely etched by plasma under the action of the protective layer, and meanwhile, in order to solve the problems of improving the odd-even loading and depth loading of CD, after the protective layer 5 is formed, it is required to ensure that the CD between the side walls of two adjacent core layers 2 is smaller than the CD (width) of the core layer 2, so that the space CD between the two adjacent side walls is reduced (namely, the transverse distance of the spacing region between the two adjacent side walls is changed from b to b1, and b1< a), after the protective layer 104 is deposited, the deposition of the protective layer 5 is completed after the space CD is judged to be smaller than the CD of the core layer 2 through transmission electron microscope detection.
Wherein the thickness of the protective layer 5 is determined by the initial core layer CD and the adjacent layerThe thickness of the side wall can be determined by the CD
This embodiment is preferably based on->
Plasma deposition can be performed at lower temperatures using high upper radio frequency source power (SRF) and low radio frequency source power (BRF). />
The method of forming the protective layer 5 includes:
a protective layer of a set thickness is deposited on the mask layer by a first process gas.
Wherein the first process gas is CH 3 F、CH 2 F 2 、HBr、CH 4 And, siCl 4 And O 2 One or more of (a). The corresponding protective layer 5 may be silicon oxide, a CF-based polymer or a Si-O-Br-based polymer.
In this embodiment, siCl is used as the first process gas 4 And O 2 The protective layer 5 is formed of SiO 2 。
The technological parameters adopted for depositing the protective layer 5 in the step comprise:
the frequency of the upper radio frequency power supply and the lower radio frequency power supply is 13.56MHz;
the upper radio frequency power range is 100W-2000W;
the lower radio frequency power range is 10W-1500W;
the pressure range of the process chamber is 3 mT-100 mT;
the temperature range of the process chamber is 10-90 ℃;
SiCl 4 the flow range of (A) is: 1 sccm-100 sccm;
O 2 the flow range of (A) is: 1sccm to 100sccm.
Referring to fig. 5, anisotropic etching is performed on the protection layer 5 and a part of the mask layer 3 until the protection layer is completely removed and the top of the core layer 2 and a part of the material layer 1 to be etched between adjacent core layers 2 are exposed;
the etching method of the step comprises the following steps:
starting upper radio frequency power and lower radio frequency power, and removing the protective layer 5 and part of the mask layer 3 positioned above the top of the core layer 2 and above part of the material layer to be etched between the adjacent core layers 2 by using first etching gas;
wherein, preferably, the upper radio frequency power range is: 100W-3000W; the lower rf power range is: 50W to 1000W. The first etching gas comprises CF 4 And CHF 3 。
The process parameters for etching the protective layer and the mask layer by using the first etching gas further include:
the process chamber pressure ranges are: 3 mT-100 mT;
the process chamber temperature range is: 10-90 ℃;
CF 4 the flow range of (A) is: 10sccm to 200sccm;
CHF 3 the flow range of (a) is: 10sccm to 200sccm.
The step is to open the top of the core layer 2, usually adopt the CF gas with high etching rate as the main etching gas during etching, and simultaneously adopt the upper radio frequency power and the lower radio frequency power which are higher to improve the etching rate, wherein the upper radio frequency power is used for generating plasma, the lower radio frequency power is used for providing energy and direction for the plasma, the anisotropic etching is enhanced, and the lateral etching to the outer side of the side wall is reduced to ensure that the top of the core layer 2 is completely exposed during etching, and the loss of the outer side wall of the side wall is less.
In the etching process of the step, due to the action of the protective layer 5, the mask layer 3 has no transverse loss basically (the mask layer 3 on the side wall of the core layer 2 is not etched, and the protective layer on the side wall is completely removed), meanwhile, in the etching process, due to the addition of the protective layer 3, the region with smaller CD between the adjacent side walls cannot be drawn out in time due to the product of plasma etching, so that the etching rate of the region with smaller CD between the side walls is lowered, and further, the material layer 1 to be etched in the step is ensured not to be etched to cause loss basically. After the etching in this step is completed, the protective layer 5 is completely removed, only the mask layer 3 remains as a part of the side wall, and the CD between two adjacent side walls is substantially equal to the CD of the core layer, i.e., b = a.
Referring to fig. 6, the core layer is removed;
the method for removing the core layer includes:
removing the core layer with a second process gas comprising O 2 . That is, the core layer 2 is removed by oxidation treatment, and the material layer 1 to be etched at the bottom of the core layer 2 is exposed.
The process parameters for removing the core layer using the second process gas include:
the frequency of the upper radio frequency power supply and the lower radio frequency power supply is 13.56MHz;
the upper rf power range is: 100W-6000W;
the power of the lower radio frequency power supply is 0;
the process chamber pressure ranges are: 5 mT-100 mT;
the process chamber temperature range is: 10-90 ℃;
O 2 the flow range is as follows: 500sccm to 1000sccm.
Since the material of the core layer 2 in this embodiment is amorphous carbon, the removal of the core layer 2 in this step mainly uses high-flow O 2 And the high-voltage condition is carried out, and meanwhile, in order to ensure that the core layer can be removed completely and reduce the damage to other film layers, the lower radio frequency power supply power is not started.
Further, in the process of removing the core layer 2, due to O 2 And does not react with the material of the side wall layer 3, so that there is substantially no lateral loss of the outer wall and the inner wall of the side wall after the core layer 2 is removed (i.e., the thickness of the side wall is substantially unchanged), and thus the CD between adjacent side walls is still equal to the CD of the position where the prokaryotic core layer is located, i.e., b = a in fig. 6.
Referring to fig. 7, the material layer to be etched 1 is etched by using the residual mask layer 3 as a mask, and a target pattern is formed in the material layer to be etched 1.
In this step, etching the material layer to be etched 1 by using the remaining mask layer 3 (sidewall) as a mask includes:
starting the upper radio frequency power and the lower radio frequency power, taking the residual mask layer 3 as a mask, and etching the material layer 1 to be etched by using second etching gas;
preferably, the upper rf power range used in this step is: 100W-6000W; the lower rf power range is: 10W to 2000W. The second etching gas comprises O 2 And SO 2 。
The process parameters for etching the material layer to be etched by using the second etching gas in the step further comprise:
the process chamber pressure ranges are: 2 mT-100 mT;
the process chamber pressure ranges are: 10-90 ℃;
O 2 the flow range is as follows: 10-200 sccm;
SO 2 the flow range is as follows: 10-300 sccm.
In the step, the residual mask layer 3 (side wall) is used as a mask to carry out patterned etching on the material to be etched, the upper radio frequency power adopts 100W-6000W to generate plasma, and the lower radio frequency power is 10W-2000W to provide energy and direction for the plasma, so that anisotropic etching is enhanced. When the target pattern is etched, the CD of the region between the side walls is substantially consistent with the CD of the region where the prokaryotic core layer 2 is located, namely b = a, so that the etching rate of the region between the side walls is substantially consistent with that of the region where the prokaryotic core layer 2 is located, and therefore the problem of pith walking can be effectively avoided, meanwhile, in the etching process, due to the fact that the etching rates are consistent, the transverse damages on the inner side and the outer side of the side walls are also substantially consistent, and the CD of the position CD of the prokaryotic core layer after the target pattern is finally etched is equal to the CD between the side walls, namely a2= b2. Therefore, the problem of odd-even loading of the CD is effectively solved, and the performance of the device is greatly improved.
The method of this embodiment takes a self-aligned dual patterning process as an example, and the preferred process recipe of each step is as follows:
fig. 8a is an etched pattern formed by adopting a traditional process method, fig. 8b is an etched pattern obtained by adopting the method of the embodiment, and the comparison of the two etching methods shows that the CD odd-even loading problem is obviously improved after the etching by adopting the method of the invention.
Furthermore, the method not only can solve the problem of CD odd-even loading formed in the etching process, but also can improve the depth loading problem, and the process only needs to deposit a side wall protective film once, so that the requirements on photoetching and etching uniformity are not high, the process flow is simple, the controllability is better, the cost is reduced, and the device performance is improved. The etching method of the invention is not limited to the self-aligned double patterning process, and can also be applied to all other processes related to patterning etching, such as the self-aligned quadruple patterning process.
While embodiments of the present invention have been described above, the above description is illustrative, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.
Claims (10)
1. An etching method of a semiconductor structure is characterized by comprising the following steps:
providing a material layer to be etched, wherein a plurality of discrete core layers are formed on the material layer to be etched;
forming a mask layer on the material layer to be etched exposed among the core layers and on the top and the side wall of the core layers;
forming a protective layer on the mask layer;
carrying out anisotropic etching on the protective layer and part of the mask layer until the protective layer is completely removed and the top of the core layer and part of the material layer to be etched between the adjacent core layers are exposed;
removing the core layer;
and etching the material layer to be etched by taking the residual mask layer as a mask, and forming a target pattern in the material layer to be etched.
2. The etching method according to claim 1, wherein the mask layer on the side wall of the core layer and the protection layer form a side wall, and a lateral spacing dimension between outer walls of adjacent side walls is smaller than a width dimension of the core layer.
3. The etching method according to claim 1, wherein the forming of the protective layer on the mask layer comprises:
depositing a protective layer with a set thickness on the mask layer through a first process gas, wherein the first process gas is CH 3 F、CH 2 F 2 、HBr、CH 4 And, siCl 4 And O 2 One or more of;
the protective layer is silicon oxide, CF type polymer or Si-O-Br type polymer.
4. The etching method according to claim 3, wherein the set thickness is
5. The etching method according to claim 3, wherein the first process gas comprises SiCl 4 And O 2 ；
The process parameters for depositing the protective layer with the set thickness on the mask layer through the first process gas comprise:
the upper radio frequency power range is 100W-2000W;
the lower radio frequency power range is 10W-1500W;
the pressure range of the process chamber is 3 mT-100 mT;
the temperature range of the process chamber is 10-90 ℃;
SiCl 4 the flow range of (A) is: 1 sccm-100 sccm;
O 2 the flow range of (A) is: 1sccm to 100sccm.
6. The etching method according to claim 1, wherein the anisotropic etching of the protection layer and a portion of the mask layer comprises:
starting upper radio frequency power and lower radio frequency power, and removing the protective layer and part of the mask layer above the part of the material layer to be etched, which is positioned above the top of the core layer and between the adjacent core layers, by using first etching gas;
wherein, the upper radio frequency power range is: 100W-3000W; the lower rf power range is: 50W to 1000W.
7. The etching method according to claim 6, wherein the first etching gas comprises CF 4 And CHF 3 。
8. The etching method according to claim 7, wherein the process parameters for performing anisotropic etching on the protection layer and a part of the mask layer further comprise:
the process chamber pressure ranges are: 3 mT-100 mT;
the process chamber temperature range is: 10-90 ℃;
CF 4 the flow range of (A) is: 10sccm to 200sccm;
CHF 3 the flow range of (A) is: 10sccm to 200sccm.
9. The etching method according to claim 1, wherein in the step of removing the core layer, only upper radio frequency power is turned on;
wherein, the upper radio frequency power range is: 100W to 6000W.
10. The etching method according to claim 1, wherein the etching the material layer to be etched by using the remaining mask layer as a mask comprises:
starting upper radio frequency power and lower radio frequency power, taking the residual mask layer as a mask, and etching the material layer to be etched by using second etching gas;
wherein, the upper radio frequency power range is: 100W-6000W; the lower rf power range is: 10W to 2000W.
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