CN115909978A

CN115909978A - Gate driving circuit and display device including the same

Info

Publication number: CN115909978A
Application number: CN202211014873.9A
Authority: CN
Inventors: 刘载星; 朴帝薰
Original assignee: LG Display Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 2021-09-30
Filing date: 2022-08-23
Publication date: 2023-04-04
Also published as: US11721290B2; US20230097004A1

Abstract

A gate driving circuit and a display device including the same are disclosed. The gate driving circuit includes: a plurality of signal transmitters receiving a start pulse, a shift clock, a charge/discharge clock, a reverse bias clock, a high potential driving voltage, and a low potential reference voltage, and connected in a cascade structure, wherein an Nth signal transmitter of the plurality of signal transmitters includes: a first control node; a second control node; a first controller for controlling charging and discharging of the first control node by using at least one transistor inputted to the reverse bias clock; a second controller for controlling charging and discharging of the second control node; a first output buffer for outputting a carry pulse in response to voltages of the first control node and the second control node; and a second output buffer for outputting the gate pulse, wherein N is a positive integer.

Description

Gate driving circuit and display device including the same

Cross Reference to Related Applications

This application claims priority and benefit to korean patent application No.10-2021-0130008, filed on 30/9/2021 and korean patent application No.10-2021-0182453, filed on 20/12/2021, the entire disclosures of which are incorporated herein by reference.

Technical Field

The present invention relates to a gate driving circuit and a display device including the same.

Background

Electroluminescent display devices may be classified into inorganic light emitting display devices and organic light emitting display devices according to the material of a light emitting layer. The active matrix type organic light emitting display device includes an Organic Light Emitting Diode (OLED) that generates light by itself and has advantages in high response speed, high light emitting efficiency, high luminance, and a wide viewing angle. In the organic light emitting display device, an OLED is formed in each pixel. The organic light emitting display device has a high response speed, a high light emitting efficiency, a high luminance, and a wide viewing angle, and can represent black gray in perfect black (perfect black), thereby achieving a high contrast ratio and a high color reproduction rate.

A pixel circuit of an electroluminescent display device includes a light emitting element, a driving element for driving the light emitting element, and one or more switching elements. The switching element is turned on or off according to the gate voltage to connect or disconnect a main node of the pixel circuit. The driving element and the switching element may be implemented together as one transistor.

The gate drive circuit generates a gate pulse to be applied to a gate of a switching element constituting the pixel circuit. Since the gate driving circuit is composed of many transistors and the size of the transistors is increased, the gate driving circuit disposed on the substrate of the display panel may cause the frame area of the display panel to be increased. For example, when the Q-node maintains a high voltage in the gate driving circuit, an on-state transistor having a large channel width may be applied to compensate for a leakage current of an off-state transistor connected to the Q-node. For this reason, it is difficult to reduce the size of the frame region occupied by the gate driving circuit in the display panel.

Disclosure of Invention

The present invention aims to address all of the above needs and/or solve the above problems.

The invention provides a gate driving circuit capable of reducing a frame region of a display panel and preventing leakage current, and a display device including the gate driving circuit.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those of ordinary skill in the art from the following description.

A gate driving circuit according to an embodiment of the present invention includes a plurality of signal transmitters that receive a start pulse, a shift clock, a charge/discharge clock, a back-bias (back-bias) clock, a high-potential driving voltage, and a low-potential reference voltage, and are connected in a cascade structure. An Nth (N is a positive integer) signal transmitter of the plurality of signal transmitters includes: a first control node; a second control node; a first controller for controlling charging and discharging of the first control node by using at least one transistor inputted to the reverse bias clock; a second controller for controlling charging and discharging of the second control node; a first output buffer for outputting a carry pulse in response to voltages of the first control node and the second control node; and a second output buffer for outputting the gate pulse.

A gate driving circuit according to another embodiment of the present invention includes a plurality of signal transmitters that receive a start pulse, a shift clock, a charge/discharge clock, a reverse bias clock, a high potential driving voltage, and a low potential reference voltage, and are connected in a cascade structure. An Nth (N is a positive integer) signal transmitter of the plurality of signal transmitters includes: a first control node; a second control node; a first controller for controlling charging and discharging of the first control node by using at least one four-terminal transistor to which the reverse bias clock is input; a second controller for controlling charging and discharging of the second control node by using at least one four-terminal transistor to which the reverse bias clock is input; a first output buffer for outputting a carry pulse in response to voltages of the first control node and the second control node; and a second output buffer for outputting the gate pulse.

The display device of the invention comprises the grid drive circuit.

A display device according to an embodiment of the present invention includes: a display panel including a plurality of data lines to which data voltages are applied, a plurality of gate lines to which gate pulses are applied, a plurality of clock lines, a plurality of power lines, a plurality of pixels, and a gate driving circuit for generating the gate pulses, the gate driving circuit including a plurality of signal transmitters receiving a start pulse, a shift clock, a charge/discharge clock, a reverse bias clock, a high potential driving voltage, and a low potential reference voltage, and connected in a cascade structure. An Nth (N is a positive integer) signal transmitter of the plurality of signal transmitters includes: a first control node; a second control node; a first controller for controlling charging and discharging of the first control node by using at least one transistor inputted to the reverse bias clock; a second controller for controlling charging and discharging of the second control node; a first output buffer for outputting a carry pulse in response to voltages of the first control node and the second control node; and a second output buffer for outputting the gate pulse.

According to the present invention, by using one or more four-terminal transistors to which a reverse bias clock is inputted, it is possible to minimize a leakage current and increase an on-current (on-current) when a high voltage is transmitted

The gate driving circuit of the present invention can minimize a leakage current of a transistor and minimize the size of the transistor constituting a controller, thereby reducing a bezel area of a display panel and also reducing power consumption of a display device. As a result of the simulation, it was confirmed that the leak current of the four-terminal transistor constituting the gate driver circuit was suppressed to nanoamperes (nano-ampere) or less.

According to the present invention, since the size of the transistor of the gate driving circuit is reduced, the current of the clock wiring can be reduced, and since most of the current is used for controlling the charging and discharging of the node, the reactive power can be reduced.

The effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned above will be clearly understood by those skilled in the art from the following description and the appended claims.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent to those of ordinary skill in the art from the exemplary embodiments described in detail with reference to the accompanying drawings. In the drawings:

fig. 1 is a view schematically illustrating a shift register of a gate driving circuit according to an embodiment of the present invention;

fig. 2 and 3 are views illustrating a shift register provided in a display panel;

fig. 4 is a view illustrating transfer characteristics of a three-terminal transistor;

fig. 5 is a view illustrating transfer characteristics of a four-terminal transistor when a negative reverse bias voltage is applied to the transistor;

fig. 6 is a view illustrating transfer characteristics of a four-terminal transistor when a reverse bias clock is applied to a second gate of the transistor;

fig. 7 is a circuit diagram illustrating the signal transmitter in detail;

FIG. 8 is a waveform diagram illustrating a clock, control node voltage and gate pulses;

FIG. 9 is a waveform diagram illustrating clock voltages;

fig. 10 is a circuit diagram illustrating an operation of the gate driving circuit in the first period shown in fig. 8;

fig. 11 is a circuit diagram illustrating an operation of the gate driving circuit in the second period shown in fig. 8;

fig. 12 is a circuit diagram illustrating an operation of the gate driving circuit in the third period shown in fig. 8;

fig. 13 is a circuit diagram illustrating an operation of the gate driving circuit in the fourth period shown in fig. 8;

fig. 14 is a block diagram illustrating a display device according to an embodiment of the present invention;

fig. 15 is a sectional view illustrating a sectional structure of the display panel shown in fig. 14.

Detailed Description

Advantages and features of the present invention and a method of implementing the same will be more clearly understood through embodiments described below with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments, but may be implemented in various different forms. The embodiments of the present invention will make the disclosure of the present invention complete and will fully convey the scope of the invention to those skilled in the art. The invention is limited only by the scope of the appended claims.

Shapes, sizes, proportions, angles, numbers, and the like shown in the drawings for describing the embodiments of the present invention are merely examples, and the present invention is not limited thereto. Like reference numerals generally refer to like elements throughout the specification. In addition, in describing the present invention, detailed descriptions of known related art may be omitted to avoid unnecessarily obscuring the subject matter of the present invention.

Terms such as "comprising," including, "" having, "and the like, as used herein, are generally intended to allow for the addition of other components, unless such terms are used with the term" only.

Even if not explicitly described, the composition is to be interpreted as including the usual error ranges.

When terms such as "on 8230," above 8230, "" below, "" at 8230, "" below, "" 8230, "" after, "are used to describe the positional relationship between two components, one or more components may be located between the two components unless the terms are used with the terms" immediately "or" directly.

The terms "first," "second," and the like may be used to distinguish one element from another, but the function or structure of an element is not limited by the number or name of such element preceding it.

The following embodiments may be combined or combined with each other partially or entirely and may be technically associated and operated in various ways. These embodiments may be implemented independently of each other or in association with each other.

In the display device of the present invention, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistor may be implemented as an oxide thin film transistor (oxide TFT) including an oxide semiconductor, a Low Temperature Polysilicon (LTPS) TFT including low temperature polysilicon, or the like. In the embodiment, a description will be given based on an example in which a transistor of a pixel circuit is implemented as an n-channel oxide TFT.

The transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In a transistor, carriers start to flow from the source. The drain is the electrode from which carriers flow out of the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since carriers are electrons, a source voltage is a voltage lower than a drain voltage, so that electrons can flow from the source to the drain. An n-channel transistor has a current direction flowing from the drain to the source. In the case of a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), since carriers are holes, a source voltage is higher than a drain voltage, so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, a current flows from the source to the drain. Note that the source and drain of the transistor are not fixed. For example, the source and drain may vary depending on the applied voltage. Therefore, the present invention is not limited by the source and drain of the transistor. In the following description, the source and the drain of the transistor will be referred to as a first electrode and a second electrode.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be described mainly with respect to an organic light emitting display device, but the present invention is not limited thereto.

Referring to fig. 1 to 3, the gate driving circuit of the present invention includes a shift register which is synchronized with shift clocks CLK1 to CLK4 and sequentially outputs pulses of gate signals (hereinafter, referred to as "gate pulses") Gout (N-1) to Gout (N + 2). Here, N is a positive integer.

The shift register includes signal transmitters ST (N-1) to ST (N + 2) which are connected in a cascade structure, thereby sequentially generating outputs, i.e., gate pulses Gout (N-1) to Gout (N + 2). Each of the signal transmitters ST (N-1) to ST (N + 2) includes: a VST node to which a start signal VST or carry pulses CAR (N-1) to CAR (N + 2) from a preceding (preceding) signal transmitter is input; a CLK node to which clocks CLK1 to CLK4, CLK1_ CAR, CLK2_ CAR, CLK1_ BB, CLK2_ BB are input; a VDD node to which a high potential driving voltage VGH is applied; a VSS node to which a low potential reference voltage VGL is applied; a first control node Q and a second control node QB for driving the cache transistor; and so on.

The start signal VST is input to the first signal transmitter. In fig. 1, the N-1 ST signal transmitter ST (N-1) may be a first signal transmitter. The shift clocks CLK1 to CLK4 are illustrated as 4-phase (four-phase) clocks, but are not limited thereto. For example, the shift clocks CLK1 to CLK4 may be two-phase clocks, four-phase clocks, six-phase clocks, or eight-phase clocks.

The compensation clocks CLK1_ CAR, CLK2_ CAR, CLK1_ BB, CLK2_ BB are further input to the shift register. The compensated clocks CLK1_ CAR, CLK2_ CAR, CLK1_ BB, CLK2_ BB include: charge/discharge clocks CLK1_ CAR, CLK2_ CAR for increasing a conduction current Ion generated when transistors charging/discharging the control nodes Q and QB are turned on; and reverse bias clocks CLK1_ BB, CLK2_ BB for preventing a static leakage current Ioff generated in an off state of the transistors.

The high and low voltages of the charge/discharge clocks CLK1_ CAR, CLK2_ CAR are set to voltage levels different from those of the reverse bias clocks CLK1_ BB, CLK2_ BB. The first charging/discharging clock CLK1_ CAR is generated as a pulse in phase with the first reverse bias clock CLK1_ BB. The second charging/discharging clock CLK2_ CAR is generated as a pulse in phase with the second reverse bias clock CLK2_ BB. The charge/discharge clocks CLK1_ CAR, CLK2_ CAR and the reverse bias clocks CLK1_ BB, CLK2_ BB are illustrated as two-phase clocks, but are not limited thereto.

The signal transmitters ST (N) to ST (N + 2) dependently connected to the N-1 signal transmitter ST (N-1) receive the carry pulse CAR as a start signal from the previous signal transmitter and start to operate. Each of the signal transmitters ST (N-1) to ST (N + 2) outputs the carry pulse CAR via the first output node, and simultaneously outputs the gate pulses Gout (N-1) to Gout (N + 2) via the second output node.

As shown in fig. 2 and 3, the gate driving circuit may be provided in the display panel 100 on which an input image is reproduced. In fig. 2 and 3, the shift register of the gate driving circuit may include: first shift registers (STL (N-1) to STL (N + 2)) provided in a frame area located outside a side of the pixel array AA reproducing the input image; and second shift registers (STR (N-1) to STR (N + 2)) disposed in a frame region located outside the other side of the pixel array AA. In fig. 3, a Chip On Film (COF) may be attached to the display panel 100. The data driver or both the data driver and the touch sensor driver may be integrated in the driving IC DIC mounted on the COF. In fig. 3, GL denotes a gate line to which a gate pulse output from the signal transmitter is applied. CL denotes a clock line to which the clocks CLK1 to CLK4, CLK1_ CAR, CLK2_ CAR, CLK1_ BB, CLK2_ BB are input and a power supply line to which constant voltages VGH and VGL are applied.

Fig. 4 is a view illustrating transfer characteristics of a three-terminal transistor. Fig. 5 is a view illustrating transfer characteristics of the four-terminal transistor when a negative reverse bias voltage is applied to the transistor. Fig. 6 is a view illustrating transfer characteristics of the four-terminal transistor when a reverse bias clock CLK _ BB is applied to the second gate (or back gate) of the transistor. In fig. 4 to 6, the horizontal axis is the gate-source voltage Vgs of the transistor, and the vertical axis is the drain-source current Ids of the transistor. Ioff is a drain current generated when the transistor is turned off, and Ion is an on current generated when the transistor is turned on.

Referring to fig. 4, the three-terminal transistor includes a gate electrode, a first electrode, and a second electrode. The shift clock CLK is applied to the gate of the transistor, and the high potential driving voltage VGH may be applied to the first electrode. In fig. 4, the shift clock CLK swings between the high potential driving voltage VGH and the low potential reference voltage VGL. When the transistor is turned on/off, the voltage of the second electrode may be changed between VGL and VGH. When the three-terminal transistor is implemented as an n-channel oxide TFT, the threshold voltage Vth of the transistor may be close to 0V. In this case, the leakage current Ioff may increase.

Referring to fig. 5, the four terminal transistor includes a first gate electrode, a second gate electrode, a first electrode, and a second electrode. The gate-source voltage Vgs of the four-terminal transistor is the voltage between the first gate and the second electrode. The reverse bias voltage Vbs is a voltage between the second gate and the second electrode. The shift clock CLK is applied to the first gate of the transistor, and a low constant voltage, for example, a third low potential reference voltage VGL3, may be applied to the second gate. The high potential driving voltage VGH may be applied to the first electrode. In fig. 5, the shift clock CLK swings between the high potential driving voltage VGH and the first low potential reference voltage VGL1. When the transistor is turned on/off, the voltage of the second electrode may vary between VGL and VGH-Vth. When a negative reverse bias voltage Vbs is applied to the transistor, the threshold voltage Vth of the transistor may shift to a positive voltage greater than 0V. As a result, the leakage current Ioff is reduced to reduce power consumption.

Referring to fig. 6, the shift clock CLK may be applied to a first gate of the four-terminal transistor, and the reverse bias clock CLK _ BB may be applied to a second gate of the four-terminal transistor. A high potential driving voltage VGH2 may be applied to the first electrode. In fig. 6, the shift clock CLK swings between the second high potential driving voltage VGH2 and the first low potential reference voltage VGL1. The reverse bias clock CLK _ BB may swing between the first high potential driving voltage VGH1 and the third low potential reference voltage VGL3. When the transistor is turned on/off, the voltage of the second electrode may be changed between VGL1 and VGH2. When the reverse bias clock CLK _ BB is the third low potential reference voltage VGL3, the negative reverse bias voltage Vbs <0 is applied to the transistor, thereby reducing the leakage current Ioff. When the reverse bias clock CLK _ BB is the first high potential driving voltage VGH1, the forward-reverse bias voltage Vbs >0 is applied to the transistor, whereby the on-current Ion increases. Therefore, the reverse bias clock CLK _ BB can improve the on/off characteristics of the transistor at the same time. The high voltage of the reverse bias clock CLK _ BB may be appropriately set in consideration of PBTS (positive bias temperature stress), and the low voltage may be appropriately set in consideration of the leakage current Ioff.

In fig. 5, when a high voltage, which is a high potential driving voltage VGH, is applied to the first electrode, a negative reverse bias is applied to the second gate due to an increase in the source voltage Vs, whereby the transistor is turned off. In the four-terminal transistor driving method shown in fig. 5, the high-potential driving voltage VGH is not transmitted to the second electrode. In the four-terminal transistor driving method shown in fig. 6, when the high-potential driving voltage VGH2 is applied to the first electrode, the high-potential driving voltage VGH2 may be transferred to the second electrode.

Fig. 7 is a circuit diagram illustrating in detail the nth signal transmitter ST (N) according to an embodiment of the present invention. The signal transmitters other than the nth signal transmitter ST (N) may be implemented using the same circuit as the substrate of the nth signal transmitter ST (N). Fig. 8 is a waveform diagram illustrating a clock, a control node voltage, and a gate pulse input to the gate driving circuit. Fig. 9 is a waveform diagram illustrating a clock voltage.

Referring to fig. 7 to 9, the nth signal transmitter ST (N) includes a first control node Q, a second control node QB, a first controller 10 for controlling charging and discharging of the first control node Q by using at least one transistor to which a reverse bias clock CLK1_ BB or CLK2_ BB is applied; a second controller 20 for controlling charging and discharging of the second control node QB by using at least one transistor to which the reverse bias clock CLK2_ BB is applied; a first output buffer 30 for outputting a carry pulse CAR (N) in response to voltages of the first and second control nodes Q and QB; and a second output buffer 40 for outputting the gate pulse Gout (N) in response to the voltages of the first and second control nodes Q and QB. All the transistors T1 to T10 constituting the nth signal transmitter ST (N) may be implemented as N-channel oxide TFTs.

Clocks such as a start pulse or a carry pulse CAR (N-1), a shift clock CLK1, and compensation clocks CLK1_ CAR, CLK1_ BB, CLK2_ CAR, CLK2_ BB are input to the nth signal transmitter ST (N). Constant voltages such as the high potential driving voltage VGH2 and the low potential reference voltages VGL1, VGL2, and VGL3 are applied to the nth signal transmitter ST (N).

As shown in fig. 8 and 9, the first compensation clock pair CLK1_ CAR and CLK1_ BB includes a first charge/discharge clock CLK1_ CAR and a first reverse bias clock CLK1_ BB generated in phase. The high and low voltages of the first charging/discharging clock CLK1_ CAR and the first reverse bias clock CLK1_ BB are different from each other.

The second compensated clock pair CLK2_ CAR and CLK2_ BB includes a second charge/discharge clock CLK2_ CAR and a second reverse bias clock CLK2_ BB generated in phase. The high and low voltages of the second charge/discharge clock CLK2_ CAR and the second reverse bias clock CLK2_ BB are different from each other. The first compensated clock pair CLK1_ CAR and CLK1_ BB is inverted from the second compensated clock pair CLK2_ CAR and CLK2_ BB. That is, the second compensation clock pair CLK2_ CAR and CLK2_ BB has a phase difference of 180 degrees with respect to the first compensation clock pair CLK1_ CAR and CLK1_ BB.

The high voltage VGH2 of the first and second charging/discharging clocks CLK1_ CAR and CLK2_ CAR is set to be higher than the high voltage VGH1 of the first and second reverse bias clocks CLK1_ BB and CLK2_ BB. Each of the high voltages VGH2 of the first and second charging/discharging clocks CLK1_ CAR and CLK2_ CAR may be set to a voltage higher than or equal to the high voltage VGH2 of the shift clock CLK1. In fig. 9, the high voltage VGH2 of the first and second charging/discharging clocks CLK1_ CAR and CLK2_ CAR is illustrated as the same voltage as the high voltage VGH2 of the shift clock CLK1, but is not limited thereto.

The low voltage VGL2 of the first and second charging/discharging clocks CLK1_ CAR and CLK2_ CAR is set to be higher than the low voltage VGL3 of the first and second reverse bias clocks CLK1_ BB and CLK2_ BB. The low voltage VGL2 of the first and second charging/discharging clocks CLK1_ CAR and CLK2_ CAR may be set to be lower than the low voltage VGL1 of the shift clock CLK1.

The nth signal transmitter ST (N) includes: a VST node to which a start pulse VST or a carry pulse CAR (N-1) from a previous signal transmitter ST (N-1) is inputted; a VDD node to which a high potential driving voltage VGH2 is applied; a VSS node to which low potential reference voltages VGL1, VGL2, and VGL3 are applied; and a CLK node to which a clock is input. The VST node and the CLK node are connected to a clock line in the display panel 100.

The nth signal transmitter ST (N) outputs the carry pulse CAR (N) via the first output node 31 and the gate pulse Gout (N) via the second output node 41.

The first controller 10 charges and discharges the first and second control nodes Q and QB by receiving the start pulse VST or the N-1 carry pulse CAR (N-1) from the previous signal transmitter ST (N-1) and also receiving the first and second charge/discharge clocks CLK1_ CAR and CLK2_ CAR.

The first controller 10 may include at least one four-terminal transistor to which a reverse bias clock is input. For example, the first controller 10 includes at least first to third transistors T1, T2, T3.

The first transistor T1 connects a VST node, to which the start pulse VST or the N-1 th carry pulse CAR (N-1) is applied, to the first control node Q in response to the second charge/discharge clock CLK2_ CAR. The first transistor T1 is implemented as a four-terminal transistor. The first transistor T1 includes a first gate connected to the 2-1CLK node to which the second charging/discharging clock CLK2_ CAR is input, a second gate connected to the 2-2CLK node to which the second reverse bias clock CLK2_ BB is input, a first electrode connected to the VST node to which the start pulse VST or the N-1 carry pulse CAR (N-1) is input, and a second electrode connected to the first control node Q.

The second transistor T2 connects the first control node Q to the third node n3 in response to the first charge/discharge clock CLK1_ CAR. The second transistor T2 is implemented as a four-terminal transistor. The second transistor T2 includes a first gate connected to the 1 st-1 st CLK node to which the first charge/discharge clock CLK1_ CAR is input, a second gate connected to the 1 st-2 st CLK node to which the first reverse bias clock CLK1_ BB is input, a first electrode connected to the first control node Q, and a second electrode connected to the third node n3.

The third transistor T3 connects the third node n3 to the second VSS node to which the second low potential reference voltage VGL2 is applied, in response to the high voltage of the second control node QB. The second low potential reference voltage VGL2 is a constant voltage lower than the first low potential reference voltage VGL1. The third transistor T3 is implemented as a four-terminal transistor. The third transistor T3 includes a first gate connected to the second control node QB, a second gate connected to the third VSS node to which the third low potential reference voltage VGL3 is applied, a first electrode connected to the third node n3, and a second electrode connected to the second VSS node. The third low potential reference voltage VGL3 is a constant voltage lower than the second low potential reference voltage VGL2.

The second controller 20 may include at least one four-terminal transistor to which a reverse bias clock is input. For example, the second controller 20 includes at least fourth and fifth transistors T4 and T5.

The fourth transistor T4 connects the VDD node, to which the second high potential driving voltage VGH2 is applied, to the second control node QB in response to the second charge/discharge clock CLK2_ CAR. The fourth transistor T4 is implemented as a four-terminal transistor. The fourth transistor T4 includes a first gate connected to the 2-1CLK node to which the second charging/discharging clock CLK2_ CAR is input, a second gate connected to the 2-2CLK node to which the second reverse bias clock CLK2_ BB is input, a first electrode connected to the VDD node to which the second high potential driving voltage VGH2 is applied, and a second electrode connected to the second control node QB.

The fifth transistor T5 connects the 2-1CLK node, to which the second charging/discharging clock CLK2_ CAR is input, to the second control node QB in response to the high voltage of the first control node Q. The fifth transistor T5 is implemented as a four-terminal transistor. The fifth transistor T5 includes a first gate connected to the first control node Q, a second gate connected to the 2-2CLK node to which the second reverse bias clock CLK2_ BB is input, a first electrode connected to the 2-1CLK node to which the second charge/discharge clock CLK2_ CAR is input, and a second electrode connected to the second control node QB.

The first output buffer 30 may include at least one four-terminal transistor having a second gate to which a constant voltage is applied. For example, the first output buffer 30 includes at least sixth to eighth transistors T6, T7 and T8.

The sixth transistor T6 is a pull-up transistor that charges the first output node 31 in response to the boost voltage VGH2+ α of the first control node Q. When the sixth transistor T6 is turned on, the voltage of the second gate is boosted due to bootstrapping by the second capacitor C2 to increase the on-current Ion; when the sixth transistor T6 is turned off, a negative reverse bias is applied to minimize the leakage current. When the sixth transistor T6 is turned on, the carry pulse CAR (N) rises to the high voltage VGH2 of the first charge/discharge clock CLK1_ CAR. The sixth transistor T6 is implemented as a four-terminal transistor having a bootstrapped back-bias structure. The sixth transistor T6 includes a first gate connected to the first control node Q, a second gate connected to the fourth node n4, a first electrode connected to the 1 st-1 st CLK node to which the first charge/discharge clock CLK1_ CAR is input, and a second electrode connected to the first output node 31. The second capacitor C2 is connected between the fourth node n4 and the first output node 31.

The seventh transistor T7 is a pull-down transistor that discharges the first output node 31 in response to the high voltage VGH2 of the second control node QB. When the seventh transistor T7 is turned on, the carry pulse CAR (N) is discharged until the second low potential reference voltage VGL2 is reached. The seventh transistor is implemented as a four-terminal transistor. The seventh transistor T7 includes a first gate connected to the second control node QB, a second gate connected to the third VSS node to which the third low potential reference voltage VGL3 is applied, a first electrode connected to the first output node, and a second electrode connected to the second VSS node to which the second low potential reference voltage VGL2 is applied. The third capacitor C3 is formed between the second control node QB and the second VSS node to suppress the ripple of the second control node QB.

The eighth transistor T8 connects the third VSS node, to which the third low potential reference voltage VGL3 is applied, to the fourth node n4 in response to the high voltage of the second reverse bias clock CLK2_ BB. The eighth transistor T8 is implemented as a three-terminal transistor. The eighth transistor T8 includes a gate connected to the 2 nd-2 CLK node to which the second reverse bias clock CLK2_ BB is applied, a first electrode connected to the third VSS node, and a second electrode connected to the fourth node n4.

The second output buffer 40 includes at least ninth and tenth transistors T9 and T10. The ninth and tenth transistors T9 and T10 may be implemented as large capacity three-terminal transistors having a channel ratio (channel ratio) higher than that of the other transistors T1 to T8. When the source voltages of the ninth and tenth transistors T9 and T10 are low voltages, the gate voltages of the ninth and tenth transistors T9 and T10 (i.e., the low voltages of the control nodes Q and QB) are always lower. Therefore, since the gate-source voltage Vgs of the ninth and tenth transistors T9 and T10 is always Vgs <0 in the off state, even if the threshold voltage Vth of the ninth and tenth transistors T9 and T10 is close to 0, a leakage current Ioff generated when the gate-source voltage Vgs is 0 or close to 0 does not occur. Thus, the ninth and tenth transistors T9 and T10 do not have leakage current in the ninth and tenth transistors T9 and T10 even if implemented as three-terminal transistors.

The ninth transistor T9 is a pull-up transistor that charges the second output node 41 in response to the boosted voltage VGH2+ α of the first control node Q. When the ninth transistor T9 is turned on, the voltage of the first control node Q is boosted due to bootstrap via the first capacitor C1, and the gate pulse Gout (N) rises until reaching the high voltage VGH2 of the first shift clock CLK1. The ninth transistor T9 is implemented as a three-terminal transistor. The ninth transistor T9 includes a gate connected to the first control node Q, a first electrode connected to the third CLK node to which the shift clock CLK1 is input, and a second electrode connected to the second output node 41. The first capacitor C1 is connected between the first control node Q and the second output node 41.

The tenth transistor T10 is a pull-down transistor that discharges the second output node 41 in response to the high voltage VGH2 of the second control node QB. When the tenth transistor T10 is turned on, the gate pulse Gout (N) is discharged until the first low potential reference voltage VGL1 is reached. The tenth transistor T10 is implemented as a three-terminal transistor. The tenth transistor T10 includes a gate connected to the second control node QB, a first electrode connected to the second output node 41, and a second electrode connected to the first VSS node to which the first low potential reference voltage VGL1 is applied.

Referring to fig. 9, the shift clock CLK swings between the second high potential driving voltage VGH2 and the first low potential reference voltage VGL1.

The charging/discharging clock CLK _ CAR swings between the second high potential driving voltage VGH2 and the second low potential reference voltage VGL2 to increase the on-current of the transistor. The second low potential reference voltage VGL2 is set lower than the first low potential reference voltage VGL1.

The low voltage of the reverse bias clock CLK _ BB is set low to apply a negative reverse bias to the transistor, and the high voltage thereof is set low to reduce the Positive Bias Temperature Stress (PBTS). The reverse bias clock CLK _ BB may swing between the first high potential driving voltage VGH1 and the third low potential reference voltage VGL3. The first high potential driving voltage VGH1 is set to be lower than the second high potential driving voltage VGH2. The third low potential reference voltage VGL3 is set lower than the second low potential reference voltage VGL2.

The voltages of the clocks CLK, CLK _ CAR, and CLK _ BB may be set to VGH2=18v, VGH1=8v, vgl1= -6V, vgl2= -10v, and vgl3= -13V, for example. In this case, the swing width of the charging/discharging clock CLK _ CAR is larger than the swing widths of the shift clock CLK and the reverse bias clock CLK _ BB. The swing width of the shift clock CLK is larger than that of the reverse bias clock CLK _ BB. It should be noted that: the voltages of the clocks CLK, CLK _ CAR, and CLK _ BB are not limited to the above example.

The driving period of the nth signal transmitter ST (N) may include a first period P1, a second period P2, a third period P3, and a fourth period P4. Hereinafter, the operation of the nth signal transmitter ST (N) at each period will be described with reference to fig. 10 to 13.

Referring to fig. 10, during the first period P1, the second transistor T2 is turned on according to the high voltage VGH2 of the first charging/discharging clock CLK1_ CAR, and the third, seventh and tenth transistors T3, T7 and T10 are charged according to the high voltage VGH2 of the second control node QB. During the first period P1, the second charge/discharge clock CLK2_ CAR and the second reverse bias clock CLK2_ BB are the low voltages VGL2 and VGL3, respectively, and the voltage of the first control node Q is the low voltage VGL2. As a result, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are turned off in the first period P1. Since a negative reverse bias voltage Vbs <0 is applied to the four-terminal transistors T1, T4, T5, T6 in an off state, an off current Ioff is minimized at Vgs = 0.

During the first period P1, since the positive reverse bias voltage Vbs >0 is applied to the four-terminal transistors T2, T3, and T7 in the on-state, the on-current Ion increases. During the first period P1, the first output node 31 and the second output node 41 are discharged to the first and second VSS nodes through the pull-down transistors T7 and T10. During the first period P1, the voltages of the first and

second output nodes

31 and 41 are the low voltages VGL1 and VGL2, respectively.

Referring to fig. 11, in the second period P2, the carry pulse CAR (N-1) is output from the previous stage ST (N-1), and the second charge/discharge clock CLK2_ CAR and the second reverse bias clock CLK2_ BB are inverted to the high voltages VGH1 and VGH2. During the second period P2, the first transistor T1 and the fourth transistor T4 are turned on according to the high voltage VGH2 of the second charge/discharge clock CLK2_ CAR. At this time, the first control node Q is charged by the high voltage VGH2, and the second control node QB maintains the high voltage VGH2. The first charge/discharge clock CLK1_ CAR and the first reverse bias clock CLK1_ BB are inverted to the low voltages VGL2 and VGL3 during the second period P2. As a result, the transistors T1, T3 to T10 except for the second transistor T2 are turned on during the second period P2.

During the second period P2, a negative reverse bias voltage Vbs <0 is applied to the four-terminal transistor T2 in an off-state, so that an off-current Ioff is minimized at Vgs = 0. Since the positive reverse bias voltage Vbs >0 is applied to the four-terminal transistors T1, T3 to T7 in the on state, the on current Ion increases. During the second period P2, the first output node 31 and the second output node 41 are discharged to the first and second VSS nodes through the pull-down transistors T7 and T10. Accordingly, the voltages of the first and

second output nodes

31 and 41 maintain the low voltages VGL1 and VGL2 during the second period P2.

Referring to fig. 12, in the third period P3, the first charging/discharging clock CLK1_ CAR and the first reverse bias clock CLK1_ BB are inverted to the high voltages VGH1 and VGH2, and the second charging/discharging clock CLK2_ CAR and the second reverse bias clock CLK2_ BB are inverted to the low voltages VGL2 and VGL3. Meanwhile, the shift clock CLK1 is generated at the high voltage VGH2.

When the high voltage VGH2 of the shift clock CLK1 is input to the first electrode of the tenth transistor T10, bootstrap is generated by the first capacitor C1, whereby the voltage of the first control node Q further rises to the boosted voltage VGH2+ α in the third period P3. The second control node QB is discharged through the 2-1CLK node, and its voltage is lowered to the low voltage VGL2. Accordingly, during the third period P3, the second, fifth, sixth, and ninth transistors T2, T5, T6, and T9 are turned on, and the other transistors T1, T3, T4, T7, T8, and T10 are turned off.

During the third period P3, a negative reverse bias voltage Vbs <0 is applied to the four-terminal transistors T1, T3, T4, T7 in an off-state, so that the off-current Ioff is minimized when Vgs = 0. Since the positive reverse bias voltage Vbs >0 is applied to the four-terminal transistors T2, T5, T6 in the on state, the on current Ion increases. During the third period P3, the first output node 31 and the second output node 41 are charged with the voltage supplied via the pull-up transistors T6 and T9. Therefore, during the third period P3, the gate pulse Gout (N) is generated at the high voltage VGH2, and the carry pulse CAR (N) is also generated at the high voltage VGH2. The gate pulse Gout (N) is applied to the gate line GL of the display panel 100. The carry pulse CAR (N) is applied to the VST node of the following (nex) signal transmitter ST (N + 1).

Referring to fig. 13, in the fourth period P4, the second charging/discharging clock CLK2_ CAR and the second reverse bias clock CLK2_ BB are inverted to the high voltages VGH1 and VGH2, and the first charging/discharging clock CLK1_ CAR and the first reverse bias clock CLK1_ BB are inverted to the low voltages VGL2 and VGL3. Meanwhile, the shift clock CLK1 is inverted to the low voltage VGL1. Accordingly, during the fourth period P4, the first transistor T1, the third transistor T3, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 are turned on, and the other transistors T2, T5, T6, and T9 are turned off. Thereby, during the tenth period P4, the first control node Q is discharged by the VST node through the first transistor T1, and its voltage is lowered to the low voltage VGL2. At this time, the second control node QB is charged by the high potential driving voltage VGH2 applied via the fourth transistor T4, so that the voltage thereof is increased to the high voltage VGH2, and the third, seventh and tenth transistors T3, T7 and T10 are turned on.

During the fourth period P4, a negative reverse bias voltage Vbs <0 is applied to the four-terminal transistors T2, T5, T6 in an off-state, so that an off-current Ioff is minimized at Vgs = 0. Since the positive reverse bias voltage Vbs >0 is applied to the four-terminal transistors T1, T3, T4 in the on state, the on current Ion increases. During the fourth period P4, the first and

second output nodes

31 and 41 are discharged by the VSS node using the pull-down transistors T7 and T10, so that the voltages thereof are lowered to the low voltages VGL1 and VGL2. Accordingly, in the fourth period P4, the gate pulse Gout (N) is inverted to the low voltage VGL1, and the carry pulse CAR (N) is also inverted to the low voltage VGL2.

The constant voltage DC is applied to the second gates of the third and fourth transistors T3 and T7. This DC reverse bias voltage can be applied to the transistors T3 and T7 under the condition that the transistors T3 and T7 satisfy the gate voltage Vg equal to or greater than the source voltage Vs (Vg ≧ Vs). The gate voltage Vg is a voltage applied to the first gates of the transistors T3 and T7. The source voltage Vs is a voltage applied to the second electrodes of the transistors T3 and T7. A back gate voltage (back gate voltage) Vb applied to the second gates of the transistors T3 and T7 is set lower than the source voltage Vs so that the threshold voltage Vth of the transistors T3 and T7 can be forward-shifted to a voltage higher than 0.

Reverse bias clocks CLK1_ BB and CLK2_ BB are applied to the second gates of the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5. These reverse biases may be applied to the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 in which the source voltage Vs is not fixed and transmits a low voltage or a high voltage according to conditions. When the transistors T1, T2, T4, and T5 are turned on, the back gate voltage Vb is set under the condition Vg > Vb > Vs. Accordingly, the transistors T1, T2, T4, and T5 are turned on by the positive gate voltages Vg and Vb, and the on current Ion increases.

Vb < Vs when the transistors T1, T2, T4 and T5 are off. At this time, since the negative reverse bias voltage Vbs <0 is applied to the transistors T1, T2, T4, and T5, the threshold voltages Vth of the transistors T1, T2, T4, and T5 are forward shifted (Vth > 0), and the leakage current Ioff can be minimized.

The bootstrapped reverse bias voltage may be applied to an element, i.e., the sixth transistor T6 in which the source voltage Vs is not fixed and transmits a low voltage or a high voltage according to conditions. If the back gate voltage Vb is fixed when the sixth transistor T6 transmits a high voltage to the first output node, an excessive negative reverse bias (Vbs < < 0) is applied when the source voltage Vs rises. In this case, the threshold voltage Vth of the sixth transistor T6 may be excessively positively shifted (Vth > > 0), so that a high voltage transfer rate (transfer rate) may be reduced. Therefore, in the bootstrap structure, it is preferable that when the source voltage Vs of the sixth transistor T6 rises, the back gate voltage Vb also rises through the capacitor C2.

Fig. 14 is a block diagram illustrating a display device according to an embodiment of the present invention. Fig. 15 is a sectional view illustrating a sectional structure of the display panel shown in fig. 14.

Referring to fig. 14 and 15, the display device according to the embodiment of the present invention includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and a power supply 140 generating power required to drive the pixels and the display panel driver.

The display panel 100 may be a panel of a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a pixel array that displays an input image on a screen. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 crossing the data lines 102, and a plurality of pixels arranged in a matrix form. The display panel 100 may further include power lines commonly connected to the pixels. The power supply line applies a constant voltage required to drive the pixel 101 to the pixel 101. For example, the display panel 100 includes power lines and clock lines connected to the pixel and gate driving circuit 120.

As shown in fig. 15, the cross-sectional structure of the display panel 100 may include a circuit layer 152, a light emitting element layer 154, and an encapsulation layer 156 stacked on a substrate 150.

The circuit layer 152 may include: a Thin Film Transistor (TFT) array including pixel circuits connected to wirings such as data lines, gate lines, and power supply lines; an array of demultiplexers 112; and a gate driving circuit 120. The wiring and circuit elements of the circuit layer 152 may include a plurality of insulating layers, two or more metal layers separated with an insulating layer therebetween, and an active layer including a semiconductor material. All of the transistors formed in the circuit layer 152 may be implemented as n-channel oxide TFTs having a coplanar structure.

The circuit elements formed in circuit layer 152 may include four-terminal transistors. The first gate electrode (or top gate electrode) and the second gate electrode (or bottom gate electrode) of the four-terminal transistor overlap each other with the semiconductor active pattern interposed therebetween. The first insulating layer is disposed between the second gate electrode and the semiconductor active pattern, and the second insulating layer is disposed between the semiconductor active pattern and the first gate electrode.

The light emitting element layer 154 may include light emitting elements EL driven by pixel circuits. The light emitting elements EL may include red (R), green (G) and blue (B) light emitting elements. In other embodiments, the light emitting element layer 154 may include a white light emitting element and a color filter. The light emitting elements EL in the light emitting element layer 154 may be covered with a multi-passivation layer (multi-passivation layer) including an organic film and an inorganic film.

The light emitting element EL may be implemented as an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an emission layer (EML), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL), but is not limited thereto. When a voltage is applied to the anode and the cathode of the OLED, holes passing through the Hole Transport Layer (HTL) and electrons passing through the Electron Transport Layer (ETL) move to the emission layer (EML), thereby forming excitons. In this case, visible light is emitted from the light emitting layer (EML). The OLED used as the light emitting element EL may have a tandem (tandem) structure in which a plurality of light emitting layers are stacked. The OLED having the series structure can improve brightness and lifetime of the pixel.

The encapsulation layer 156 covers the light emitting element layer 154 to seal the circuit layer 152 and the light emitting element layer 154. The encapsulation layer 156 may be a multi-layered insulating structure in which organic films and inorganic films are alternately stacked. The inorganic film blocks permeation of moisture or oxygen. The organic film planarizes the surface of the inorganic film. When the organic film and the inorganic film are stacked in a multilayer, a movement path of moisture or oxygen becomes longer than that of a single layer, so that permeation of moisture and oxygen which may affect the light emitting element layer 154 can be effectively blocked.

Although not shown, a touch sensor layer is formed on the encapsulation layer 156, and a polarizing plate or a color filter layer may be disposed on the touch sensor layer. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on a change in capacitance before and after the touch input. The touch sensor layer may include an insulating film and a metal interconnection pattern forming a capacitance of the touch sensor. The insulating film may insulate the crossing portions of the metal interconnection patterns and planarize the surface of the touch sensor layer. The polarizing plate may switch polarization of external light reflected by the metal of the touch sensor layer and the circuit layer to improve visibility and contrast. The polarizing plate may be implemented as a polarizing plate in which a linear polarizing plate and a phase retardation film are bonded to each other or a circular polarizing plate. A glass cover (cover glass) may be adhered to the polarizer plate. The color filter layer may include red, green, and blue color filters. The color filter layer may further include a black matrix pattern. The color filter layer may absorb a portion of light reflected from the circuit layer and the touch sensor layer instead of the polarizing plate and improve color purity of an image reproduced on the pixel array.

The pixel array includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of sub-pixels arranged along a row direction (X-axis direction) on the pixel array of the display panel 100. The sub-pixels arranged in one pixel row share the gate line 103. The sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period is time obtained by dividing one frame period by the total number of pixel rows L1 to Ln.

The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel can be applied to a transparent display device that displays an image on a screen and an actual background can be seen. The display panel 100 may be manufactured as a flexible display panel.

To implement color, each pixel 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Each pixel 101 may further include a white sub-pixel. Each sub-pixel includes a pixel circuit. Hereinafter, "pixel" may be understood to have the same meaning as "sub-pixel". Each pixel circuit is connected to a data line, a gate line, and a power supply line.

The pixel circuit includes a light emitting element EL, a driving element for driving the light emitting element, and one or more switching elements. The switching element is turned on or off according to a gate voltage of the gate pulse to connect or disconnect a main node of the pixel circuit. The switching element is turned on in response to the gate-on voltage and turned off in response to the gate-off voltage. In the case of the N-channel oxide TFT, the gate-on voltage is a high potential driving voltage VGH of the gate pulse Gout (N) output from the gate driving circuit 120, and the gate-off voltage is a low potential reference voltage VGL of the gate pulse Gout (N). The driving element and the switching element of the pixel circuit may be implemented as an n-channel oxide TFT having a coplanar structure.

The electrical characteristics of the driving elements may vary between pixels due to element characteristic variations and process variations in the manufacturing process of the display panel, and such variations may increase as the driving time of the pixels elapses. In order to compensate for the deviation in the electrical characteristics of the driving element between pixels, an internal compensation circuit may be built in the pixel circuit, or an external compensation circuit may be connected to the pixel circuit. The internal compensation circuit may be built in the pixel circuit, and sense a variation amount of the threshold voltage of the driving element, thereby compensating the gate-source voltage of the driving element by the variation amount of the threshold voltage. The external compensation circuit may generate a compensation value based on a result of sensing the electrical characteristic of the driving element using the external compensation circuit connected to the pixel circuit, thereby compensating for a change in the electrical characteristic of the driving element. The pixel circuit of the respective sub-pixel may comprise an internal compensation circuit or may be connected to an external compensation circuit.

The pixels may be arranged as actual color pixels and Pentile pixels. The Pentile pixel can drive two sub-pixels having different colors as one pixel 101 by using a preset pixel rendering algorithm (pixel rendering algorithm), thereby achieving a higher resolution than an actual color pixel. The pixel rendering algorithm may utilize the color of light emitted from neighboring pixels to compensate for insufficient color rendering in each pixel.

The power supply 140 generates a DC voltage (or a constant voltage) required to drive the pixel array of the display panel 100 and the display panel driver by using a DC-DC converter. The DC-DC converter may include a charge pump, a rectifier, a buck converter (buck converter), a boost converter (boost converter), and the like. The power supply 140 may adjust a level of a DC input voltage applied from a host system (not shown), thereby generating a constant voltage, such as a gamma reference voltage VGMA; gate voltages VGH, VGL; a pixel driving voltage ELVDD; the low potential pixel reference voltage ELVSS. The gamma reference voltage VGMA is supplied to the data driver 110. The gate voltages VGH, VGL are supplied to the gate driving circuit 120. The pixel driving voltage ELVDD and the low potential pixel reference voltage ELVSS are supplied to the pixels 101 through power supply lines commonly connected to the pixels 101.

The display panel driver writes pixel data of an input image to the pixels of the display panel 100 under the control of the timing controller 130.

The display panel driver includes a data driver 110 and a gate driving circuit 120. The display panel driver may further include a demultiplexer array 112 disposed between the data driver 110 and the data lines 102.

The demultiplexer array 112 sequentially applies the data voltages output from the channels of the data driver 110 to the data lines 102 using a plurality of Demultiplexers (DEMUXs). The DEMUX may include a plurality of switching elements on the display panel 100. When the DEMUX is disposed between the output terminal of the data driver 110 and the data line 102, the number of channels of the data driver 110 may be reduced. The demultiplexer array 112 may be omitted.

The display panel driver may further include a touch sensor driver for driving the touch sensor. The touch sensor driver is omitted from fig. 14. The data driver 110 and the touch sensor driver may be integrated into one driving Integrated Circuit (IC). In a mobile device or a wearable device, the timing controller 130, the power supply 140, the data driver 110, and the like may be integrated into one driving IC.

The display panel driver may operate in a low-speed driving mode under the control of the timing controller 130. The low speed driving mode may be set to analyze the input image and reduce power consumption of the display apparatus when a degree of change of the input image is less than a predetermined number of frames. In the low-speed driving mode, when a still image is input for a certain period of time or more, the refresh rate of the pixels may be reduced to reduce power consumption of the display panel driver and the display panel 100. The low-speed driving mode is not limited to the case where a still image is input. For example, when the display device is operated in a standby mode or a user command or an image is not input to the display panel driver for a certain time, the display panel driver may be operated in a low-speed driving mode.

The data driver 110 receives pixel data of an input image in the form of digital signals from the timing controller 130 and outputs data voltages. The data driver 110 generates a data voltage by converting pixel data of an input image into a gamma compensation voltage every frame period using a digital-to-analog converter (DAC). The gamma reference voltage VGMA is divided into gamma compensation voltages via a voltage dividing circuit for each gray level. The gamma compensation voltage for each gray level is supplied to the DAC of the data driver 110. The data voltage is output via an output buffer in each channel of the data driver 110.

The gate driving circuit 120 may be implemented as a gate-in-panel (GIP) circuit formed on the circuit layer 152 of the display panel 100 together with an interconnection structure of the TFT array and the pixel array. The gate driving circuit 120 may be disposed on the bezel region BZ, which is a non-display region of the display panel 100, or may be dispersed in a pixel array on which an input image is reproduced.

As shown in fig. 14, the gate driving circuit 120 may be disposed in a bezel region BZ on one side of the display panel 100, and may supply the gate pulse Gout (N) to the gate lines 103 in a single feeding (single feeding) method. In addition, the gate driving circuit 120 may be disposed in the bezel region BZ on opposite sides of the display panel 100 with the pixel array interposed therebetween, and the gate driving circuit 120 may supply the gate pulse Gout (N) to the gate lines 103 according to a dual feeding method.

The gate driving circuit 120 sequentially outputs gate pulses Gout (N) to the gate lines 103 under the control of the timing controller 130. The gate driving circuit 120 may sequentially supply the gate pulse Gout (N) to the gate lines 103 by shifting the gate pulse Gout (N) using a shift register. The signal transmitter in the shift register may be implemented as the above-described circuit. The gate driving circuit 120 may include two or more shift registers, such as a shift register generating a scan pulse, a shift register generating a sensing pulse, a shift register generating an initialization pulse, and a shift register generating a light emission control pulse (or an EM pulse), and each shift register may be implemented as a circuit employed in the above-described embodiment.

The timing controller 130 receives digital video data of an input image and a timing signal synchronized with the digital video data from a host system (not shown). The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, and a data enable signal DE. Since the vertical period and the horizontal period may be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The data enable signal DE has a period of one horizontal period (1H).

The host system may be one of a Television (TV) system, a tablet computer, a notebook computer, a navigation system, a Personal Computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system. The host system may scale the image signal from the video source to match the resolution of the display panel 100 and may transmit the image signal to the timing controller 130 together with the timing signal.

The timing controller 130 may multiply an input frame frequency by i (i is a natural number) in the normal driving mode, so that a frame frequency of x iHz may be input to control the operation timing of the display panel driver. The input frame frequency is 60Hz in the NTSC (national television standards Committee) system and 50Hz in the PAL (phase alternating line) system.

The timing controller 130 reduces a frequency corresponding to a frame rate of writing pixel data to the pixels in the low-speed driving mode compared to the normal driving mode. For example, the data refresh frame rate for writing pixel data to pixels in the normal driving mode may be generated at a refresh rate of 60Hz or higher, for example, any one of 60Hz, 120Hz, and 144Hz, and the data refresh frame DRF in the low-speed driving mode may be generated at a corresponding frequency lower than that of the normal driving mode. The timing controller 130 may reduce the driving frequency of the display panel driver by reducing the frame frequency to a frequency between 1Hz and 30Hz in order to reduce the refresh rate of the pixels in the low-speed driving mode.

The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a control signal for controlling the operation timing of the demultiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driving circuit 120, based on timing signals Vsync, hsync, and DE received from a host system. The timing controller 130 synchronizes the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driving circuit 120 by controlling the operation timing of the display panel driver.

The gate timing control signal generated from the timing controller 130 may be input to the shift register of the gate driving circuit 120 through a level shifter (not shown). The level shifter may receive the gate timing control signal and generate a start pulse and a shift clock and supply them to the shift register of the gate driving circuit 120.

The objects to be achieved, means for achieving the objects, and effects of the present invention described above do not specify essential features of the claims, and therefore, the scope of the claims is not limited by the detailed description of the invention.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not limited thereto, and may be embodied in many different forms without departing from the technical concept of the present invention. Therefore, the embodiments disclosed in the present invention are provided only for illustrative purposes, and are not intended to limit the technical idea of the present invention. The scope of the technical idea of the present invention is not limited thereto. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and do not limit the present invention. The scope of the invention should be construed based on the appended claims, and all technical equivalents thereof should be construed as being included in the scope of the present invention.

Claims

1. A gate drive circuit comprising:

a plurality of signal transmitters receiving a start pulse, a shift clock, a charge/discharge clock, a reverse bias clock, a high potential driving voltage, and a low potential reference voltage, and connected in a cascade structure,

wherein an Nth signal transmitter of the plurality of signal transmitters comprises:

a first control node;

a second control node;

a first controller for controlling charging and discharging of the first control node by using at least one transistor inputted to the reverse bias clock;

a second controller for controlling charging and discharging of the second control node;

a first output buffer for outputting a carry pulse in response to voltages of the first control node and the second control node; and

and a second output buffer for outputting the gate pulse, wherein N is a positive integer.

2. The gate driving circuit of claim 1, wherein the charge/discharge clock comprises:

a first charge/discharge clock input to a 1 st-1 st CLK node;

a second charge/discharge clock generated in reverse phase to the first charge/discharge clock and input to a 2-1CLK node,

wherein the reverse biased clock comprises:

a first reverse bias clock input to the 1 st-2 nd CLK node; and

a second reverse biased clock generated in anti-phase with the first reverse biased clock and input to a 2-2CLK node,

wherein the shift clock is input to a third CLK node,

wherein the first charge/discharge clock and the first reverse bias clock are in-phase clocks,

wherein the second charge/discharge clock and the second reverse-biased clock are in-phase clocks.

3. The gate drive circuit of claim 2, wherein a high voltage of each of the first charge/discharge clock and the second charge/discharge clock is higher than a high voltage of each of the first reverse bias clock and the second reverse bias clock,

wherein a low voltage of each of the first charge/discharge clock and the second charge/discharge clock is higher than a low voltage of each of the first reverse bias clock and the second reverse bias clock,

wherein a high voltage of each of the first charge/discharge clock and the second charge/discharge clock is equal to or higher than a high voltage of the shift clock,

wherein a low voltage of each of the first charge/discharge clock and the second charge/discharge clock is lower than a low voltage of the shift clock.

4. The gate driving circuit according to claim 3, wherein the low voltage of the shift clock is a first low potential reference voltage, the high voltage of the shift clock is a second high potential driving voltage,

wherein a low voltage of each of the first charge/discharge clock and the second charge/discharge clock is a second low potential reference voltage lower than the first low potential reference voltage, a high voltage of each of the first charge/discharge clock and the second charge/discharge clock is the second high potential driving voltage,

wherein a low voltage of each of the first and second reverse bias clocks is a third low potential reference voltage lower than the second low potential reference voltage, and a high voltage of each of the first and second reverse bias clocks is a first high potential driving voltage lower than the second high potential driving voltage.

5. The gate drive circuit of claim 2, wherein the first controller comprises at least a first transistor, a second transistor, and a third transistor,

the first transistor includes a first gate connected to the 2-1CLK node, a second gate connected to the 2-2CLK node, a first electrode connected to a VST node to which the start pulse or an N-1 carry pulse of a previous signal transmitter is input, and a second electrode connected to the first control node,

the second transistor includes a first gate connected to the 1 st-1 CLK node, a second gate connected to the 1 st-2 CLK node, a first electrode connected to the first control node, and a second electrode connected to a third node,

the third transistor includes a first gate connected to the second control node, a second gate connected to a third VSS node to which a third low potential reference voltage is applied, a first electrode connected to the third node, and a second electrode connected to the second VSS node to which a second low potential reference voltage is applied,

wherein the third low potential reference voltage is lower than the second low potential reference voltage.

6. The gate drive circuit of claim 5, wherein the second controller comprises at least a fourth transistor and a fifth transistor that are input to the second reverse bias clock.

7. The gate driving circuit of claim 6, wherein the fourth transistor includes a first gate connected to the 2-1CLK node, a second gate connected to the 2-2CLK node, a first electrode connected to a VDD node to which the high potential driving voltage is applied, and a second electrode connected to the second control node,

wherein the fifth transistor includes a first gate connected to the first control node, a second gate connected to the 2 nd-2 CLK node, a first electrode connected to the 2 nd-1 CLK node, and a second electrode connected to the second control node.

8. The gate drive circuit of claim 7, wherein the first output buffer comprises at least a sixth transistor, a seventh transistor, an eighth transistor, a second capacitor, and a third capacitor,

the sixth transistor includes a first gate connected to the first control node, a second gate connected to a fourth node, a first electrode connected to the 1 st-1 st CLK node, and a second electrode connected to a first output node outputting the carry pulse,

the second capacitor is connected between the fourth node and the first output node,

the seventh transistor includes a first gate connected to the second control node, a second gate connected to the third VSS node, a first electrode connected to the first output node, and a second electrode connected to the second VSS node,

the third capacitor is connected between the second control node and the second VSS node,

the eighth transistor includes a gate connected to the 2-2CLK node, a first electrode connected to the third VSS node, and a second electrode connected to the fourth node.

9. The gate drive circuit of claim 8, wherein the second output buffer comprises at least a ninth transistor, a tenth transistor, and a first capacitor,

the ninth transistor includes a gate connected to the first control node, a first electrode connected to the third CLK node, and a second electrode connected to a second output node that outputs the gate pulse,

the first capacitor is connected between the first control node and the second output node,

the tenth transistor includes a gate connected to the second control node, a first electrode connected to the second output node, and a second electrode connected to a first VSS node to which a first low potential reference voltage is applied,

the first low potential reference voltage is higher than the second low potential reference voltage.

10. The gate drive circuit of claim 1, wherein a high voltage of the charge/discharge clock is different from a high voltage of the reverse bias clock,

wherein a low voltage of the charge/discharge clock is different from a low voltage of the reverse bias clock.

11. The gate drive circuit of claim 1, wherein the second output buffer comprises:

a pull-up transistor charging a second output node outputting the gate pulse in response to a voltage of the first control node; and

a pull-down transistor that discharges the second output node in response to the voltage of the second control node,

wherein each of the pull-up transistor and the pull-down transistor is a three-terminal transistor.

12. The gate drive circuit of claim 1, wherein the first output buffer comprises at least one four-terminal transistor having a second gate to which a constant voltage is applied.

13. A gate drive circuit comprising:

a first control node;

a second control node;

a first controller for controlling charging and discharging of the first control node by using at least one four-terminal transistor inputted to the reverse bias clock;

a second controller for controlling charging and discharging of the second control node by using at least one four-terminal transistor to which the reverse bias clock is input;

14. The gate drive circuit of claim 13, wherein the first output buffer comprises at least one four-terminal transistor having a second gate to which a constant voltage is applied.

15. The gate drive circuit of claim 13, wherein a high voltage of the charge/discharge clock is different from a high voltage of the reverse bias clock,

16. The gate drive circuit of claim 13, wherein the second output buffer comprises:

a pull-up transistor that charges a second output node that outputs the gate pulse in response to a voltage of the first control node; and

a pull-down transistor that discharges the second output node in response to a voltage of the second control node,

17. A display device, comprising:

a display panel including a plurality of data lines to which data voltages are applied, a plurality of gate lines to which gate pulses are applied, a plurality of clock lines, a plurality of power lines, a plurality of pixels, and a gate driving circuit for generating the gate pulses,

the gate driving circuit includes:

a first control node;

a second control node;

a second output buffer for outputting the gate pulse, wherein N is a positive integer.

18. The display device according to claim 17, wherein the charge/discharge clock comprises:

a first charge/discharge clock input to a 1 st-1 st CLK node;

wherein the reverse biased clock comprises:

a first reverse bias clock input to the 1 st-2 nd CLK node; and

a second reverse biased clock generated in reverse phase to the first reverse biased clock and input to a 2-2CLK node,

wherein the shift clock is input to a third CLK node,

wherein the second charge/discharge clock and the second reverse bias clock are in-phase clocks.

19. The display device according to claim 18, wherein a high voltage of each of the first charge/discharge clock and the second charge/discharge clock is higher than a high voltage of each of the first reverse bias clock and the second reverse bias clock,

20. The display device according to claim 18, wherein the low voltage of the shift clock is a first low potential reference voltage, the high voltage of the shift clock is a second high potential driving voltage,

21. The display device according to claim 17, wherein the second controller comprises at least one four-terminal transistor to which the reverse bias clock is input.

22. The display device according to claim 21, wherein the first output buffer comprises at least one four-terminal transistor having a second gate to which a constant voltage is applied.

23. The display device according to claim 17, wherein a circuit layer of the display panel comprises the gate driver circuit,

wherein all transistors disposed in a circuit layer of the display panel are n-channel oxide thin film transistors.

24. The display device according to claim 17, wherein a high voltage of the charge/discharge clock is different from a high voltage of the reverse bias clock,

25. The display device of claim 17, wherein the second output buffer comprises:

26. A display device comprising a gate drive circuit according to any one of claims 1 to 16.