CN115904826A

CN115904826A - ATE-based DSP test method

Info

Publication number: CN115904826A
Application number: CN202110960321.6A
Authority: CN
Inventors: 杨超; 唐金慧; 张金凤; 马成英; 吴迪; 金荣康
Original assignee: Beijing Zhenxing Metrology and Test Institute
Current assignee: Beijing Zhenxing Metrology and Test Institute
Priority date: 2021-08-20
Filing date: 2021-08-20
Publication date: 2023-04-04

Abstract

The invention discloses an ATE-based DSP testing method, belongs to the technical field of electronic component detection, and solves the problem that the existing testing method cannot meet the testing requirement of a high-performance DSP. An ATE-based DSP testing method, the method comprising: writing a DSP configuration program of a test item adapted to a DSP chip to be tested, and downloading the DSP configuration program to a plug-in FLASH of the DSP chip to be tested; the DSP configuration program comprises a test configuration subprogram corresponding to each test item; the ATE is powered on and configured with a DSP chip to be tested based on a DSP configuration program in the plug-in FLASH; sending a GPIO test interaction instruction corresponding to the test item to the DSP chip by ATE; the DSP chip to be tested runs a test configuration subprogram corresponding to the test item based on the received GPIO test interaction instruction, and outputs a test observation signal; and the ATE judges whether the test item passes the test based on the acquired test observation signal. The testing method can meet the testing requirement of the high-performance DSP.

Description

ATE-based DSP test method

Technical Field

The invention relates to the technical field of electronic component detection, in particular to a DSP testing method based on ATE.

Background

DSP, i.e. digital signal processor. DSP has been developed rapidly and widely used from birth to the present; the system has the advantages of high integration level, good stability, strong programmability, high speed, strong embeddable performance, convenient interface and integration, large data processing throughput and high reliability; due to its ultra-high cost performance, multiple functions and stable performance, it has been widely used as a core chip in various aspects such as industrial control and data processing. The diversified market demands further promote the rapid development of the DSP functions towards diversification, high speed, high integration and the like, and form a virtuous circle, so that the DSP is developed vigorously in the aspects of process and functions.

Digital circuit testing, which generally involves applying stimuli to a device directly using ATE test equipment, and observing whether the device response is consistent with expectations; the unprogrammed DSP device has no functional output, and cannot apply excitation to directly observe response through the test bench, so that much inconvenience is brought to the test process; the configuration program must be written in the DSP chip in advance, and the DSP self-starting observation device outputs after being electrified. The testing method has great limitation, and cannot be realized by a DSP without an internal FLASH.

At present, 5000 and 6000 series DSPs are applied in the market, and have rich peripheral interfaces, including IO interfaces, interrupt interfaces, timer interfaces, memory interfaces, bus protocol interfaces, high-speed data transmission interfaces and the like; due to the powerful and complicated functions, most of pins of the DSP have multiple functions, the protocol of the protocol interface is complex, direct communication with the test board is difficult, the speed of the high-speed data transmission interface can reach hundreds of M and even more than 1GHZ, and the test board can not meet the test requirements at all.

Disclosure of Invention

In view of the foregoing analysis, embodiments of the present invention provide an ATE-based DSP testing method, so as to solve the problem that the existing testing method cannot meet the requirement of high-performance DSP testing.

The embodiment of the invention provides a DSP test method based on ATE, which comprises the following steps:

writing a DSP configuration program of a test item adapted to a DSP chip to be tested, and downloading the DSP configuration program to a plug-in FLASH of the DSP chip to be tested; the DSP configuration program comprises a test configuration subprogram corresponding to each test item;

a DSP chip to be tested is configured on the basis of the DSP configuration program in the plug-in FLASH;

sending a GPIO test interaction instruction corresponding to the test item to the DSP chip by ATE;

the DSP chip to be tested runs a test configuration subprogram corresponding to the test item based on the received GPIO test interaction instruction, and outputs a test observation signal;

and the ATE judges whether the test item passes the test or not based on the collected test observation signals.

On the basis of the scheme, the invention also makes the following improvements:

further, the test configuration subprogram is used for responding to the GPIO test interaction instruction, executing data processing and judgment operations matched with the test items, and outputting a test observation signal after verification passes;

all the test configuration subroutines are uniformly placed in a WHILE loop.

Further, the DSP configuration program also comprises GPIO initialization configuration;

the GPIO initialization configuration is used for configuring the input and output states of the GPIO ports according to the test items; the GPIO port configured as the input port is used for receiving the GPIO test interaction instruction, and the GPIO port configured as the output port is used for outputting the test observation signal.

Further, the test items include one or more of: timer test, input high level leakage current test, input low level leakage current test, output high level test and output low level test.

Further, when the test item corresponding to the GPIO test interactive instruction received by the DSP chip to be tested is a timer test:

the DSP chip to be tested runs a test configuration subprogram corresponding to the timer test based on the received GPIO test interaction instruction corresponding to the timer test:

after the timing time is up, the DSP chip to be tested outputs a level switching signal through the GPIO output port to be used as a test observation signal for testing the timer;

if the ATE collects the test observation signals of the promissory timer test within the expected time, the timer test is passed, otherwise, the timer test is not passed.

Further, when the test item corresponding to the GPIO test interaction instruction received by the DSP chip to be tested is an input high-level leakage current test:

the DSP chip to be tested runs a test configuration subprogram corresponding to the input high-level leakage current test based on the received GPIO test interaction instruction corresponding to the input high-level leakage current test:

all GPIO ports in the DSP configuration program are configured as input ports; after appointed time, restoring the GPIO initialization configuration in the DSP configuration program;

in appointed time, the ATE acquires leakage current flowing through each GPIO port as a test observation signal for inputting a high-level leakage current test in a vcc voltage test mode;

and if the drain current which is acquired by the ATE and flows through each GPIO port is smaller than the maximum drain current of the GPIO port, the input high-level drain current test is passed, otherwise, the input high-level drain current test is not passed.

Further, when the test item corresponding to the GPIO test interaction instruction received by the DSP chip to be tested is an input low-level leakage current test:

the DSP chip to be tested operates a test configuration subprogram corresponding to the input low-level leakage current test based on the received GPIO test interactive instruction corresponding to the input low-level leakage current test:

in appointed time, the ATE collects leakage current flowing through each GPIO port in a 0v voltage test mode and uses the leakage current as a test observation signal for inputting a low-level leakage current test;

and if the drain current which is acquired by the ATE and flows through each GPIO port is smaller than the maximum drain current of the GPIO port, the input low-level drain current test is passed, otherwise, the input low-level drain current test is not passed.

Further, when the test item corresponding to the GPIO test interaction instruction received by the DSP chip to be tested is an output high level test:

the DSP chip to be tested operates a test configuration subprogram corresponding to the high level test based on the received GPIO test interactive instruction corresponding to the high level test:

all GPIO ports in the DSP configuration program are configured as output ports; outputting a high level as a test observation signal of an output high level test according to a certain frequency through all GPIO output ports of the DSP chip to be tested;

subsequently, restoring the GPIO initialization configuration in the DSP configuration program;

and if the voltage output by each GPIO port acquired by the ATE is higher than the minimum value of the high level voltage, outputting that the high level test is passed, otherwise, outputting that the high level test is not passed.

Further, when the test item corresponding to the GPIO test interaction instruction received by the DSP chip to be tested is an output low level test:

the DSP chip to be tested operates a test configuration subprogram corresponding to the low-level VOL test based on the received GPIO test interactive instruction corresponding to the low-level test:

all GPIO ports in the DSP configuration program are configured as output ports; outputting a low level as a test observation signal for outputting a low level test according to a certain frequency through all GPIO output ports of the DSP chip to be tested;

then, restoring the GPIO initialization configuration in the DSP configuration program;

and if the voltage output by each GPIO port acquired by the ATE is lower than the highest value of the low-level voltage, outputting that the low-level test is passed, otherwise, outputting that the low-level test is not passed.

Further, the DSP configuration program also comprises kernel initialization configuration and configuration of each module register; wherein, the first and the second end of the pipe are connected with each other,

the kernel initialization configuration is used for initializing the kernel of the DSP chip to be tested;

and the configuration of each module register is used for carrying out initialization configuration of each module register.

Compared with the prior art, the invention can realize at least one of the following beneficial effects:

(1) The method can realize the one-key test of the high-performance DSP;

(2) The testing method can be cut at will, and can realize the full coverage test of DSP resources;

(3) The testing method utilizes GPIO to realize the interaction between ATE and DSP, and the vein is clear;

(4) The testing method makes full use of the programmable function of the DSP, and carries out qualification judgment inside the DSP, thereby greatly reducing the difficulty of testing PATTERN and compiling a testing program;

(5) The test method utilizes the plug-in chip to carry out the test, and greatly reduces the dependence of the test process on ATE test equipment.

In the invention, the technical schemes can be combined with each other to realize more preferable combination schemes. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.

FIG. 1 is a flowchart of an ATE-based DSP testing method in an embodiment of the present invention;

FIG. 2 is a diagram illustrating a connection relationship when downloading a DSP configuration program according to an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating a connection relationship between a DSP chip to be tested and a peripheral device according to an embodiment of the present invention;

FIG. 4 is a flowchart of another ATE-based DSP testing method in accordance with an embodiment of the present invention;

FIG. 5 is a diagram of the hardware connection for the multiplexing memory interface test according to the embodiment of the present invention;

FIG. 6 is a flowchart illustrating the testing of the multiplexing memory interface according to an embodiment of the invention.

Detailed Description

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate preferred embodiments of the invention and together with the description, serve to explain the principles of the invention and not to limit the scope of the invention.

One embodiment of the present invention discloses a method for testing a DSP chip based on ATE, and the flowchart is shown in fig. 1 and fig. 4, and includes the following steps:

step S1: writing a DSP configuration program of a test item adapted to a DSP chip to be tested, and downloading the DSP configuration program to a plug-in FLASH of the DSP chip to be tested; the DSP configuration program comprises a test configuration subprogram corresponding to each test item;

preferably, the test configuration subprogram is configured to respond to the GPIO test interaction instruction, perform data processing and judgment operations matched to the test item, and output a test observation signal after verification passes; and all the test configuration subprograms are uniformly placed in a WHILE loop to wait for the arrival of a test interaction instruction so as to carry out actual test.

Preferably, the DSP configuration program further includes GPIO initialization configuration, which is used to perform power-on configuration on the DSP chip to be tested;

the GPIO initialization configuration is used for configuring the input and output states of GPIO ports in the DSP chip to be tested according to the test items; the GPIO port configured as the input port is used for receiving the GPIO test interaction instruction, and the GPIO port configured as the output port is used for outputting the test observation signal.

For example, the data of the GPIO port configured as the input port can be determined according to the number of the test items in the test items; if 8 test items exist, 3 GPIO ports are set as input ports, if 16 test items exist, 4 GPIO ports are set as input ports, and so on; the design process of the test project should comprehensively consider the performance of the device, and cover all the peripheral and core functions of the chip as much as possible to meet the test requirements.

In addition, the DSP configuration program in this embodiment may further include:

the kernel initialization configuration is used for initializing the kernel of the DSP chip to be tested so as to normally start the DSP chip to be tested;

the configuration of each module register is used for carrying out the initialization configuration of each module register, so that the calling of each subsequent configuration subprogram is facilitated;

in this embodiment, each test item corresponds to an agreed GPIO test interaction command and a test configuration subroutine.

Preferably, in this embodiment, the model of the plug-in FLASH is selected according to the capacity of the DSP configuration program. When the DSP configuration program is downloaded to the plug-in FLASH of the DSP chip to be tested, a schematic connection relationship diagram is shown in fig. 2, and includes:

accessing an upper computer (namely a PC) to a JTAG interface of the DSP chip to be detected, and accessing the plug-in FLASH to a FLASH interface of the DSP chip to be detected;

and the upper computer compiles the DSP configuration program, downloads the compiled DSP configuration program and a secondary bootstrap program into an internal RAM of the DSP chip to be tested, and runs the secondary bootstrap program, wherein the DSP configuration program in the internal RAM is downloaded into the plug-in FLASH through the FLASH interface.

In the process, an external power supply can be used for supplying power, and the external power supply adjusts the voltage through the power management chip and respectively supplies power to the DSP chip to be tested and the plug-in FLASH. After the power is on, the PC machine is connected with the DSP chip to be tested through the JTAG interface, the compiled configuration program is downloaded into the internal RAM of the DSP, the secondary bootstrap program is operated at the moment, and the DSP configuration program of the internal RAM is downloaded into the FLASH through the FLASH interface. In the test process, the DSP chip to be tested and the plug-in FLASH are powered by ATE equipment, and after the test is powered on, as long as the communication between the DSP chip to be tested and the plug-in FLASH is normal, the DSP chip to be tested can automatically load a DSP configuration program from the plug-in FLASH without additional control.

Prior to performing the power-up configuration, the ATE performs the following operations:

the ATE controls all pins of the DSP chip to be tested to be connected to the ATE, the DSP chip to be tested is subjected to connection test, and the electrifying configuration is carried out after the connection test is passed;

preferably, the connection testing process can be realized by adopting a flow pressure measuring mode.

Step S2: carrying out power-on configuration on the DSP chip to be tested based on the DSP configuration program in the plug-in FLASH;

and the plug-in FLASH is connected to a FLASH interface of the DSP chip to be tested to supply power to the DSP chip to be tested, and the DSP chip to be tested is powered on and automatically started. The DSP completes power-on configuration according to the DSP configuration program, meanwhile completes read-write testing of the internal registers based on the configuration of each module register in the DSP configuration program, and the DSP can be in a cycle after completing the power-on configuration until receiving a GPIO (general purpose input/output) test interaction instruction sent by the ATE, and the DSP starts to execute subsequent testing.

After power-on configuration, if the to-be-tested DSP chip is normally started and operated, the FLASH interface in the to-be-tested DSP chip is normal, and meanwhile, the ATE executes the test of the test item; otherwise, the ATE stops performing the test of the test item.

Preferably, the present embodiment provides two sets of power systems for the test interface board, which are respectively an ATE power supply and an external power supply, as shown in fig. 3 below. The external power supply is an interface, all chips including the DSP chip to be tested are powered through the power management chip and are used for online debugging of the DSP and debugging of communication among modules (mainly used during debugging before ATE, ATE supplies power to all devices in the testing process, and the external power supply interface is disconnected); the ATE power supply is used for actual test, and external matched chips such as a memory, an FPGA and a bus protocol chip are respectively powered by different power ports of the ATE, so that accurate test and flexible control of power consumption of each chip in a test process can be realized.

The schematic diagram of the connection relationship between the DSP chip to be tested and the peripheral is shown in fig. 3: the intelligent power supply comprises main peripheral equipment and a connection mode of two sets of power supplies, wherein black arrowhead-free oblique lines indicate that the connection relation can be switched through a relay. In the testing process, the ATE testing equipment provides a power supply for the DSP chip, and the DSP chip can be normally started. And the pin of the DSP chip is connected to the ATE digital channel or the external equipment by using the function of selecting one of the relays, and the relay control power supply and the control signal are provided by the ATE test board. And switching the relay control signals when the test is started, so that all pins of the DSP are connected to the ATE for connection test, and the chips are guaranteed to be connected perfectly. The relay control signals are grouped and switched, so that the memory interface of the DSP is connected to the plug-in FLASH, power is supplied to the DSP at the moment, and the DSP realizes power-on self-starting. And the DSP completes power-on configuration according to the configuration program and simultaneously completes read-write test of the internal register, and the DSP can wait in a cycle after completing the power-on configuration until receiving a test instruction sent by the ATE through the GPIO, and the DSP starts to execute subsequent test.

And step S3: sending a GPIO test interaction instruction corresponding to the test item to the DSP chip by ATE;

and step S4: the DSP chip to be tested runs a test configuration subprogram corresponding to the test item based on the received GPIO test interaction instruction, and outputs a test observation signal;

step S5: and the ATE judges whether the test item passes the test or not based on the collected test observation signals.

The process of step S4 and step S5 differs for a specific test item, and, in particular,

when the test item corresponding to the GPIO test interaction instruction received by the DSP chip to be tested is a peripheral related test item, the step S4 executes the following operations:

the DSP chip to be tested runs a test configuration subprogram corresponding to the peripheral related test item based on the received GPIO test interaction instruction corresponding to the peripheral related test item:

the DSP chip to be tested writes specific data into the peripheral through the pins related to the corresponding test items, reads the data in the peripheral through the pins related to the corresponding test items, judges whether the read data is consistent with the written specific data or not, and if so, the DSP chip to be tested outputs the level with the variable height of the fixed frequency through the GPIO output port to be used as a test observation signal of the peripheral related test items;

at this time, step S5 performs the following operations:

if the ATE collects the test observation signals of the appointed peripheral related test items in the expected time, the test of the peripheral related test items passes, otherwise, the test of the peripheral related test items does not pass.

Preferably, the peripheral related class test items include one or more of: the test method comprises the following steps of memory interface test, bus protocol interface test and high-speed data transmission interface test. The peripheral used for completing the memory interface test by matching with the DSP chip to be tested is a plug-in memory matched with a memory interface; the peripheral used for matching the DSP chip to be tested to finish the bus protocol interface test is a plug-in protocol chip matched with a bus protocol interface or an FPGA loaded with an IP core; the peripheral used for matching the DSP chip to be tested to finish the high-speed data transmission interface test is a plug-in data transmission chip matched with the high-speed data transmission interface.

In order to better understand the technical solution of the present application, the present embodiment further introduces each peripheral related class test item in more detail, as follows:

(1) Memory interface testing

The DSP memory interface can be generally externally connected with one or more memories such as SRAM, FLASH, SDRAM, ZBTRAM and the like; the FLASH interface is used for power-on self-starting, which has been discussed above, and if the DSP can be started and operated normally, the subsequent test item passes normally, which indicates that the FLASH interface is intact, and no separate test is required. Therefore, the memory interface test in this embodiment does not include the test of the FLASH interface. And when testing other memory interfaces of the DSP, data reading, writing and transmission are required to be carried out on the external memory through the DSP, so that the memory interfaces are ensured to be intact.

For DSP chips, some memory interfaces are special, and only one type of memory can be connected with the memory interfaces; some memory interfaces are multiplexed, (ZBTRAM and SDRAM memory interfaces are typically multiplexed, with specific hardware connections as shown in fig. 5 below), which may be connected to several different memories. For the special interface, selecting a memory with proper type and capacity on hardware to be connected with a corresponding DSP interface, and performing writing-reading-erasing operations on the memory through a DSP configuration subprogram program, wherein the read data is the same as the written data, so that the corresponding DSP memory interface can be proved to work normally; for a multiplexing memory interface, different types of memories are simultaneously connected to a memory interface corresponding to a DSP, and the difference is that the enable signals (generally controlled by a given GPIO) of the memories are directly sent by the DSP, and the other enable signals are controlled by the DSP through an inverter, so that the two memories can occupy the same DSP resource but can be subjected to time division multiplexing. The multiplexed memory interface test hardware connection diagram is shown in fig. 5.

The test of each memory interface corresponds to a GPIO instruction, when the DSP receives a specific memory test instruction sent by ATE, the memory test is started (at the moment, the DSP is electrified and self-starting is completed), ATE test equipment controls a relay to switch, the memory is connected with DSP data and a control pin, after the DSP receives the instruction, the memory test is executed, specific data are written into the whole memory, then reading is carried out, whether the read data are consistent with the written data or not is judged, the memory needing to be erased carries out erasing operation, whether the read data are empty or not is judged correctly, the DSP sends a level with certain frequency and high-low variation through a specific GPIO output port, the ATE test equipment acquires the level with expected high-low variation at expected time, the DSP memory interface passes the test, otherwise, the test does not pass.

The specific flow of the testing of the multiplexing memory interface is shown in fig. 6.

(2) Bus protocol interface testing

The high-performance DSP has rich bus protocol interfaces, which generally comprise an IIC protocol interface, a CAN bus protocol interface, a UART bus protocol interface, an HPI bus protocol interface, a PCI bus protocol interface and the like. Typically, testing these bus interface chips requires the ATE to emulate the communication protocol of the particular bus interface, such that the protocol chips communicate data with the ATE. This approach not only requires the engineering developer to have a detailed understanding of the bus protocol, but also to program a large number of test paterns to apply stimuli conforming to the communication protocol using ATE and to make high and low level decisions on the output of each cycle; for the response bit field, because of the inconsistency of the interface chip, a large amount of redundant operations need to be added, and the misjudgment of the chip is avoided; for a high-performance DSP with a rich protocol interface chip, the testing method can be realized, but has ultrahigh requirements on engineering technical developers, needs a large amount of debugging and tests, and can ensure the stability and the effectiveness of the test by repeatedly adjusting the test PATTERN; the test method has huge workload on the whole, and the test passing rate is not high because the ATE does not have a specific communication protocol.

The embodiment provides a method for testing a plug-in specific protocol chip, which comprises the following steps: and the DSP chip is connected with the DSP chip by using a specific protocol, and the DSP pin is switched between the plug-in equipment and the ATE by using the relay. The IIC protocol interface is tested, and the memory with the IIC protocol is connected with the DSP; testing a CAN bus protocol interface, and connecting the CAN bus protocol interface of the DSP with a CAN bus controller SJA 1000T; testing a UART bus protocol interface, and connecting the UART bus protocol interface with a UART protocol interface of the DSP by using a UART bus transceiver; in order to reduce the complexity of the test interface board, a proper FPGA and a configuration memory can be selected, different IP cores are loaded through the FPGA, time division multiplexing is carried out on the FPGA, so that the FPGA simulates different bus protocol chips at different moments, and the bus protocol interface test is completed by matching with the DSP.

Taking IIC protocol interface test as an example, an IIC test subprogram is pre-programmed by a configuration program and placed in a WHILE loop, when an IIC interface test instruction received by a GPIO interface is received, IIC test is started to be executed, at the moment, an IIC protocol interface of a DSP is connected to an IIC protocol memory by a relay control interface, the IIC test subprogram starts to write data into the memory through the IIC interface of the DSP, then the data is read out, whether the written data is consistent with the read data is judged, and whether the IIC protocol interface of the DSP is intact is judged.

(3) High speed data transfer interface testing

The high-performance DSP is widely applied, part of the DSPs are provided with high-speed data transmission interfaces, and the high-speed data transmission interfaces can transmit high-speed signals of hundreds of MHZ and even a few GHZ, so that the testing requirements of the high-speed data transmission interfaces of the DSPs are difficult to meet for general ATE testing equipment. The test method of the embodiment: the method comprises the steps of externally connecting a high-speed data transmission chip, writing a DSP and an external chip transmission control subprogram in a DSP configuration program, executing high-speed data transmission through GPIO instructions sent by ATE test equipment, reading back transmitted data, comparing whether the read-back data is consistent with the transmitted data inside the DSP, sending high and low levels with fixed frequency change through GPIO output ports after comparison is passed, and collecting the levels by ATE to judge the performance of a high-speed transmission interface.

And for the peripheral irrelevant test items, the ATE directly executes the test of the corresponding test items based on the DSP configuration program. Specifically, the peripheral independent class test items include the following test items:

(1) I/O functional testing

When the test item corresponding to the GPIO test interactive instruction received by the DSP chip to be tested is an I/O function test, the step S4 executes the following operations:

the DSP chip to be tested runs a test configuration subprogram corresponding to the I/O function test based on the received GPIO test interactive instruction corresponding to the I/O function test:

all GPIO ports in the DSP configuration program are configured as output ports; outputting continuously changing high and low levels as test observation signals of the I/O function test through all GPIO output ports of the DSP chip to be tested according to a certain frequency;

at this time, step S5 performs the following operations:

if the ATE collects test observation signals of the appointed I/O function test in the expected time, the I/O function test is passed, otherwise, the I/O function test is not passed.

(2) Timer testing

When the test item corresponding to the GPIO test interactive instruction received by the DSP chip to be tested is a timer test, the step S4 executes the following operations:

the DSP chip to be tested runs a test configuration subprogram corresponding to the timer test based on the received GPIO test interactive instruction corresponding to the timer test:

if the ATE collects the test observation signals of the appointed timer test in the expected time, the timer test is passed, otherwise, the timer test is not passed.

(3) Data processing module testing

The DSP has a powerful data processing capability, and when a certain algorithm is processed by the DSP, one or more data processing modules, such as a mathematical operation module, etc., inside the DSP associated with the operation of the algorithm are called at the same time. Therefore, when the data processing module is tested, a data processing algorithm, such as a data processing algorithm commonly used in engineering, such as a Fourier transform algorithm, an image processing algorithm and the like, can be directly written in a test configuration subprogram corresponding to the test of the data processing module.

When the test item corresponding to the GPIO test interactive instruction received by the DSP chip to be tested is a data processing module test, the step S4 executes the following operations:

the DSP chip to be tested runs a test configuration subprogram corresponding to the test of the data processing module based on the received GPIO test interactive instruction corresponding to the test of the data processing module:

the DSP runs a data processing algorithm in a test configuration subprogram corresponding to the test of the data processing module and judges a data processing result in the DSP, and if the data processing result is consistent with an expected result, the DSP chip to be tested outputs a high-low level with fixed frequency change as a test observation signal of the test of the data processing module through the GPIO output port;

at this time, step S5 performs the following operations:

and if the ATE acquires the test observation signal tested by the appointed data processing module in the expected time, the data processing module passes the test, otherwise, the data processing module fails the test.

Preferably, in order to perform a relatively comprehensive test on the data processing module, the algorithm in the test configuration subprogram corresponding to the test item can call multiple types of data processing modules; alternatively, multiple algorithms are written, each invoking one or more types of data processing modules.

(4) Parameter testing

Preferably, the parametric test may comprise:

inputting a high-level leakage current IIH test, inputting a low-level leakage current IIL test, outputting a high-level VOH test and outputting a low-level VOL test;

it should be noted that, the parameter testing process needs to be combined with the setting of the DSP configuration program.

1) Input high level leakage current IIH test

When the test item corresponding to the GPIO test interaction instruction received by the DSP chip to be tested is an input high-level leakage current test, step S4 performs the following operations:

at this time, step S5 performs the following operations:

2) Input low level leakage current IIL test

When the test item corresponding to the GPIO test interaction instruction received by the DSP chip to be tested is an input low-level leakage current test, step S4 performs the following operations:

at this time, step S5 performs the following operations:

3) Output high level VOH test

When the test item corresponding to the GPIO test interaction instruction received by the DSP chip to be tested is an output high level test, step S4 performs the following operations:

all GPIO ports in the DSP configuration program are configured as output ports; outputting a high level as a test observation signal for outputting a high level test according to a certain frequency through all GPIO output ports of the DSP chip to be tested;

at this time, step S5 performs the following operations:

and if the voltage output by each GPIO port acquired by the ATE is higher than the minimum value of the high level voltage, outputting that the high level test passes, otherwise, outputting that the high level test does not pass.

4) Output low level VOL test

When the test item corresponding to the GPIO test interaction instruction received by the DSP chip to be tested is an output low level test, step S4 performs the following operations:

at this time, step S5 performs the following operations:

The DSP configuration program is arranged in the plug-in FLASH, the power-on self-starting is realized in the testing process, the problem that the internal FLASH memory DSP is not used for testing is solved, the complicated operations of programming, testing and erasing are avoided, and the one-key testing can be realized.

The GPIO port is used for realizing communication between ATE test equipment and the DSP, complex functions of the DSP are differentiated, only single function test is carried out at the same time, the test process is simplified, and the test difficulty is reduced.

The external interface of the DSP is inspected by using the plug-in protocol chip and the FPGA, all excitations are sent by the DSP and are judged in the DSP, so that the functions of the DSP are fully inspected, and the complicated test PATTERN writing is avoided.

In the whole test process, ATE test equipment only needs to provide a power supply and GPIO (general purpose input/output) interaction signals and judge whether the GPIO outputs high and low levels with fixed frequency at expected time to finish the test, so that the difficulty in programming the test PATTERN is greatly reduced.

The relays are used for switching in groups, so that the DSP pins are ensured to be continuously switched between the peripheral and the ATE in the testing process, and the functional test and the parameter test are conveniently switched.

This patent utilizes external high-speed communication chip, realizes the test to DSP high-speed data transmission interface, has reduced the dependence of test process to ATE high-speed signal for the test of high performance DSP can be accomplished to the most basic testboard.

Those skilled in the art will appreciate that all or part of the flow of the method implementing the above embodiments may be implemented by a computer program, which is stored in a computer readable storage medium, to instruct related hardware. The computer readable storage medium is a magnetic disk, an optical disk, a read-only memory or a random access memory, etc.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.

Claims

1. An ATE-based DSP testing method, the method comprising:

2. The ATE-based DSP testing method of claim 1,

the test configuration subprogram is used for responding to the GPIO test interactive instruction, executing data processing and judgment operation matched with the test item, and outputting a test observation signal after verification is passed;

all the test configuration subroutines are uniformly placed in a WHILE loop.

3. The ATE-based DSP testing method of claim 2,

the DSP configuration program also comprises GPIO initialization configuration;

4. The ATE-based DSP testing method of claim 3, wherein,

the test items include one or more of: the method comprises the following steps of timer testing, input high-level leakage current testing, input low-level leakage current testing, output high-level testing and output low-level testing.

5. The ATE-based DSP testing method of claim 4, wherein,

when the test item corresponding to the GPIO test interactive instruction received by the DSP chip to be tested is a timer test:

6. The multi-functional test method of DSP chip of claim 4,

when the test item corresponding to the GPIO test interaction instruction received by the DSP chip to be tested is an input high-level leakage current test:

the DSP chip to be tested operates a test configuration subprogram corresponding to the input high-level leakage current test based on the received GPIO test interactive instruction corresponding to the input high-level leakage current test:

all GPIO ports in the DSP configuration program are configured as input ports;

after appointed time, restoring the GPIO initialization configuration in the DSP configuration program;

7. The multifunctional testing method of DSP chip according to claim 4,

when the test item corresponding to the GPIO test interactive instruction received by the DSP chip to be tested is an input low-level leakage current test:

all GPIO ports in the DSP configuration program are configured as input ports;

in a scheduled time, the ATE collects leakage current flowing through each GPIO port in a 0v voltage test mode and takes the leakage current as a test observation signal for inputting a low-level leakage current test;

8. The multifunctional testing method of DSP chip according to claim 4,

when the test item corresponding to the GPIO test interactive instruction received by the DSP chip to be tested is an output high level test:

all GPIO ports in the DSP configuration program are configured as output ports;

outputting a high level as a test observation signal of an output high level test according to a certain frequency through all GPIO output ports of the DSP chip to be tested;

9. The multi-functional test method of DSP chip of claim 4,

when the test item corresponding to the GPIO test interactive instruction received by the DSP chip to be tested is an output low level test:

all GPIO ports in the DSP configuration program are configured as output ports;

outputting a low level as a test observation signal for outputting a low level test according to a certain frequency through all GPIO output ports of the DSP chip to be tested;

and if the voltage output by each GPIO port acquired by the ATE is lower than the highest value of the low level voltage, outputting that the low level test is passed, otherwise, outputting that the low level test is not passed.

10. The ATE-based DSP test method defined in any one of claims 1-9, wherein the DSP configuration program further comprises a kernel initialization configuration and a configuration of module registers; wherein, the first and the second end of the pipe are connected with each other,

and the configuration of each module register is used for carrying out initialization configuration on each module register.