CN115904309A

CN115904309A - Adder, analog-to-digital converter and semiconductor chip

Info

Publication number: CN115904309A
Application number: CN202211718556.5A
Authority: CN
Inventors: 陈俊宇
Original assignee: Shanghai Southchip Semiconductor Technology Co Ltd
Current assignee: Shanghai Southchip Semiconductor Technology Co Ltd
Priority date: 2022-12-29
Filing date: 2022-12-29
Publication date: 2023-04-04

Abstract

The embodiment of the application provides an adder, an analog-to-digital converter and a semiconductor chip. The adder includes: a first differential circuit and a second differential circuit; the first end and the second end of the first differential circuit are respectively and electrically connected with a positive input voltage signal and a negative input voltage signal, the third end and the fourth end of the first differential circuit are respectively and electrically connected with a positive voltage signal output end and a negative voltage signal output end of the adder, the fifth end of the first differential circuit is electrically connected with a power supply positive voltage, the first end of the second differential circuit is electrically connected with a reference voltage signal, the second end of the second differential circuit is electrically connected with the third end of the first differential circuit, the third end of the second differential circuit is electrically connected with the fourth end of the first differential circuit, and the sixth end of the first differential circuit and the fourth end of the second differential circuit are both grounded. The adder can add the jitter signal and the input differential signal, thereby realizing the function of adding the jitter signal.

Description

Adder, analog-to-digital converter and semiconductor chip

Technical Field

The embodiment of the application relates to the technical field of integrated circuits, in particular to an adder, an analog-to-digital converter and a semiconductor chip.

Background

The Sigma-delta analog-to-digital converter is a device capable of converting an analog signal into a digital signal, and a quantization error is generated in the working process of the Sigma-delta analog-to-digital converter. The Sigma-delta analog-to-digital converter can generate a plurality of intermediate signals in the working process, and can reduce quantization errors generated in the working process of the Sigma-delta analog-to-digital converter and improve the precision of the Sigma-delta analog-to-digital converter by adding a jitter signal to at least one of the intermediate signals and processing the intermediate signal added with the jitter signal. Also in other types of semiconductor devices, a dither signal may be added to at least one of the intermediate signals to improve the accuracy of the device.

Thus, it is desirable to provide a specific technical solution to implement the function of adding the jitter signal.

Disclosure of Invention

In view of the above problems, embodiments of the present application provide an adder, an analog-to-digital converter, and a semiconductor chip, which can superimpose a dither signal and an input differential signal, thereby enabling a function of adding the dither signal.

In a first aspect, an embodiment of the present application provides an adder, including: a first differential circuit and a second differential circuit;

a first end of the first differential circuit is electrically connected with a positive input voltage signal, a second end of the first differential circuit is electrically connected with a negative input voltage signal, a third end of the first differential circuit is electrically connected with a positive voltage signal output end of the adder, fourth ends of the first differential circuit are respectively electrically connected with a negative voltage signal output end of the adder, a fifth end of the first differential circuit is electrically connected with a power supply positive voltage, a first end of the second differential circuit is electrically connected with a reference voltage signal, a second end of the second differential circuit is electrically connected with the third end of the first differential circuit, the third end of the second differential circuit is electrically connected with the fourth end of the first differential circuit, and the sixth end of the first differential circuit and the fourth end of the second differential circuit are both grounded; wherein the positive input voltage signal and the negative input voltage signal constitute an input differential signal;

and the adder is used for superposing the reference voltage signal and the input differential signal to obtain an output differential signal and outputting the output differential signal.

In some embodiments, the first differential circuit comprises a first switching component, a first capacitance, a second switching component, and a second capacitance;

the first end of the first switch assembly is electrically connected to the positive input voltage signal, the second end of the first switch assembly is electrically connected to the lower plate of the first capacitor, the upper plate of the first capacitor is electrically connected to the positive voltage signal output end and the third end of the first switch assembly, the fourth end of the first switch assembly is electrically connected to the positive voltage of the power supply, and the fifth end of the first switch assembly is grounded;

the first end of the second switch assembly is electrically connected with the negative input voltage signal, the second end of the second switch assembly is electrically connected with the lower pole plate of the second capacitor, the upper pole plate of the second capacitor is electrically connected with the negative voltage signal output end and the third end of the second switch assembly, the fourth end of the second switch assembly is electrically connected with the positive voltage of the power supply, and the fifth end of the second switch assembly is grounded.

In some embodiments, the first switch assembly comprises a first switch, a second switch, and a third switch;

the first end of the first switch is electrically connected with the positive input voltage signal, the second end of the first switch is electrically connected with the lower pole plate of the first capacitor and the first end of the second switch, the upper pole plate of the first capacitor is electrically connected with the first end of the third switch and the positive voltage signal output end, the second end of the second switch is grounded, and the second end of the third switch is electrically connected with the power supply positive voltage;

the second switch assembly comprises a fourth switch, a fifth switch and a sixth switch;

the first end electricity of fourth switch is connected the negative input voltage signal, the second end electricity of fourth switch connect with the second electric capacity the bottom plate with the first end of fifth switch, the top plate electricity of second electric capacity the first end of sixth switch with negative voltage signal output end, the second end ground connection of fifth switch, the second end electricity of sixth switch is connected the power positive voltage.

In some embodiments, the second differential circuit comprises a third switching component, a third capacitance, a fourth switching component, and a fourth capacitance;

the first end of the third switch component and the first end of the fourth switch component are electrically connected with the reference voltage signal, the second end of the third switch component is electrically connected with the lower pole plate of the third capacitor, the upper pole plate of the third capacitor is electrically connected with the positive voltage signal output end, the second end of the fourth switch component is electrically connected with the lower pole plate of the fourth capacitor, the upper pole plate of the fourth capacitor is electrically connected with the negative voltage signal output end, and the third end of the third switch component and the third end of the fourth switch component are all grounded.

In some embodiments, the third switch assembly comprises a seventh switch and an eighth switch;

a first end of the seventh switch is electrically connected to the reference voltage signal, a second end of the seventh switch is electrically connected to the lower plate of the third capacitor and the first end of the eighth switch, and a second end of the eighth switch is grounded;

the fourth switch assembly comprises a ninth switch and a tenth switch;

the first end of the ninth switch is electrically connected to the reference voltage signal, the second end of the ninth switch is electrically connected to the lower plate of the fourth capacitor and the first end of the tenth switch, and the second end of the tenth switch is grounded.

In some embodiments, the first switch assembly is configured to conduct the positive input voltage signal and the lower plate of the first capacitor, and conduct the upper plate of the first capacitor and the positive power supply voltage in a first state; in a second state, disconnecting the positive input voltage signal from the lower plate of the first capacitor, disconnecting the upper plate of the first capacitor from the positive power supply voltage, and connecting the lower plate of the first capacitor to ground;

the second switch component is used for conducting the negative input voltage signal and the lower plate of the second capacitor in the first state, and conducting the upper plate of the second capacitor and the positive power supply voltage; and in the second state, the connection between the negative input voltage signal and the lower plate of the second capacitor is disconnected, the connection between the upper plate of the second capacitor and the positive power supply voltage is disconnected, and the lower plate of the second capacitor and the ground are connected.

In some embodiments, the connection between the positive input voltage signal and the lower plate of the first capacitor is broken at a time later than the connection between the upper plate of the first capacitor and the positive supply voltage during the switching from the first state to the second state.

In some embodiments, the third switch component is configured to turn on the reference voltage signal and the lower plate of the third capacitor in the first state; disconnecting the reference voltage signal from the lower plate of the third capacitor and connecting the lower plate of the third capacitor with the ground in the second state;

the fourth switch component is used for conducting the lower plate of the fourth capacitor and the ground in the first state; and maintaining the lower plate of the fourth capacitor to be conducted with the ground in the second state.

In some embodiments, during the switching from the first state to the second state, the connection between the upper plate of the first capacitor and the positive supply voltage is broken at a time later than the connection between the reference voltage signal and the lower plate of the third capacitor.

In some embodiments, the adder further comprises a third differential circuit;

the first end of the third differential circuit is electrically connected with the reference voltage signal, the second end of the third differential circuit is electrically connected with the third end of the first differential circuit, the third end of the third differential circuit is electrically connected with the fourth end of the first differential circuit, and the fourth ends of the third differential circuit are all grounded.

In a second aspect, an embodiment of the present application provides an analog-to-digital converter, including: any one of the adders provided in the first aspect.

In a third aspect, an embodiment of the present application provides a semiconductor chip, including: any one of the adders provided in the first aspect.

In the technical solution of the embodiment of the present application, the adder includes a first differential circuit and a second differential circuit, a first end of the first differential circuit is electrically connected to a positive input voltage signal, a second end of the first differential circuit is electrically connected to a negative input voltage signal, a third end of the first differential circuit is electrically connected to a positive voltage signal output end of the adder, a fourth end of the first differential circuit is electrically connected to a negative voltage signal output end of the adder, a fifth end of the first differential circuit is electrically connected to a positive voltage of a power supply, a first end of the second differential circuit is electrically connected to a reference voltage signal, a second end of the second differential circuit is electrically connected to a third end of the first differential circuit, a third end of the second differential circuit is electrically connected to a fourth end of the first differential circuit, a sixth end of the first differential circuit and a fourth end of the second differential circuit are both grounded, wherein the positive input voltage signal and the negative input voltage signal constitute an input differential signal; the reference voltage signal and the input differential signal can be superposed through the adder to obtain the output differential signal and output the output differential signal, so that the reference voltage signal after attenuation is used as a jitter signal, the jitter signal and the input differential signal can be superposed, and the function of adding the jitter signal can be realized.

The foregoing description is only an overview of the technical solutions of the embodiments of the present application, and the embodiments of the present application can be implemented according to the content of the description in order to make the technical means of the embodiments of the present application more clearly understood, and the detailed description of the present application is provided below in order to make the foregoing and other objects, features, and advantages of the embodiments of the present application more clearly understandable.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of an adder according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of another adder provided in the embodiment of the present application;

FIG. 4 is an equivalent circuit diagram of the adder shown in FIG. 3 in a first state;

FIG. 5 is an equivalent circuit diagram of the adder shown in FIG. 3 in a second state;

fig. 6 is an overall timing diagram of an analog-to-digital converter according to an embodiment of the present application;

FIG. 7 is a timing diagram of a jitter signal adding phase according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of another adder according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of another adder according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the description and claims of this application and the description of the figures are intended to cover non-exclusive inclusions.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

Furthermore, the terms "first," "second," and the like in the description and claims of the present application or in the above-described drawings are used for distinguishing between different objects and not necessarily for describing a particular sequential order, and may explicitly or implicitly include one or more of the features.

In the description of the present application, unless otherwise expressly specified or limited, the terms "connected" or "connecting" are to be construed broadly, e.g., "connected" or "connected" of a circuit arrangement may mean, in addition to physical connection, electrical connection or signal connection, e.g., direct connection, i.e., physical connection, indirect connection via at least one intervening element, as long as electrical continuity is achieved, or communication between two elements; signal connection may refer to signal connection through a medium, such as radio waves, in addition to signal connection through circuitry.

The term "and/or" herein is merely an association relationship describing an associated object, and means that there may be three relationships, for example, a and/or B, which may mean: there are three cases of A, A and B, and B. In addition, the character "/" herein generally indicates that the former and latter associated objects are in an "or" relationship.

In the description of the present application, unless otherwise specified, "a plurality" and "at least two" mean two or more (including two), and similarly, "a plurality of groups" and "at least two groups" mean two or more (including two).

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present disclosure, as shown in fig. 1, the analog-to-digital converter 100 includes an adder 10, a feedback adder 20, an integrator 30, and a comparator 40, where a first input terminal of the feedback adder 20 is electrically connected to an input signal Signalin of the analog-to-digital converter 100, a second input terminal of the feedback adder 20 is electrically connected to an output terminal of the comparator 40, an output terminal of the feedback adder 20 is electrically connected to an input terminal of the integrator 30, an output terminal of the integrator 30 is electrically connected to a first input terminal of the adder 10, a second input terminal of the adder 10 is electrically connected to a dither signal Vdith, an output terminal of the adder 10 is electrically connected to an input terminal of the comparator 40, and an output terminal of the comparator 40 is electrically connected to an output terminal of the analog-to-digital converter 100.

The feedback adder 20 adds the input signal Signalin and the inverted signal-Dout of the output signal Dout of the comparator 40, that is, subtracts the input signal Signalin and the output signal Dout of the comparator 40 to obtain a superimposed signal Signalin-Dout, and outputs the superimposed signal Signalin-Dou to the integrator 30. The integrator 30 may perform z-domain integration on the superimposed signal Signalin-Dout to obtain an integrated signal Vsig. The adder 10 may add the integration signal Vsig and the dither signal Vdith to obtain a superimposed signal Vsig + Vdith, and send the superimposed signal Vsig + Vdith to the comparator 40. The comparator 40 can generate a digital code stream, i.e., an output signal Dout, based on the superimposed signal Vsig + Vdith. In this manner, by adding the adder 10 between the comparator 40 and the integrator 30, the dither signal Vdith can be superimposed with the integrated signal Vsig based on the adder 10, so that the comparator 40 performs the comparison operation based on the superimposed signal Vsig + Vdith, and thus, the function of adding the dither signal can be integrated in the analog-to-digital converter.

Similarly, in other types of semiconductor devices, when a dither signal needs to be added to a signal input to a comparator, an adder 10 may be connected in series to the input terminal of the comparator, and the function of adding the dither signal may be integrated into the semiconductor device.

The adder 10 provided in the embodiments of the present application is described in detail below with several specific embodiments.

Fig. 2 is a schematic structural diagram of an adder according to an embodiment of the present application, and as shown in fig. 2, the adder 10 includes: a first differential circuit 110 and a second differential circuit 120.

The first end of the first differential circuit 110 is electrically connected to the positive input voltage signal VIP, the second end of the first differential circuit 110 is electrically connected to the negative input voltage signal VIN, the third end of the first differential circuit 110 is electrically connected to the positive voltage signal output end of the adder 10, the fourth end of the first differential circuit 110 is electrically connected to the negative voltage signal output end of the adder 10, the fifth end of the first differential circuit 110 is electrically connected to the positive power voltage VDD, the first end of the second differential circuit 120 is electrically connected to the reference voltage signal VREF, the second end of the second differential circuit 120 is electrically connected to the third end of the first differential circuit 110, the third end of the second differential circuit 120 is electrically connected to the fourth end of the first differential circuit 110, and the sixth end of the first differential circuit 110 and the fourth end of the second differential circuit 120 are both grounded. The positive input voltage signal VIP and the negative input voltage signal VIN form an input differential signal VIP-VIN.

And the adder 10 is used for superposing the reference voltage signal VREF and the input differential signal VIP-VIN to obtain and output the output differential signal VOP-VON.

Illustratively, as shown in fig. 2, the third terminal of the first differential circuit 110 is electrically connected to the positive voltage signal output terminal of the adder 10, and the fourth terminal of the first differential circuit 110 is electrically connected to the negative voltage signal output terminal of the adder 10, where the positive voltage signal output terminal is used to output a positive voltage output signal VOP, the negative voltage signal output terminal is used to output a negative voltage output signal VON, then the third terminal of the first differential circuit 110 is electrically connected to the positive voltage output signal VOP, and the fourth terminal of the first differential circuit 110 is electrically connected to the negative voltage output signal VON. The positive voltage output signal VOP is further electrically connected to the second terminal of the second differential circuit 120, and the negative voltage output signal VON is further electrically connected to the third terminal of the second differential circuit 120, such that the positive voltage output signal VOP is equal to the sum of the voltage at the second terminal of the second differential circuit 120 and the voltage at the third terminal of the first differential circuit 110, and the negative voltage output signal VON is equal to the sum of the voltage at the third terminal of the second differential circuit 120 and the voltage at the fourth terminal of the first differential circuit 110.

The first terminal of the first differential circuit 110 is electrically connected to the positive input voltage signal VIP, the second terminal of the first differential circuit 110 is electrically connected to the negative input voltage signal VIN, the positive input voltage signal VIP and the negative input voltage signal VIN form an input differential signal, that is, the input differential signal is VIP-VIN, and the fifth terminal of the first differential circuit 110 is electrically connected to the positive power supply voltage VDD. When the analog-to-digital converter 100 is in the sampling phase and the integration phase, i.e. in the first state, the first differential circuit 110 is turned on with the positive voltage VDD of the power supply, the first differential circuit 110 is turned on with the positive voltage output signal VOP, the first differential circuit 110 is also turned on with the voltage output signal VON, and the first differential circuit 110 can sample the positive input voltage signal VIP and the negative input voltage signal VIN respectively. When the analog-to-digital converter 100 is in the comparison stage, i.e., in the second state, the connection between the first differential circuit 110 and the power supply positive voltage VDD is disconnected, the first differential circuit 110 is connected to ground, and charge transfer occurs inside the first differential circuit 110, so that the voltage at the third terminal of the first differential circuit 110 is k1 times of the positive input voltage signal VIP, and the voltage at the fourth terminal of the first differential circuit 110 is k1 times of the negative input voltage signal VIN, where k1 is related to the capacitance of the sampling capacitor in the first differential circuit 110 and the capacitance of the sampling capacitor in the second differential circuit 120.

The first end of the second differential circuit 120 is electrically connected to the reference voltage signal VREF, and in the first state, the second differential circuit 120 is conducted with the reference voltage signal VREF, the second differential circuit 120 is further conducted with the power supply positive voltage VDD, and the second differential circuit 120 may sample the reference voltage signal VREF. In the second state, the connection between the second differential circuit 120 and the reference voltage signal VREF is disconnected, the second differential circuit 120 and the ground are connected, and charge transfer occurs inside the second differential circuit 120, so that the voltage at the second end of the second differential circuit 120 is k2 times of the reference voltage signal VREF, and the voltage at the third end of the second differential circuit 120 is 0; or the voltage at the second terminal of the second differential circuit 120 is 0, and the voltage at the third terminal of the second differential circuit 120 is k2 times of the reference voltage signal VREF, where k2 is related to the capacitance of the sampling capacitor in the first differential circuit 110 and the capacitance of the sampling capacitor in the second differential circuit 120.

In summary, if the positive voltage output signal VOP is equal to the sum of k1 times the positive input voltage signal VIP and k2 times the reference voltage signal VREF, and the negative voltage output signal VON is equal to the sum of k1 times the negative input voltage signal VIN and 0, i.e., the negative voltage output signal VON is equal to k1 times the negative input voltage signal VIN, then the differential signal VOP-VIN = k1 × VIP + k2 × VREF-k1 × VIN = k1 (VIP-VIN) + k2 × VREF is output. Or, the positive voltage output signal VOP is equal to the sum of k1 times and 0 of the positive input voltage signal VIP, that is, the positive voltage output signal VOP is equal to k1 times of the positive input voltage signal VIP, and the negative voltage output signal VON is equal to the sum of k1 times of the negative input voltage signal VIN and k2 times of the reference voltage signal VREF, then the differential signal VOP-VIN = k1= VIP- (k 1 × VIN + k2= VREF) = k1= (VIP-VIN) -k2 × VREF is output.

In this way, the signal obtained by attenuating the reference voltage signal VREF by k2 times is used as the jitter signal Vdith, the input differential signal VIP-VIN may be attenuated by k1 times and then superimposed with the jitter signal Vdith to obtain the output differential signal VOP-VON, and the output differential signal VOP-VON is used as the output signal of the adder 10 for output.

In an embodiment of the present application, the adder includes a first differential circuit and a second differential circuit, a first end of the first differential circuit is electrically connected to a positive input voltage signal, a second end of the first differential circuit is electrically connected to a negative input voltage signal, a third end of the first differential circuit is electrically connected to a positive voltage signal output end of the adder, a fourth end of the first differential circuit is electrically connected to a negative voltage signal output end of the adder, a fifth end of the first differential circuit is electrically connected to a positive voltage of a power supply, a first end of the second differential circuit is electrically connected to a reference voltage signal, a second end of the second differential circuit is electrically connected to a third end of the first differential circuit, a third end of the second differential circuit is electrically connected to a fourth end of the first differential circuit, a sixth end of the first differential circuit and a fourth end of the second differential circuit are both grounded, wherein the positive input voltage signal and the negative input voltage signal constitute an input differential signal; the reference voltage signal and the input differential signal can be superimposed by the adder to obtain the output differential signal and output the output differential signal, so that the reference voltage signal after attenuation is used as a jitter signal, the jitter signal and the input differential signal can be superimposed, and the function of adding the jitter signal can be realized.

In some embodiments, fig. 3 is a schematic structural diagram of another adder provided in the present application, and fig. 3 is a schematic structural diagram of the embodiment shown in fig. 2, where the first differential circuit 110 includes a first switch element 111, a first capacitor C1, a second switch element 112, and a second capacitor C2.

A first end of the first switch element 111 is electrically connected to the positive input voltage signal VIP, a second end of the first switch element 111 is electrically connected to a lower plate of the first capacitor C1, an upper plate of the first capacitor C1 is electrically connected to the positive voltage signal output end and the third end of the first switch element 111, a fourth end of the first switch element 111 is electrically connected to the power supply positive voltage VDD, and a fifth end of the first switch element 111 is grounded. A first end of the second switch assembly 112 is electrically connected to the negative input voltage signal VIN, a second end of the second switch assembly 112 is electrically connected to a lower plate of the second capacitor C2, an upper plate of the second capacitor C2 is electrically connected to the negative voltage signal output end and a third end of the second switch assembly 112, a fourth end of the second switch assembly 112 is electrically connected to the positive power supply voltage VDD, and a fifth end of the second switch assembly 112 is grounded.

Illustratively, as shown in fig. 3, the first switch assembly 111 includes a first switch S1, a second switch S2 and a third switch S3, a first end of the first switch S1 is electrically connected to the positive input voltage signal VIP, a second end of the first switch S1 is electrically connected to a lower plate of the first capacitor C1 and a first end of the second switch S2, an upper plate of the first capacitor C1 is electrically connected to a first end of the third switch S3 and the positive voltage signal output end, a second end of the second switch S2 is grounded, and a second end of the third switch S3 is electrically connected to the power supply positive voltage VDD.

The second switch assembly 112 includes a fourth switch S4, a fifth switch S5 and a sixth switch S6, a first end of the fourth switch S4 is electrically connected to the negative input voltage signal VIN, a second end of the fourth switch S4 is electrically connected to a lower plate of the second capacitor C2 and a first end of the fifth switch S5, an upper plate of the second capacitor C2 is electrically connected to a first end of the sixth switch S6 and the negative voltage signal output end, a second end of the fifth switch S5 is grounded, and a second end of the sixth switch S6 is electrically connected to the positive power supply voltage VDD.

In the first state, the first switch S1 and the third switch S3 are both turned on, and the second switch S2 is turned off, so as to turn on the positive input voltage signal VIP and the first capacitor C1The plate, which connects the upper plate of the first capacitor C1 with the positive power supply voltage VDD, the first capacitor C1 can sample the positive input voltage signal VIP, as shown in fig. 4, and fig. 4 is an equivalent circuit diagram of the adder shown in fig. 3 in the first state. Meanwhile, the fourth switch S4 and the sixth switch S6 are both turned on, and the fifth switch S5 is turned off, so that the negative input voltage signal VIN and the lower plate of the second capacitor C2 can be turned on, the upper plate of the second capacitor C2 and the positive power voltage VDD are turned on, and the second capacitor C2 can sample the negative input voltage signal VIN, as shown in fig. 4. At this time, if the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2 are both 6Cu, the charge Q of the first capacitor C1 _{C1_1} = (VDD-VIP) × 6Cu, charge Q of second capacitor C2 _{C2_1} ＝(VDD-VIN)*6Cu。

In the second state, the first switch S1 and the third switch S3 are both turned off, the second switch S2 is turned on, and the positive input voltage signal VIP is disconnected from the lower plate of the first capacitor C1, the upper plate of the first capacitor C1 is disconnected from the power supply positive voltage VDD, and the lower plate of the first capacitor C1 is connected to ground, as shown in fig. 5, fig. 5 is an equivalent circuit diagram of the adder shown in fig. 3 in the second state. Meanwhile, the fourth switch S4 and the sixth switch S6 are both turned off, and the fifth switch S5 is turned on, so that the connection between the negative input voltage signal VIN and the lower plate of the second capacitor C2 is disconnected, the connection between the upper plate of the second capacitor C2 and the positive power supply voltage VDD is disconnected, and the lower plate of the second capacitor C2 is turned on and grounded, as shown in fig. 5. At this time, the charge Q of the first capacitor C1 _{C1_2} = VOP 6Cu, charge Q of the second capacitor C2 _{C2_2} ＝VON*6Cu。

In this way, the first switch element 111 may conduct the positive input voltage signal VIP and the lower plate of the first capacitor C1, and conduct the upper plate of the first capacitor C1 and the power positive voltage VDD in the first state; in the second state, the positive input voltage signal VIP is disconnected from the lower plate of the first capacitor C1, the upper plate of the first capacitor C1 is disconnected from the power supply positive voltage VDD, and the lower plate of the first capacitor C1 is connected to ground. The second switch component 112 may conduct the negative input voltage signal VIN and the lower plate of the second capacitor C2 in the first state, and conduct the upper plate of the second capacitor C2 and the positive power supply voltage VDD; in the second state, the negative input voltage signal VIN is disconnected from the lower plate of the second capacitor C2, the upper plate of the second capacitor C2 is disconnected from the positive power supply voltage VDD, and the lower plate of the second capacitor C2 is connected to ground.

As shown in fig. 3 to 5, during the process of switching the first state to the second state, only the second switch S2 and the fifth switch S5 in the first differential circuit 110 need to be turned on, since the second switch S2 and the fifth switch S5 are grounded and have stronger driving force for the second switch S2 and the fifth switch S5, the second switch S2 and the fifth switch S5 can be turned on quickly, so as to reduce the power consumption of the positive input voltage signal VIP and the negative input signal VIN, i.e. reduce the power consumption of the input differential signal, and thus reduce the power consumption of the adder 10.

In an embodiment of the present application, the first differential circuit includes a first switch component, a first capacitor, a second switch component and a second capacitor, a first end of the first switch component is electrically connected to a positive input voltage signal, a second end of the first switch component is electrically connected to a lower plate of the first capacitor, an upper plate of the first capacitor is electrically connected to a positive voltage signal output end and a third end of the first switch component, a fourth end of the first switch component is electrically connected to a positive voltage of a power supply, and a fifth end of the first switch component is grounded. The first end electricity of second switch module connects negative input voltage signal, the second end electricity of second switch module connects the bottom plate of second electric capacity, the third end of negative voltage signal output end and second switch module is connected to the last polar plate electricity of second electric capacity, the fourth end electricity of second switch module connects the power positive voltage, the fifth end ground connection of second switch module, so, first differential circuit is the circuit of compriseing switch and electric capacity, so can reduce first differential circuit's area and cost, promote first differential circuit's precision, thereby can reduce the area and the cost of adder, promote the precision of adder.

In some embodiments, with continued reference to fig. 3, the second differential circuit 120 includes a third switching component 121, a third capacitance C3, a fourth switching component 122, and a fourth capacitance C4.

The first end of the third switch component 121 and the first end of the fourth switch component 122 are both electrically connected to a reference voltage signal VREF, the second end of the third switch component 121 is electrically connected to the lower plate of the third capacitor C3, the upper plate of the third capacitor C3 is electrically connected to the positive voltage signal output end, the second end of the fourth switch component 122 is electrically connected to the lower plate of the fourth capacitor C4, the upper plate of the fourth capacitor C4 is electrically connected to the negative voltage signal output end, and the third end of the third switch component 121 and the third end of the fourth switch component 122 are both grounded.

Illustratively, as shown in fig. 3, the third switch assembly 121 includes a seventh switch S7 and an eighth switch S8, a first end of the seventh switch S7 is electrically connected to the reference voltage signal VREF, a second end of the seventh switch S7 is electrically connected to the lower plate of the third capacitor C3 and a first end of the eighth switch S8, and a second end of the eighth switch S8 is grounded. The fourth switch assembly 122 includes a ninth switch S9 and a tenth switch S10, a first end of the ninth switch S9 is electrically connected to the reference voltage signal VREF, a second end of the ninth switch S9 is electrically connected to the lower plate of the fourth capacitor C4 and the first end of the tenth switch S10, and a second end of the tenth switch S10 is grounded.

In the first state, the seventh switch S7 is turned on, the eighth switch S8 is turned off, the reference voltage signal VREF and the lower plate of the third capacitor C3 can be turned on, the upper plate of the third capacitor C3 is turned on with the positive power supply voltage VDD, and the third capacitor C3 can sample the reference voltage signal VREF, as shown in fig. 4. Meanwhile, the tenth switch S10 is turned on, the ninth switch S9 is turned off, the lower plate of the fourth capacitor C4 may be turned on with the ground, the upper plate of the fourth capacitor C4 may be turned on with the positive power voltage VDD, and the fourth capacitor C4 may sample the positive power voltage VDD, as shown in fig. 4. At this time, if the capacitance of the third capacitor C3 and the capacitance of the fourth capacitor C4 are both Cu, the charge Q of the third capacitor C3 _{C3_1} = (VDD-VREF) × Cu, charge Q of fourth capacitance C4 _{C4_1} ＝VDD*Cu。

In the second state, the seventh switch S7 is turned off, the eighth switch S8 is turned on, the connection between the reference voltage signal VREF and the lower plate of the third capacitor C3 is disconnected, the lower plate of the third capacitor C3 is turned on and grounded, and the connection between the upper plate of the third capacitor C3 and the power supply positive voltage VDD is disconnected, as shown in fig. 5. At the same time, the tenth switch S10 is turned on, the ninth switch S9 is turned off, and the lower electrode of the fourth capacitor C4The plate is maintained in an on state with ground and the connection between the upper plate of the fourth capacitor C4 and the supply positive voltage VDD is broken as shown in fig. 5. At this time, the charge Q of the third capacitor C3 _{C3_2} = VOP Cu, charge Q of the fourth capacitor C4 _{C4_2} ＝VON*Cu。

In this way, the third switch component 121 can turn on the reference voltage signal VREF and the lower plate of the third capacitor C3 in the first state, turn off the connection between the reference voltage signal VREF and the lower plate of the third capacitor C3 in the second state, and turn on the lower plate of the third capacitor C3 and the ground. The fourth switch assembly 122 is capable of turning on the lower plate of the fourth capacitor C4 and the ground in the first state, and maintaining the lower plate of the fourth capacitor C4 in conduction with the ground in the second state.

In the first state, the sum of the charges of all capacitors on the positive input side of the adder 10 is Q _P1 And Q _P1 ＝Q _{C1_1} +Q _{C3_1} = (VDD-VIP) × 6Cu + (VDD-VREF) × Cu, the sum of the charges of all capacitors on the negative input side of the adder 10 is Q _N1 And Q is _N1 ＝Q _{C2_1} +Q _{C4_1} = (VDD-VIN) { 6Cu + } VDD }. Cu. In the second state, the sum of the charges of all capacitors on the positive input side of the adder 10 is Q _P2 And Q _P2 ＝Q _{C1_2} +Q _{C3_2} VOP 6Cu + VOP Cu = VOP 7Cu, and the sum of the charges of all capacitors on the negative input side of the adder 10 is Q _N2 And Q is _N2 ＝Q _{C2_2} +Q _{C4_2} = VON × 6cu + VON cu = VON × 7cu. Conservation of energy, i.e., Q, at the positive input side of the adder 10 in the first and second states _P1 ＝Q _P2 Therefore, VOP = (VDD-VIP) × 6Cu + (VDD-VREF) × Cu, and VOP = (VDD × 7-VIP × 6-VREF)/7. Conservation of energy on the negative input side of the adder 10 in the first and second states, i.e. Q _N1 ＝Q _N2 Therefore, (VDD-VIN) } 6Cu + VDD + Cu = VON + 7Cu, then VON = (VDD × 7-VIN × 6)/7. Thus, the differential signal VOP-VON = -6 (VIP-VIN)/7-VREF/7 is output, and at this time, k1= -6/7, and k2=1/7.

In another embodiment, in the first state, the seventh switch S7 is turned off, the eighth switch S8 is turned on, the lower plate of the third capacitor C3 and the ground can be connected, and the upper plate of the third capacitor C3 and the ground can be connectedThe source positive voltage VDD is turned on and the third capacitor C3 may sample the source positive voltage VDD. Meanwhile, when the tenth switch S10 is turned off and the ninth switch S9 is turned on, the reference voltage signal VREF and the lower plate of the fourth capacitor C4 may be turned on, the upper plate of the fourth capacitor C4 is turned on with the positive voltage VDD of the power supply, and the fourth capacitor C4 may sample the reference voltage signal VREF. At this time, if the capacitance of the third capacitor C3 and the capacitance of the fourth capacitor C4 are both Cu, the charge Q of the third capacitor C3 _{C3_1} = VDD × Cu, charge Q of fourth capacitor C4 _{C4_1} ＝(VDD-VREF)*Cu。

In the second state, the seventh switch S7 is turned off, the eighth switch S8 is turned on, the lower plate of the third capacitor C3 is kept in a conductive state with respect to the ground, and the connection between the upper plate of the third capacitor C3 and the power supply positive voltage VDD is disconnected. Meanwhile, the tenth switch S10 is turned on, the ninth switch S9 is turned off, the connection between the reference voltage signal VREF and the lower plate of the fourth capacitor C4 is disconnected, the lower plate of the fourth capacitor C4 is connected to the ground, and the connection between the upper plate of the fourth capacitor C4 and the positive power supply voltage VDD is disconnected. At this time, the charge Q of the third capacitor C3 _{C3_2} = VOP Cu, charge Q of the fourth capacitor C4 _{C4_2} ＝VON*Cu。

In this way, the third switch component 121 can conduct the lower plate of the third capacitor C3 and the ground in the first state, and maintain the lower plate of the third capacitor C3 to be conducted with the ground in the second state. The fourth switching element 122 is capable of turning on the reference voltage signal VREF and the lower plate of the fourth capacitor C4 in the first state, turning off the connection between the reference voltage signal VREF and the lower plate of the fourth capacitor C4 in the second state, and turning on the lower plate of the fourth capacitor C4 and the ground.

In the first state, the sum Q of the charges of all capacitors at the positive input side of the adder 10 _P1 ＝Q _{C1_1} +Q _{C3_1} = (VDD-VIP) × 6cu + VDD × cu, the sum Q of the charges of all capacitors on the negative input side of the adder 10 _N1 ＝Q _{C2_1} +Q _{C4_1} = (VDD-VIN) × 6Cu + (VDD-VREF) × Cu. In the second state, the sum Q of the charges of all capacitors on the positive input side of the adder 10 _P2 ＝Q _{C1_2} +Q _{C3_2} = VOP × 7Cu, sum Q of charges of all capacitors on negative input side of adder 10 _N2 ＝Q _{C2_2} +Q _{C4_2} = VON 7Cu. According to Q _P1 ＝Q _P2 It is possible to obtain (VDD-VIP) } 6Cu + VDD = VOP = 7Cu, then VOP = (VDD × 7-VIP = 6)/7, according to Q = _N1 ＝Q _N2 It is possible to obtain (VDD-VIN) × 6Cu + (VDD-VREF) × Cu = VON × 7Cu, and then VON = (VDD × 7-VIN × 6-VREF)/7. Thus, VOP-VON = -6 (VIP-VIN)/7 + VREF/7, at which time k1= -6/7, k2= -1/7.

As shown in fig. 3 to 5, in the process of switching the first state to the second state, only the eighth switch S8 and the tenth switch S10 in the second differential circuit 120 need to be turned on, since the eighth switch S8 and the tenth switch S10 are grounded and have a strong driving force for the eighth switch S8 and the tenth switch S10, the eighth switch S8 and the tenth switch S10 can be turned on quickly, so that the power consumption of the reference voltage signal VREF can be reduced, and the power consumption of the adder 10 can be reduced.

In this embodiment, the second differential circuit includes a third switch assembly, a third capacitor, a fourth switch assembly and a fourth capacitor, a first end of the third switch assembly and a first end of the fourth switch assembly are both electrically connected to a reference voltage signal, a second end of the third switch assembly is electrically connected to a lower plate of the third capacitor, an upper plate of the third capacitor is electrically connected to a positive voltage signal output end, a second end of the fourth switch assembly is electrically connected to a lower plate of the fourth capacitor, an upper plate of the fourth capacitor is electrically connected to a negative voltage signal output end, and a third end of the third switch assembly and a third end of the fourth switch assembly are both grounded.

In some embodiments, during the switching from the first state to the second state, the connection between the positive input voltage signal VIP and the lower plate of the first capacitor C1 is broken at a time later than the connection between the upper plate of the first capacitor C1 and the power supply positive voltage VDD.

For example, fig. 6 is an overall timing diagram of an analog-to-digital converter according to an embodiment of the present application, as shown in fig. 6, the analog-to-digital converter switches to an integration phase after a sampling phase is ended, a dither signal is added when the integration phase is about to be ended, and during the addition of the dither signal and during the switching from the integration phase to the sampling phase, the analog-to-digital converter enters a comparison phase. At the end of the comparison phase, the addition of the dither signal is ended and the analog-to-digital converter enters the sampling phase again.

Fig. 7 is a switch timing diagram of a dither signal adding process according to an embodiment of the present application, and as shown in fig. 3 and fig. 7, the first switch S1 controls on/off between the positive input voltage signal VIP and the lower plate of the first capacitor C1, the third switch S3 controls on/off between the upper plate of the first capacitor C1 and the power supply positive voltage VDD, and the off-time of the third switch S3 is earlier than the off-time of the first switch S1, that is, the time of disconnection between the upper plate of the first capacitor C1 and the power supply positive voltage VDD is earlier than the time of disconnection between the positive input voltage signal VIP and the lower plate of the first capacitor C1, which can avoid signal-dependent errors introduced by charge injection of the third switch S3, can improve the precision of the positive output voltage signal VOP, and thus can improve the precision of the adder 10.

The fourth switch S4 controls the on-off between the negative input voltage signal VIN and the lower plate of the fourth capacitor C4, the sixth switch S6 controls the on-off between the upper plate of the fourth capacitor C4 and the power supply positive voltage VDD, the cut-off time of the sixth switch S6 is earlier than the cut-off time of the fourth switch S4, that is, the time of the disconnection between the upper plate of the fourth capacitor C4 and the power supply positive voltage VDD is earlier than the time of the disconnection between the negative input voltage signal VIN and the lower plate of the fourth capacitor C4, so that signal-related errors caused by charge injection of the sixth switch S6 can be avoided, the precision of the negative output voltage signal VON can be improved, and the precision of the adder 10 can be improved.

In some embodiments, with continued reference to fig. 3 and 7, during the switching of the first state to the second state, the connection between the upper plate of the first capacitor C1 and the supply positive voltage VDD is broken at a time later than the connection between the reference voltage signal VREF and the lower plate of the third capacitor C3.

Illustratively, as shown in fig. 3 and 7, the seventh switch S7 controls the on/off between the reference voltage signal VREF and the lower plate of the third capacitor C3, and the off time of the seventh switch S7 is earlier than the off time of the third switch S3, that is, the time of disconnection between the reference voltage signal VREF and the lower plate of the third capacitor C3 is earlier than the time of disconnection between the upper plate of the first capacitor C1 and the power supply positive voltage VDD, so that signal-dependent errors caused by charge injection of the seventh switch S7 can be avoided, the accuracy of the positive output voltage signal VOP can be improved, and thus the accuracy of the adder 10 can be improved.

In some embodiments, fig. 8 is a schematic structural diagram of another adder provided in an embodiment of the present application, and fig. 8 is a schematic structural diagram of the embodiment shown in fig. 2, where the adder 10 further includes a third differential circuit 130, a first end of the third differential circuit 130 is electrically connected to the reference voltage signal VREF, a second end of the third differential circuit 130 is electrically connected to a third end of the first differential circuit 110, a third end of the third differential circuit 130 is electrically connected to a fourth end of the first differential circuit 110, and fourth ends of the third differential circuit 130 are both grounded.

For example, fig. 9 is a schematic structural diagram of another adder provided in the embodiment of the present application, and fig. 9 is a schematic structural diagram of the embodiment shown in fig. 8, where the third differential circuit 130 includes a fifth switch element 131, a fifth capacitor C5, a sixth switch element 132, and a sixth capacitor C6, and capacitance values of the fifth capacitor C5 and the sixth capacitor C6 are the same. A first end of the fifth switch component 131 and a first end of the sixth switch component 132 are both electrically connected to a reference voltage signal VREF, a second end of the fifth switch component 131 is electrically connected to a lower plate of a fifth capacitor C5, an upper plate of the fifth capacitor C5 is electrically connected to a positive voltage signal output terminal VOP, a second end of the sixth switch component 132 is electrically connected to a lower plate of a sixth capacitor C6, an upper plate of the sixth capacitor C6 is electrically connected to a negative voltage signal output terminal VON, and a third end of the fifth switch component 131 and a third end of the sixth switch component 132 are both grounded.

The fifth switch assembly 131 includes an eleventh switch S11 and a twelfth switch S12, a first end of the eleventh switch S11 is electrically connected to the reference voltage signal VREF, a second end of the eleventh switch S11 is electrically connected to the lower plate of the fifth capacitor C5 and the first end of the twelfth switch S12, and a second end of the twelfth switch S12 is grounded. The sixth switch assembly 132 includes a thirteenth switch S13 and a fourteenth switch S14, a first end of the thirteenth switch S13 is electrically connected to the reference voltage signal VREF, a second end of the thirteenth switch S13 is electrically connected to the lower plate of the sixth capacitor C6 and a first end of the fourteenth switch S14, and a second end of the fourteenth switch S14 is grounded.

It should be noted that fig. 8 and 9 only exemplarily show that the adder 10 includes the first differential circuit 110, the second differential circuit 120, and the third differential circuit 130, that is, the adder 10 includes the first differential circuit 110 and two other differential circuits. In other embodiments, the adder 10 further includes the first differential circuit 110 and two or more other differential circuits, where capacitance values of two capacitors in the same other differential circuit are the same, capacitance values of capacitors in different other differential circuits are different, and a specific capacitance value may be adjusted proportionally based on the number of other differential circuits.

For example, the capacitance values of the third capacitor C3 and the fourth capacitor C4 in the second differential circuit 120 are the same, and the capacitance values of the fifth capacitor C5 and the sixth capacitor C6 in the third differential circuit 130 are the same. For example, the capacitance values of the third capacitor C3 and the fifth capacitor C5 are the same, the capacitance values of the third capacitor C3 and the sixth capacitor C6 are the same, the capacitance values of the fourth capacitor C4 and the fifth capacitor C5 are the same, and the capacitance values of the fourth capacitor C4 and the sixth capacitor C6 are the same.

The embodiment of the present application further provides a semiconductor chip, including the adder 10 provided in any one of the above embodiments.

Illustratively, the adder 10 provided by any of the above embodiments is integrated into a semiconductor chip, so that the size of the adder 10 can be reduced, which is beneficial to the miniaturization development of the adder 10.

The semiconductor chip provided by the embodiment of the present application includes the adder 10 provided by any one of the above embodiments, and has the same functional modules and beneficial effects as the adder 10, and details are not described here.

The above disclosure is only for the specific embodiments of the present application, but the embodiments of the present application are not limited thereto, and any variations that can be considered by those skilled in the art are intended to fall within the scope of the present application.

The word "comprising" as used herein does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means can be embodied by one and the same item of hardware. The use of first, second, third, etc. does not denote any order, and the words may be interpreted as names. The steps in the above embodiments should not be construed as limiting the order of execution unless specified otherwise.

The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present application.

Claims

1. An adder, comprising: a first differential circuit and a second differential circuit;

2. The adder according to claim 1, wherein the first differential circuit comprises a first switching element, a first capacitor, a second switching element, and a second capacitor;

the first end of the first switch assembly is electrically connected with the positive input voltage signal, the second end of the first switch assembly is electrically connected with the lower pole plate of the first capacitor, the upper pole plate of the first capacitor is electrically connected with the positive voltage signal output end and the third end of the first switch assembly, the fourth end of the first switch assembly is electrically connected with the positive voltage of the power supply, and the fifth end of the first switch assembly is grounded;

3. The summer of claim 2, wherein the first switch assembly includes a first switch, a second switch, and a third switch;

the first end electricity of fourth switch is connected the negative input voltage signal, the second end electricity of fourth switch connect with the second electric capacity the bottom plate with the first end of fifth switch, the top plate electricity of second electric capacity the first end of sixth switch with negative voltage signal output part, the second end ground connection of fifth switch, the second end electricity of sixth switch is connected the power positive voltage.

4. The adder of claim 2 or 3, wherein the second differential circuit comprises a third switching component, a third capacitor, a fourth switching component, and a fourth capacitor;

5. The summer of claim 4, wherein the third switch assembly includes a seventh switch and an eighth switch;

the fourth switch assembly comprises a ninth switch and a tenth switch;

a first end of the ninth switch is electrically connected to the reference voltage signal, a second end of the ninth switch is electrically connected to the lower plate of the fourth capacitor and the first end of the tenth switch, and a second end of the tenth switch is grounded.

6. The adder according to claim 4, wherein the first switch element is configured to conduct the positive input voltage signal and the lower plate of the first capacitor in a first state, and conduct the upper plate of the first capacitor and the positive power supply voltage; in a second state, disconnecting the positive input voltage signal from the lower plate of the first capacitor, disconnecting the upper plate of the first capacitor from the positive power supply voltage, and connecting the lower plate of the first capacitor to ground;

7. The adder according to claim 6, wherein during the switching from the first state to the second state, the connection between the positive input voltage signal and the lower plate of the first capacitor is broken at a time later than the connection between the upper plate of the first capacitor and the positive supply voltage.

8. The adder according to claim 6, wherein said third switch component is configured to conduct said reference voltage signal and a lower plate of said third capacitor in said first state; disconnecting the reference voltage signal from the lower plate of the third capacitor and connecting the lower plate of the third capacitor with the ground in the second state;

9. The adder according to claim 8, wherein during the switching from the first state to the second state, the connection between the upper plate of the first capacitor and the positive supply voltage is broken at a time later than the connection between the reference voltage signal and the lower plate of the third capacitor.

10. The adder according to any one of claims 1 to 3, further comprising a third differential circuit;

11. An analog-to-digital converter comprising an adder according to claims 1-10.

12. A semiconductor chip comprising the adder according to claims 1 to 10.