CN115902597A - BGA/LGA device back EMMI failure analysis method - Google Patents

Abstract

The invention discloses a BGA/LGA device back EMMI failure analysis method, which analyzes a BGA/LGA device substrate layout obtained by a grinding technology and determines the one-to-one corresponding relation between a binding line and a device solder ball by adopting an X-ray technology, thereby providing accurate electrical connection for the device back EMMI and realizing the BGA/LGA device back EMMI analysis. When performing EMMI on the back surface of an integrated circuit, correct electrical connection needs to be realized firstly, because the IO ports are numerous and binding wires are firstly rewired through a substrate and then connected with external welding points. The invention can quickly and simply obtain the one-to-one corresponding relation between the binding line of the BGA/LGA device and the external welding spot, thereby providing accurate electrical connection for the EMMI on the back surface of the BGA/LGA device, realizing the failure analysis of the EMMI on the back surface of the BGA/LGA device, expanding the applicability of the failure analysis of the EMMI on the back surface of the integrated circuit and reducing the limitation of the EMMI on the back surface of the integrated circuit.

Description

BGA/LGA device back EMMI failure analysis method

Technical Field

The invention relates to the field of integrated circuit manufacturing, in particular to an EMMI (empirical mode decomposition) failure analysis method for the back surface of a BGA/LGA (ball grid array/land grid array) device.

Background

For semiconductor devices, micro-optical microscopy (EMMI) has proven to be a useful and highly efficient tool for detecting photons emitted by electron-hole combinations and hot carriers.

As the size of the device decreases and the integration degree increases, the number of metal layers of the chip increases, and the light emitting effect of the leakage current blocking from the front surface is exhibited by an excessive number of metal layers, so that the EMMI is generally performed from the back surface for a chip with metal layers exceeding 3 layers.

During back EMMI, the back of the device is ground to expose the substrate of the silicon wafer encapsulated in the package, so that photons are transmitted through the silicon wafer and received by the detector, thereby locating defects.

When back grinding is carried out, the leading-out terminal on the back of the device is also ground, only the wire head of the binding wire is left, and then a probe is pricked to a signal Input and Output (IO) terminal and a power supply or ground terminal so as to realize correct power-on.

Chinese patent 201310028.1 discloses a method for preparing a backside optical failure positioning sample of an integrated circuit, comprising: step 1, carrying out open-circuit and short-circuit tests on a sample, applying a current by using an ATE (automatic test equipment) machine table of a tester to judge whether the voltage is in a normal range, and carrying out next analysis after determining that the open-circuit and short-circuit test voltage is in the normal range; step 2, grinding the back plastic package material of the failed sample by using a manual grinding machine table; step 3, after the device is unsealed, cleaning the device by using an ultrasonic cleaner, removing residues remained on the back of the chip, selecting the normal temperature and the constant temperature, carrying out ultrasonic cleaning for 8-15 minutes to obtain a clean sample, and naturally drying; and 4, measuring the electrical characteristic parameters of the sample by using an Automatic Test Equipment (ATE) again, confirming that the characteristics of the sample are completely consistent with those of the sample before sample preparation, and greatly improving the success rate of nondestructive unsealing and the failure analysis speed. The invention also relates to a failure analysis method of the sample.

Chinese patent 201010605339.6 discloses a failure analysis method for a semiconductor device, which includes the steps of: removing the copper layer on the back surface of the semiconductor device; thinning a silicon layer on the back of the semiconductor device; and locating a failure point on the back side of the semiconductor device using an optical micro microscope (EMMI) and/or laser beam induced resistance value variation test (OBIRCH) electrical positioning apparatus. According to the failure analysis method, the copper is removed from the back of the semiconductor device, the silicon layer is thinned, and the failure point is positioned, so that the time is saved, and the efficiency and the success rate are improved.

Chinese patent 201310028.1 describes a sample preparation and analysis method for positioning optical failure on the back surface of an integrated circuit, which is a conventional method for the back surface of an integrated circuit, is suitable for devices packaged by DIP, SOP, LCC, QFN and the like, and can obtain the back surface of a chip well without damaging a lead frame, thereby realizing the purpose of providing electrical connection for positioning failure points. However, in the case of BGA/LGA devices, the lead frame must be completely ground away if the back side of the chip is exposed, and the electrical connection at the failure point cannot be determined by this method.

The chinese patent 201010605339.6 mainly aims at the situation that when the surface of a semiconductor device is covered by a large block of aluminum (such as DMOS), photons cannot penetrate through the aluminum when EMMI is used for failure analysis.

Disclosure of Invention

The technical purpose of the invention is to provide a back EMMI failure analysis method of a BGA/LGA device, which can effectively improve the analysis efficiency of the back EMMI of the device without providing the corresponding relation between a binding line and an external welding point by a device designer. The technical principle of the invention is to analyze the BGA/LGA device substrate layout obtained by grinding technology and determine the one-to-one corresponding relation between the binding line and the device solder ball by adopting X-ray technology, so as to provide accurate electrical connection for the device back side EMMI, thereby realizing the back side EMMI analysis of the BGA/LGA device. When the EMM I is carried out on the back surface of the integrated circuit, correct electrical connection is firstly realized, the prior art is only suitable for packaged devices such as DIP, SOP, LCC, QFN and the like, and the electrical connection of the EMMI on the back surface is easily realized because the number of IO ports is small and binding lines and the IO ports are in one-to-one correspondence. For the back EMMI of BGA/LGA device, because of its numerous IO ports, and the binding wires are re-wired through the substrate first and then connected with the external pads (fig. 1), it is impossible to implement simple one-to-one correspondence. The electrical connection relationship of the back side EMMI can be determined only by the corresponding relationship between the bonding lines and the external pads provided by the device designer. For the users of the devices, such a correspondence relationship cannot be generally obtained, which brings great limitations to the failure analysis of the BGA/LGA devices.

In order to solve the problems in the background art and achieve the technical purpose of the present invention, the technical scheme adopted by the present invention is a BGA/LGA device back side EMMI failure analysis method, which comprises the following steps:

firstly, carrying out volt-ampere (IV) characteristic test on the BGA/LGA device to obtain a volt-ampere characteristic curve of a failed pin, and determining the position of the failed pin in an external welding spot.

Secondly, grinding the external welding spot of the failed BGA/LGA device to expose the bonding pad and the through hole, determining the positions of the bonding pad and the through hole of the failed pin according to a data manual of the BGA/LGA device, and photographing the layout of the layer;

grinding a substrate of a failure pin of the BGA/LGA device to expose a copper-clad layer, and determining the position of a failure pin through hole on the copper-clad layer;

fourthly, repeating the grinding of the substrate in the third step, grinding layer by layer until the last layer of metal wiring on the substrate is exposed, and confirming the position of the failure pin through hole;

fifthly, carrying out volt-ampere curve test on the metal wiring where the failure pin through hole is located to obtain a volt-ampere curve, and comparing and confirming the volt-ampere curve with the volt-ampere characteristic curve obtained in the first step; if the voltammetry curve in the fifth step is the same as or similar to the voltammetry curve obtained in the first step (resistance value changes due to the removal of the substrate by grinding), the sixth step is carried out, and if the voltammetry curve is different from the voltammetry curve obtained in the first step, two possibilities exist: firstly), if the failed pin is positioned wrongly, comparing the substrate layouts obtained in the second step to the fifth step, and re-confirming the position of the failed pin; two) the failure location is located on the substrate and not on the chip.

And sixthly, carrying out X-ray photographing on the BGA/LGA device, determining the position of a binding line connected with the metal wiring connected with the failed pin through hole, and recording the position.

Seventhly, grinding and removing the last layer of metal wiring to expose the silicon chip substrate and the binding wire head, and finding out the binding wire position recorded in the sixth step;

and eighthly, puncturing the probe to the binding wire end and the power supply or ground end of the failed pin to realize correct power-on.

The ninth step, back EMMI is performed. The binding lines and the external welding points are in one-to-one correspondence through the back EMMI, so that accurate electrical connection is provided for the back EMMI of the integrated circuit, and failure analysis of the back EMMI of the integrated circuit is realized.

The invention can achieve the technical effects that:

the prior integrated circuit back EMMI technology is only suitable for devices packaged by DIP, SOP, LCC, QFN and the like, can better obtain the back of a chip under the condition of not damaging a lead frame, and realizes the purpose of providing electrical connection for positioning failure points. For the back EMMI of BGA/LGA device, the corresponding relation between the binding line and the external welding point provided by the device design manufacturer is required to determine the electrical connection relation of the back EMMI. For the users of the devices, such a correspondence relationship cannot be generally obtained, which brings great limitations to the failure analysis of the BGA/LGA devices.

The invention can quickly and simply obtain the one-to-one corresponding relation between the binding line of the BGA/LGA device and the external welding spot, thereby providing accurate electrical connection for the EMMI at the back of the BGA/LGA device, realizing the failure analysis of the EMMI at the back of the BGA/LGA device, expanding the applicability of the failure analysis of the EMMI at the back of the integrated circuit and reducing the limitation of the EMMI at the back of the integrated circuit.

Drawings

Some specific embodiments of the invention will be described in detail hereinafter, by way of illustration and not limitation, with reference to the accompanying drawings.

The same reference numbers in the drawings identify the same or similar elements or components. As will be appreciated by those skilled in the art, these

The drawings are not necessarily to scale. In the drawings:

fig. 1 is a longitudinal structural view of the BGA device.

FIG. 2 is a back side of a failure sample of an embodiment of the present invention.

FIG. 3 shows the profile of a failed sample after solder points have been ground off on the back side.

Fig. 4 shows the copper clad layer of the failed sample substrate according to an embodiment of the present invention.

FIG. 5 is an X-ray of a failed sample substrate according to an embodiment of the present invention.

FIG. 6 is a graph showing the effect of back EMMI performed by the embodiment of the present invention.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and examples.

A method for analyzing EMMI (empirical mode decomposition) failure of the back surface of a BGA/LGA device comprises the first step of carrying out volt-ampere (IV) characteristic test on a failure pin of the BGA/LGA device, and the back surface appearance of the device is shown in figure 2.

Secondly, grinding the external welding spots of the failed BGA/LGA device to expose the bonding pads and the through holes, and determining the positions of the bonding pads and the through holes of the failed pins according to a data manual of the device, wherein the positions are shown in figure 3;

thirdly, grinding the substrate to expose the copper-clad layer, and determining the position of the failure pin through hole on the copper-clad layer, as shown in fig. 4;

fourthly, repeating the third step, and grinding the substrate layer by layer until the metal step line is exposed at the last layer, as shown in figure 5;

fifthly, performing IV curve test on the metal step line where the failure pin through hole is located, and comparing and confirming the IV curve with the IV curve obtained in the first step;

sixthly, performing X-ray photographing on the device, and determining the position relationship between the binding line of the failed pin and the metal step line, as shown in figure 5;

grinding the substrate to expose the silicon wafer substrate and the binding wire head;

and eighthly, pricking the probes to the binding wire ends and the power supply or ground ends of the failed pins to realize correct power-on.

The ninth step, back EMMI is performed.

Claims (2)

1. A method for analyzing EMMI failure of the back surface of a BGA/LGA device is characterized by comprising the following steps:

firstly, carrying out volt-ampere characteristic test on a BGA/LGA device to obtain a volt-ampere characteristic curve of a failure pin, and determining the position of the failure pin in an external welding spot;

secondly, grinding the external welding spot of the failed BGA/LGA device to expose the bonding pad and the through hole, determining the positions of the bonding pad and the through hole of the failed pin according to a data manual of the BGA/LGA device, and photographing the layout of the layer;

grinding a substrate of a failure pin of the BGA/LGA device to expose a copper-clad layer, and determining the position of a failure pin through hole on the copper-clad layer;

fourthly, repeating the grinding of the substrate in the third step, grinding layer by layer until the last layer of metal wiring on the substrate is exposed, and confirming the position of the failure pin through hole;

fifthly, carrying out volt-ampere curve test on the metal wiring where the failure pin through hole is located to obtain a volt-ampere curve, and comparing and confirming the volt-ampere curve with the volt-ampere characteristic curve obtained in the first step;

sixthly, carrying out X-ray photographing on the BGA/LGA device, determining the position of a binding line connected with the metal wiring connected with the failure pin through hole, and recording the position;

seventhly, grinding and removing the last layer of metal wiring to expose the silicon chip substrate and the binding wire head, and finding out the binding wire position recorded in the sixth step;

eighthly, puncturing the probes to the binding wire ends and the power supply or the ground end of the failed pins to realize correct power-on;

the ninth step, carry on the back EMMI; the binding lines and the external welding points are in one-to-one correspondence through the back EMMI, so that accurate electrical connection is provided for the back EMMI of the integrated circuit, and failure analysis of the back EMMI of the integrated circuit is achieved.

2. The method of claim 1, wherein in the fifth step, the sixth step is performed if the voltammetry curve of the fifth step is the same as or similar to the voltammetry curve obtained in the first step; if not the same, there are two possibilities: firstly), if the failed pin is positioned wrongly, comparing the substrate layouts obtained in the second step to the fifth step, and re-confirming the position of the failed pin; two) the failure position is located on the substrate but not on the chip; .

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