CN115902597A - BGA/LGA device back EMMI failure analysis method - Google Patents

Abstract

The invention discloses an EMMI failure analysis method on the back side of a BGA/LGA device. The method analyzes the BGA/LGA device substrate layout obtained by grinding technology and adopts X-ray technology to determine the one-to-one correspondence between bonding lines and device solder balls relationship, provide accurate electrical connection for the EMMI on the back of the device, and realize the EMMI analysis on the back of the BGA/LGA device. When performing EMMI on the back of the integrated circuit, the correct electrical connection must first be achieved, because there are many IO ports and the bonding wires are rewired through the substrate first, and then connected to the external solder joints. The invention can quickly and easily obtain the one-to-one correspondence between the BGA/LGA device bonding wire and the external solder joint, thereby providing accurate electrical connection for the EMMI on the back side of the BGA/LGA device circuit, and realizing the failure of the EMMI on the back side of the BGA/LGA device analysis, expanding the applicability of IC backside EMMI failure analysis and reducing the limitations of IC backside EMMI.

Description

A method for EMMI failure analysis on the back side of BGA/LGA devices

technical field

The invention relates to the field of integrated circuit manufacturing, in particular to an EMMI failure analysis method on the back side of a BGA/LGA device.

Background technique

For semiconductor devices, the Emission Microscope (EMMI) has been proven to be a very useful and highly efficient defect localization tool, which is used to detect electron-hole combination and hot carrier excitation. photon.

With the reduction of device size and the increase of integration, the number of metal layers of the chip is increasing, and too many metal layers will block the light-emitting effect of leakage from the front. Therefore, for chips with more than 3 metal layers, generally from EMMI on the back.

When performing backside EMMI, the backside of the device must be ground to expose the substrate of the silicon wafer enclosed in the package, so that photons can pass through the silicon wafer and be received by the detector, thereby realizing the positioning of the defect.

When performing back grinding, the leads on the back of the device are also ground off, leaving only the ends of the binding wires, and then the probes are tied to the signal input and output (IO) terminals and power or ground terminals to achieve correct power-up.

Chinese patent 201310028028.1 discloses a method for preparing samples for optical failure location on the back of integrated circuits, including: Step 1. Conduct open and short circuit tests on the samples, and use a tester ATE machine to apply a current to determine whether the voltage is in the normal range. After confirming that the open and short circuit test voltage is in the normal range, proceed to the next step of analysis; step 2, use a manual grinder to grind the plastic sealing material on the back of the failed sample; step 3, use an ultrasonic cleaner to clean the device after unsealing, and remove the remaining Remove the residue on the back of the chip, and use normal temperature and constant temperature to perform ultrasonic cleaning for 8 to 15 minutes to obtain a clean sample and dry it naturally; step 4, use ATE (automatic tester) to measure the electrical characteristic parameters of the sample again to confirm the characteristics of the sample It is exactly the same as before sample preparation, which can greatly improve the success rate of non-destructive unsealing and the speed of failure analysis. The invention also relates to a failure analysis method of the sample.

Chinese patent 201010605339.6 discloses a failure analysis method for semiconductor devices, which includes the steps of: removing the copper layer on the back of the semiconductor device; thinning the silicon layer on the back of the semiconductor device; and using an EMMI and/or laser beam Induced Impedance Change Testing (OBIRCH) Electrical Locating Equipment locates failure points on the backside of semiconductor devices. The failure analysis method saves time and improves efficiency and success rate by removing copper, thinning the silicon layer and locating the failure point on the back side of the semiconductor device.

Chinese patent 201310028028.1 introduces sample preparation and analysis methods for optical failure location on the back of integrated circuits. This method is a conventional method for EMMI on the back of integrated circuits. It is suitable for devices packaged in DIP, SOP, LCC, QFN, etc., without damaging the lead frame In this case, it is better to obtain the back of the chip, so as to provide electrical connection for the location of the failure point. But for BGA/LGA devices, if the back of the chip is to be exposed, the lead frame must be completely ground off, and the electrical connection mode of the failure point cannot be determined by this method.

Chinese patent 201010605339.6 is mainly aimed at the situation that the surface of a semiconductor device is covered with bulk aluminum (such as DMOS), and when EMMI is used for failure analysis, photons cannot pass through the aluminum.

Contents of the invention

The technical purpose of the present invention is to provide a backside EMMI failure analysis method of a BGA/LGA device, which does not require device design manufacturers to provide the corresponding relationship between bonding wires and external solder joints, and effectively improves the analysis efficiency of EMMI on the backside of such devices. The technical principle of the present invention is to analyze the BGA/LGA device substrate layout obtained by grinding technology and adopt X-ray technology to determine the one-to-one correspondence between the bonding wire and the device solder ball, and provide accurate electrical connection for the EMMI on the back of the device , so as to realize the EMMI analysis on the back side of BGA/LGA devices. When performing EMM I on the back of the integrated circuit, the correct electrical connection must first be achieved. The existing technology is only applicable to devices packaged in DIP, SOP, LCC, QFN, etc. One-to-one correspondence, it is easy to realize the electrical connection of the back EMMI. For the EMMI on the back of the BGA/LGA device, because of the large number of IO ports, and the bonding wires are rewired through the substrate first, and then connected to the external solder joints (Figure 1), a simple one-to-one correspondence cannot be achieved. It is necessary to rely on the corresponding relationship between the bonding wire and the external solder joint provided by the device design manufacturer to determine the electrical connection relationship of the back EMMI. For the user of the device, it is generally impossible to obtain such a corresponding relationship, which brings great limitations to the failure analysis of the BGA/LGA device.

In order to solve the problem in the above-mentioned background technology and realize the technical purpose of the present invention, the technical solution adopted in the present invention is a kind of BGA/LGA device backside EMMI failure analysis method, and this method comprises the following steps:

The first step is to conduct a volt-ampere (IV) characteristic test on the BGA/LGA device, obtain the volt-ampere characteristic curve of the failed pin, and determine the position of the failed pin in the external solder joint.

The second step is to grind off the external solder joints of the failed BGA/LGA device to expose the pads and through holes. According to the data sheet of the BGA/LGA device, determine the positions of the pads and through holes of the failed pins, and Take pictures of the layout;

The third step is to grind the substrate of the failed pin of the BGA/LGA device to expose the copper clad layer, and determine the position of the through hole of the failed pin on the copper clad layer;

The fourth step is to repeat the third step of substrate grinding, and perform layer-by-layer grinding until the last layer of metal wiring on the substrate is exposed, and confirm the position of the through hole of the failed pin;

The fifth step is to conduct a volt-ampere curve test on the metal wiring where the via hole of the failed pin is located to obtain a volt-ampere curve, and compare and confirm it with the volt-ampere characteristic curve obtained in the first step; If the obtained volt-ampere characteristic curves are the same or similar (there is a change in resistance value due to the removal of the substrate), proceed to the sixth step. If they are not the same, there are two possibilities: 1) The failure pin is located incorrectly, and you need to compare the second step to On the substrate layout obtained in the fifth step, reconfirm the location of the failed pin; 2) The location of the failure is located on the substrate and not on the chip.

The sixth step is to take an X-ray photo of the BGA/LGA device, determine the position of the bonding wire connected to the metal wiring connected to the through hole of the failed pin, and record the position.

The seventh step is to grind and remove the last layer of metal wiring to expose the silicon substrate and the bonding wire head, and find the bonding wire position recorded in the sixth step;

The eighth step is to tie the probe to the binding wire end of the failed pin and the power or ground end to achieve correct power-on.

The ninth step is to carry out the back EMMI. The one-to-one correspondence between bonding wires and external solder joints is realized through the back EMMI, thereby providing accurate electrical connection to the back EMMI of the integrated circuit, and realizing the failure analysis of the back EMMI of the integrated circuit.

The technical effect that the present invention can reach is:

The existing EMMI technology on the back of integrated circuits is only applicable to devices packaged in DIP, SOP, LCC, QFN, etc. It can better obtain the back of the chip without damaging the lead frame, and provide electrical connection for the location of the failure point. For the back EMMI of BGA/LGA devices, the electrical connection relationship of the back EMMI can only be determined by relying on the corresponding relationship between the bonding wires and the external solder joints provided by the device design manufacturer. For device users, it is generally impossible to obtain such corresponding relationships, which brings great limitations to the failure analysis of BGA/LGA devices.

The invention can quickly and easily obtain the one-to-one correspondence between the BGA/LGA device bonding wire and the external solder joint, thereby providing accurate electrical connection for the EMMI on the back side of the BGA/LGA device circuit, and realizing the failure of the EMMI on the back side of the BGA/LGA device The analysis expands the applicability of IC backside EMMI failure analysis and reduces the limitations of IC backside EMMI.

Description of drawings

Hereinafter, some specific embodiments of the present invention will be described in detail by way of illustration and not limitation with reference to the accompanying drawings.

The same reference numerals in the drawings designate the same or similar parts or parts. Those skilled in the art should understand that these

The drawings are not necessarily drawn to scale. In the attached picture:

Figure 1 shows a vertical structure diagram of a BGA device.

Fig. 2 is the back side of the failed sample of the embodiment of the present invention.

Fig. 3 is the morphology of the backside of the failed sample of the embodiment of the present invention after grinding away the solder joints.

FIG. 4 is a copper clad layer of a failed sample substrate according to an embodiment of the present invention.

FIG. 5 is an X-ray photo of a failed sample substrate of an embodiment of the present invention.

FIG. 6 is an effect diagram of backside EMMI according to an embodiment of the present invention.

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

An EMMI failure analysis method for the back of a BGA/LGA device. The first step is to perform a volt-ampere (IV) characteristic test on the failed pin of the BGA/LGA device. The topography of the back of the device is shown in Figure 2.

The second step is to grind off the external solder joints of the failed BGA/LGA device to expose the pads and through holes. According to the data sheet of the device, determine the positions of the pads and through holes of the failed pins, as shown in Figure 3;

The third step is to grind the substrate to expose the copper clad layer, and determine the position of the through hole of the failed pin on the copper clad layer, as shown in Figure 4;

The fourth step, repeat the third step, and grind the substrate layer by layer until the last layer, exposing the metal line, see Figure 5;

The fifth step is to test the IV curve of the metal line where the via hole of the failed pin is located, and compare and confirm it with the IV curve obtained in the first step;

The sixth step is to take an X-ray photo of the device to determine the positional relationship between the bonding line of the failed pin and the metal line, as shown in Figure 5;

The seventh step is to grind the substrate to expose the silicon substrate and the bonding wire;

The eighth step is to tie the probe to the bond wire tip of the failed pin and the power or ground terminal to achieve correct power-up.

The ninth step is to carry out the back EMMI.

Claims (2)

1. A BGA/LGA device backside EMMI failure analysis method is characterized in that the method may further comprise the steps: The first step is to test the volt-ampere characteristics of the BGA/LGA device, obtain the volt-ampere characteristic curve of the failed pin, and determine the position of the failed pin in the external solder joint; The second step is to grind off the external solder joints of the failed BGA/LGA device to expose the pads and through holes. According to the data sheet of the BGA/LGA device, determine the positions of the pads and through holes of the failed pins, and Take pictures of the layout; The third step is to grind the substrate of the failed pin of the BGA/LGA device to expose the copper clad layer, and determine the position of the through hole of the failed pin on the copper clad layer; The fourth step is to repeat the third step of substrate grinding, and perform layer-by-layer grinding until the last layer of metal wiring on the substrate is exposed, and confirm the position of the through hole of the failed pin; The fifth step is to conduct a volt-ampere curve test on the metal wiring where the through hole of the failed pin is located to obtain a volt-ampere curve, and compare and confirm it with the volt-ampere characteristic curve obtained in the first step; The sixth step is to take an X-ray photo of the BGA/LGA device, determine the position of the bonding wire connected to the metal wiring connected to the through hole of the failed pin, and record the position; The seventh step is to grind and remove the last layer of metal wiring to expose the silicon substrate and the bonding wire head, and find the bonding wire position recorded in the sixth step; The eighth step is to tie the probe to the end of the binding wire of the failed pin and the power or ground end to achieve correct power-on; The ninth step is to carry out the back EMMI; through the back EMMI, the one-to-one correspondence between the bonding wire and the external solder joint is realized, so as to provide accurate electrical connection for the EMMI on the back of the integrated circuit, and realize the failure analysis of the back EMMI of the integrated circuit. 2. a kind of BGA/LGA device backside EMMI failure analysis method according to claim 1 is characterized in that, in the 5th step, the volt-ampere curve of the 5th step is identical or similar with the volt-ampere characteristic curve that the first step obtains Then go to the sixth step; if they are not the same, there are two possibilities: 1) the location of the failed pin is incorrect, and you need to compare the board layout obtained in steps 2 to 5 to reconfirm the location of the failed pin; 2) the location of the failed pin Located on the substrate and not on the chip;.

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