CN115902587A

CN115902587A - Chip testing method and device, electronic equipment and storage medium

Info

Publication number: CN115902587A
Application number: CN202211582074.1A
Authority: CN
Inventors: 廖道聪
Original assignee: Xi'an Ziguang Zhanrui Technology Co ltd
Current assignee: Xi'an Ziguang Zhanrui Technology Co ltd
Priority date: 2022-12-09
Filing date: 2022-12-09
Publication date: 2023-04-04

Abstract

The application provides a chip testing method, a chip testing device, electronic equipment and a storage medium, wherein after first current data when a chip executes a testing instruction are obtained by testing equipment, compensation parameters corresponding to a testing environment where the chip is located are determined, compensation processing is carried out on the first current data based on the compensation parameters to obtain second current data, and finally the chip is analyzed according to the second current data which is more accurate after repair to obtain a testing result. Therefore, when the test equipment tests the chip, the first current data are compensated through the compensation parameters, so that the influence of the test environment where the chip is located on the first current data is eliminated, and the actual current change condition of the chip can be reflected more accurately by the second current data obtained after compensation, so that the test equipment can test the chip more effectively according to the second current data.

Description

Chip testing method and device, electronic equipment and storage medium

Technical Field

The present disclosure relates to the field of chip testing technologies, and in particular, to a chip testing method and apparatus, an electronic device, and a storage medium.

Background

After the chip supplier designs the chip, the chip is tested by the test scheme, and after the chip passes the test, the chip is reproduced and provided for the user. For example, for chips in electronic devices such as mobile phones and tablet computers, after the chips need to be arranged inside the electronic devices, a tester simulates real operations of a user according to requirements of a test scheme to send an operation instruction to the chips, so that the chips obtain the operation instruction sent by the tester and execute the operation instruction. Meanwhile, in the process of executing the operation instruction by the chip, the tester also uses current acquisition equipment such as an ammeter to acquire the current data of the chip, so that after the chip executes all the operation instructions, the tester can perform subsequent processing such as power analysis on the chip according to the current data of the chip.

However, when the test environment where the chip is located changes, the current data of the chip collected by the current collection device changes, and even when a plurality of chips of the same model are tested respectively, a plurality of different current data also can be generated, so that the chip cannot be accurately tested. Therefore, how to overcome the influence of the test environment of the chip on the current data of the chip is a technical problem to be solved in the field.

Disclosure of Invention

The application provides a chip testing method and device, electronic equipment and a storage medium, which are used for solving the technical problem that the chip cannot be accurately tested due to the fact that the current data of the chip is influenced by the testing environment where the chip is located in the prior art.

A first aspect of the present application provides a method for testing a chip, including: acquiring first current data when a chip executes a test instruction; determining a compensation parameter corresponding to a test environment where a chip is located; the compensation parameters are used for representing the influence of the test environment on the current data; compensating the first current data based on the compensation parameters to obtain second current data; and carrying out power analysis on the chip according to the second current data to obtain a test result.

In an embodiment of the first aspect of the present application, determining a compensation parameter corresponding to a test environment in which a chip is located includes: determining at least one environmental factor of a test environment in which the chip is located; environmental factors include: the method comprises the steps of obtaining screen brightness of electronic equipment where a chip is located, volume of the electronic equipment, signal intensity of the electronic equipment, current value of equipment for obtaining first current data and standby condition of the electronic equipment; determining a compensation grade corresponding to each environmental factor in at least one environmental factor according to the mapping relation; the mapping relation comprises a plurality of environment factors and the corresponding relation between a plurality of environment factor grades and a plurality of compensation grades of each environment factor; a compensation parameter is determined based on a compensation level of at least one environmental factor.

In an embodiment of the first aspect of the present application, determining the compensation parameter according to the compensation level of the at least one environmental factor includes: and carrying out weighted summation on the compensation grade of at least one environmental factor to obtain a compensation parameter.

In an embodiment of the first aspect of the present application, determining the compensation parameter according to the compensation level of the at least one environmental factor includes: calculating the product of the compensation level of each environmental factor and the duration of the environmental factor; and weighting and summing the products of the compensation level and the duration of all the at least one environmental factor to obtain the compensation parameter.

In an embodiment of the first aspect of the present application, the method further includes: acquiring standard current data of a chip in a standard test environment; acquiring measurement current data of a chip under a plurality of measurement test environments; the plurality of measurement test environments comprise measurement test environments with at least one environmental factor respectively taking different environmental factor grades; and obtaining a mapping relation according to the standard current data and the plurality of measured current data.

In an embodiment of the first aspect of the present application, the method further includes: acquiring a mapping relation input by a tester; or when the testing environment where the chip is located is different from the standard testing environment, sending a mapping relation obtaining request to the server, and receiving the mapping relation sent by the server.

In an embodiment of the first aspect of the present application, the compensating the first current data based on the compensation parameter to obtain the second current data includes: and calculating the product of the first current data and the compensation parameter to obtain second current data.

A second aspect of the present application provides a device for testing a chip, which can be used to perform a method for testing a chip as provided in any one of the first aspects of the present application, the device comprising: the acquisition module is used for acquiring first current data when the chip executes the test instruction; the determining module is used for determining the compensation parameters corresponding to the testing environment where the chip is located; the compensation parameters are used for representing the influence of the test environment on the current data; the compensation module is used for compensating the first current data based on the compensation parameters to obtain second current data; and the analysis module is used for carrying out power analysis on the chip according to the second current data to obtain a test result.

A third aspect of the present application provides an electronic device comprising: a processor and a memory communicatively coupled; wherein the memory has stored therein a computer program which, when executed by the processor, causes the processor to carry out the method according to any one of the first aspect of the present application.

A fourth aspect of the present application provides a storage medium storing computer instructions for implementing a method as in any one of the first aspect of the present application when executed.

The application provides a chip testing method, a chip testing device, electronic equipment and a storage medium, wherein after first current data of a chip executing a testing instruction are obtained by testing equipment, compensation parameters corresponding to a testing environment where the chip is located are determined, the first current data are compensated based on the compensation parameters to obtain second current data, and finally the chip is analyzed according to the second current data which are more accurate after repair to obtain a testing result. Therefore, when the test equipment tests the chip, the compensation of the compensation parameters on the first current data eliminates the influence of the test environment where the chip is located on the first current data, and the second current data obtained after compensation can more accurately reflect the actual current change condition of the chip, so that the test equipment can more effectively test the chip according to the second current data.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the description below are only some embodiments of the present application, and for those skilled in the art, other drawings may be obtained according to these drawings without inventive labor.

FIG. 1 is a schematic diagram of an application scenario of the present application;

FIG. 2 is a schematic diagram of current data for a chip;

FIG. 3 is a schematic flowchart of an embodiment of a chip testing method provided in the present application;

FIG. 4 is a schematic flow chart illustrating an embodiment of determining compensation parameters provided herein;

FIG. 5 is a schematic diagram of a chip testing apparatus provided in the present application;

fig. 6 is a schematic structural diagram of an embodiment of an electronic device provided in the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application and in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic diagram of an application scenario of the present application. In one scenario, as shown in fig. 1, a supplier of the chip 30 produces the chip 30 and sets the chip 30 in the electronic device 40 through step (1), a battery in the electronic device 40 is used to provide a rated operating voltage for the chip 30, and the current provided by the battery to the chip 30 is related to an operation instruction executed by the chip 30. In order to determine the power consumption of the chip 30 in the electronic device 40, the tester 10 needs to test the chip 30 in a certain test scheme through step (2), determine parameters such as current when the chip 30 executes an operation instruction in the electronic device 40, and further determine the power consumption of the chip 30 and the electronic device 40 where the chip is located. The electronic device 40 may be a mobile phone, a tablet computer, or the like.

In one scenario, a tester 20 issues an operation instruction to the chip 30 of the electronic device 40 according to a requirement of a test scheme corresponding to the chip 30 by a user of the analog electronic device 40. The operation instruction includes an operation instruction to light a screen of the electronic apparatus 40, open an application in the electronic apparatus 40, set the electronic apparatus 40, and the like. After receiving the operation instruction, the chip 30 may execute the operation instruction sent by the tester.

Meanwhile, in the process of executing the operation instruction by the chip 30, the tester 10 may further use the test equipment 20 to acquire the working parameters, such as the current data of the chip 30, through the step (3). For example, fig. 2 is a schematic diagram of current data of a chip, in which the horizontal axis is a time axis and the vertical axis is an intensity value of current as shown in fig. 2, and each point on the curve of the current data is used to indicate the intensity value of current of the chip 30 at the time corresponding to the horizontal axis of the chip. It can be seen that at times t1, t2, \8230;, t10, during the entire time period, chip 30 receives and executes an operation command at each time, and the current intensity value of chip 30 changes to D1 at these times. At other times, the current intensity value of the chip 30 is maintained around D5.

After the chip 30 executes all the operation instructions corresponding to the test scheme, the test equipment 20 also acquires the current data of the chip 30 when all the operation instructions are executed within the time corresponding to the test scheme. Then, the test device 20 or a tester can perform power analysis and other processing on the chip 30 according to the collected current data of the chip 30 to obtain a test result. Further, it can be determined whether the chip 30 can implement the related function in the electronic device 40 according to the test result, and further adjusting and processing the chip 30 and the electronic device 40 where the chip is located according to the test result.

In one scenario, the testing device 20 may be any electronic device with related data processing capability, such as a computer, a server, a workstation, and the like, and the testing device 20 may collect current data when the chip 30 executes an operation instruction through a current collecting device, such as a connected ammeter. The current data includes the intensity value of the current and the like. It is understood that when the battery in the electronic device 40 provides voltage to the chip 30, the current between the battery and the chip 30 varies according to the operation instruction executed by the chip 30. For example, when the chip 30 executes an operation instruction such as lighting a screen, the current required by the chip 30 is large, so that the intensity value of the current in the current data in the time period in which the chip 30 executes the operation instruction is large, the intensity value may reach D1 shown in fig. 2, and the change is obvious; when the chip 30 executes an operation instruction such as screen-off, the current required by the chip 30 is small, so that the intensity value of the current in the current data in the time period in which the chip 30 executes the operation instruction is small, the intensity value can only reach D3 shown in fig. 2, and the change of the intensity value is less obvious compared with D1.

However, when testing the chip 30 in the scenario shown in fig. 1, it is necessary to perform related settings on the electronic device 40 and the testing device 20 where the chip 30 is located, so as to ensure that the tester 10 sends a testing instruction to the chip 30 after the chip 30 is in the standard testing environment. The standard test environment includes a standard screen brightness, a standard volume, a standard signal strength, a current value of the test equipment 20, etc. of the electronic device 40. When the test environment in which the chip 30 is located changes, the current data of the chip 30 collected by the test apparatus 20 may change. For example, the current data of the chip 30 collected under the standard test environment is shown in fig. 2, and when the test command is executed at time t1-t5, the intensity value in the current data changes to be close to D1. If the chip 30 is not under a standard test environment, for example, if the power consumption of the electronic device 40 is low compared to the standard test environment, the variation of the intensity values at these times in the current data of the chip 30 will be around D3 and to a lesser extent compared to D1.

Therefore, when the chip 30 is in a non-standard environment, the current data of the chip 30 collected by the testing apparatus 20 includes a current data error caused by an error between an actual testing environment and a standard testing environment. Even when a plurality of chips 30 of the same model are tested in different test environments, a plurality of different current data may appear on the plurality of chips 30. It can be understood that the test environment may cause the current data of the chip 30 to vary, and when the current data of the chip 30 collected by the test device 20 is not accurate, the test device 20 cannot accurately perform the power analysis on the chip 30 according to the inaccurate current data to obtain the test result, thereby reducing the effectiveness of testing the chip 30.

Based on this, aiming at the technical problems that the power analysis cannot be accurately performed on the chip according to the current data in the prior art, and the effectiveness of testing the chip is low, the application provides a chip testing method, after the testing device 20 obtains the first current data when the chip 30 executes the test instruction, the compensation parameter corresponding to the test environment where the chip 30 is currently located is also determined, the compensation processing is performed on the first current data based on the compensation parameter to obtain the second current data, and finally the chip is analyzed according to the more accurate second current data after the repair to obtain the test result. Therefore, when the test device 20 provided by this embodiment tests the chip 30, the compensation performed on the first current data by the compensation parameter eliminates the influence of the test environment where the chip 30 is located on the first current data, and the second current data obtained after the compensation can more accurately reflect the actual current change condition of the chip 30, so that the test device 20 can more effectively test the chip 30 according to the second current data. The technical solution of the present application will be described in detail below with specific examples. These several specific embodiments may be combined with each other below, and details of the same or similar concepts or processes may not be repeated in some embodiments.

Fig. 3 is a flowchart illustrating an embodiment of a chip testing method provided in the present application, where the chip testing method shown in fig. 3 can be applied to the scenario shown in fig. 1 and executed by the testing apparatus 20. Specifically, the method for testing the chip shown in fig. 3 includes:

s101: the test apparatus 20 acquires first current data when the chip 30 executes a test instruction.

Specifically, the tester 10 may send an operation instruction to the chip 30 according to a test scheme corresponding to the chip 30 when testing the chip 30, for example, the operation instruction may be a screen lighting instruction, and in a preset time period, the operator continuously clicks the display screen of the electronic device 40 multiple times and each time clicks a certain time interval, so that the chip 30 continuously receives the operation instruction for lighting the screen multiple times in the preset time period, and executes the operation instruction for lighting the screen. Alternatively, the operation instruction may be a homepage return instruction, and the operator presses the display screen of the electronic device 40 for a predetermined time period, so that the chip 30 receives the operation instruction of homepage return in the predetermined time period, and executes the operation instruction of homepage return.

S102: the test equipment 20 determines the compensation parameters corresponding to the test environment in which the chip 30 is located.

In particular, the compensation parameters are used to characterize the effect of the test environment on the current data of the chip 30. In this embodiment, the compensation parameter is specifically used to characterize the effect of the test environment on the first current data.

In an embodiment, fig. 4 is a schematic flowchart of an embodiment of determining a compensation parameter provided in the present application, and fig. 4 shows a specific implementation manner of determining the compensation parameter by the testing device 20 in fig. 3. As shown in fig. 4, the determination of the compensation parameter by the test device 20 includes:

s1021: and determining a plurality of environmental factors of the testing environment of the chip. Wherein the plurality of environmental factors include: the screen brightness of the electronic device 40 where the chip 30 is located, the volume of the electronic device 40 where the chip 30 is located, the signal strength of the electronic device 40 where the chip 30 is located, the current value of the device obtaining the first current data, the standby condition of the electronic device where the chip 30 is located, and the like.

S1022: and determining the compensation level corresponding to each environmental factor in the plurality of environmental factors according to the mapping relation. The mapping relation comprises a plurality of environment factors and the corresponding relation between a plurality of environment factor grades and a plurality of compensation grades of each environment factor.

In one embodiment, the mapping relationships provided herein may be represented by tables 1-5 below.

TABLE 1

The environmental factors shown in table 1 are screen brightness of the electronic device 40 where the chip 30 is located, and the mapping relationship includes N

environmental factor levels

1 and 2 \8230, N of the environmental factors, and a corresponding relationship between each environmental factor level and the compensation level a1 and a2 \8230, aN.

TABLE 2

The environmental factors shown in table 2 are the sound volume of the electronic device 40 where the chip 30 is located, and the mapping relationship includes M

environmental factor levels

1, 2 \8230, M of the environmental factors, and the corresponding relationship between each environmental factor level and the compensation levels b1, b2 \8230, bM.

TABLE 3

The environmental factors shown in table 3 are signal strengths of the electronic device 40 where the chip 30 is located, and the mapping relationship includes P

environmental factor levels

1, 2 \8230, 8230303030ccn of the environmental factors, and a corresponding relationship between each environmental factor level and the compensation levels c1, c2 \8230ccn.

TABLE 4

The environmental factors shown in table 4 are current values of the test equipment for acquiring the first current data, that is, self differences of the measuring instruments such as the ammeter, and the mapping relationship includes P environmental factor levels of a plurality of the environmental factors: low current compensation, medium current compensation and high current compensation, and the corresponding relationship of each environmental factor level to the compensation levels d1, d2 and d 3.

TABLE 5

As shown in table 5, the environmental factors are standby conditions of the electronic device 40 where the chip 30 is located, that is, standby differences of the electronic device 40, and the mapping relationship includes a plurality of P environmental factor levels of the environmental factors: off-screen standby compensation, off-screen use compensation and on-screen standby compensation, and the correspondence of each environmental factor level to the compensation levels e1, e2 and e3.

With reference to tables 1 to 5, assuming that the environmental factor level of the screen brightness is 1 in the test environment where the chip is located, the compensation level corresponding to the environmental factor of the screen brightness determined according to table 1 is a1; if the environmental factor level of the volume is 2, the compensation level corresponding to the environmental factor of the volume determined according to the table 2 is b2; if the environmental factor level of the signal strength is 3, the compensation level corresponding to the environmental factor of the signal strength determined according to the table 3 is c3; if the environmental factor grade of the test equipment is low current compensation, determining the compensation grade corresponding to the environmental factor of the test equipment according to the table 4 as d1; and if the environmental factor grade of the electronic equipment is bright screen standby compensation, determining the compensation grade corresponding to the environmental factor of the electronic equipment as e3 according to the table 5.

S1023: the test device 20 determines the compensation parameters of the test environment in which the chip is located according to the plurality of compensation levels respectively corresponding to the plurality of environmental factors determined in S1022. Thereby more effectively measuring the influence of each environmental factor on the current data.

In an embodiment, the testing device 20 may perform a weighted summation of the compensation levels corresponding to all the environmental factors, for example, the compensation parameter K is obtained by the formula K = a1+ B1+ C3+ D1+ E3. Wherein, a, B, C, D, E are weights corresponding to a plurality of environmental factors, respectively, and the weights may be set in advance, or may be designated by the tester 10 according to different testing environments. In one embodiment, the sum of a, B, C, D, and E may be 1. In a special implementation, a, B, C, D and E may all be 1.

In another embodiment, the test device 20 may calculate the product of the compensation level and the duration time of each environmental factor and weight-sum the products of the compensation levels and the duration times of all of the plurality of environmental factors. The compensation parameter K is obtained, for example, by the formula K = t1 × a1+ t2 × b1+ t3 × c3+ t4 × d1+ t5 × e3. Wherein t1, t2, t3, t4 and t5 are the durations of the plurality of environmental factors, respectively, and the unit is second(s). In an embodiment, the test equipment 20 may further jointly obtain the compensation parameter K according to the weight and the duration corresponding to the plurality of environmental factors, for example, the compensation parameter K is obtained by using a formula K = a × t1 × a1+ B × t2 × B1+ C × t3 × C3+ D × t4 + D1+ E × t5 × E3.

S103: the test device 20 performs compensation processing on the first current data acquired in S101 based on the compensation parameter determined in S102, to obtain second current data.

Specifically, after the test device 20 determines the compensation parameter, the compensation processing may be performed on the first current data according to the compensation parameter to compensate for an error of the current data caused by a difference in the test environment where the chip 30 is located in the first current data, so as to obtain the second current data. It will be appreciated that errors in the current data caused by the test environment in which the chip 30 is located have been eliminated in the second current data.

In one embodiment, the test equipment 20 may specifically multiply the first current data by the compensation parameter K to obtain the second current data.

S104: the test device 20 performs power analysis on the chip according to the second current data obtained in S103, so as to obtain a test result.

Specifically, since the second current data is obtained by the test device after compensating the first current data, when the second current data eliminates the influence on the current data due to the difference of the test environment where the chip 30 is located, the second current data can more accurately reflect the actual current change condition of the chip 30, so that the test device 20 can more effectively test the chip 30 according to the second current data.

In the embodiment of the present application, the test performed by the test device 20 after obtaining the second current data is not limited, for example, the test device 20 may determine, according to the second current data, a test result such as power when the chip 30 executes at least one test instruction within a preset time period, and further perform power analysis and the like on the chip 30 and the electronic device 40 where the chip is located according to power variation of the chip 30.

In an embodiment, the mapping relationship that the test device 20 repairs the first current data in the embodiment of the present application may be stored in the test device 20 in advance, or may be input by the tester 10, and the test device 20 receives the mapping relationship input by the tester 10 and then stores the mapping relationship. Or, when the test device 20 tests the chip 30 and determines that the test environment in which the chip 30 is located is different from the standard test environment, the mapping relationship obtaining request is sent to the server through the network, so that the mapping relationship sent by the server is received and stored, and the mapping relationship can be deleted after use, so that the occupation of the storage space of the test device 20 is reduced, and the mapping relationship on the server can be updated and modified in real time, so that the timeliness of the mapping relationship is improved. The server may be provided by the supplier of the chip 30 or may be provided by the tester 10.

In an embodiment, the present application further provides a method for determining a mapping relationship, where the method may be executed by the test device 20 or other devices, and the application does not limit the execution subject for obtaining the mapping relationship. Specifically, the method for obtaining the mapping relationship includes: the method includes the steps of firstly obtaining standard current data of a chip 30 in a standard test environment, and then sequentially modifying the environmental factor grade of each environmental factor in the standard test environment according to the environmental factors and the environmental factor grades provided in tables shown in tables 1 to 5 to obtain a plurality of different measurement test environments. Then, the measurement chip 30 measures the current data under a plurality of measurement test environments, and obtains a mapping relationship according to the standard data and the current data under each measurement test environment.

Illustratively, it is assumed that the environmental factor levels of the plurality of environmental factors of the standard test environment are respectively: the environmental factor grade of the screen brightness is 2; the environmental factor level of the volume is 2; the environmental factor level of signal strength is 2; the environmental factor grade of the test equipment is medium current compensation; the environmental factor level of the electronic device is compensated for the use of the screen being turned off. And under the standard test environment, standard current data when the chip executes at least one test instruction corresponding to the test scheme can be measured. Subsequently, the environmental factor grade of the screen brightness in the standard test environment is modified to be 1, and the environmental factor grades of other environmental factors are unchanged, so that a measurement current data 1 can be obtained; the environmental factor grade of the screen brightness in the standard test environment is modified to be 3, the environmental factor grades of other environmental factors are unchanged, and one measurement current data 2 \8230, 8230can be obtained, and so on, 1 environmental factor grade of one environmental factor is modified each time. Subsequently, the value of the compensation grade a1 in the table 1 can be obtained according to the ratio of the measured current data 1 to the standard current data, the value of the compensation grade a3 in the table 1 can be obtained according to the ratio of the measured current data 1 to the standard current data, 8230is obtained, and by analogy, the compensation grade of each environmental factor in the tables 1 to 5 under each environmental factor grade can be obtained. It is understood that the compensation level a2 in table 1 has a value of 1, the compensation level b2 in table 2 has a value of 1, the compensation level c2 in table 3 has a value of 1, the compensation level d2 in table 4 has a value of 1, and the compensation level e2 in table 5 has a value of 1, corresponding to the standard test environment.

In the foregoing embodiments, methods and steps executed by the test equipment provided in the embodiments of the present application are described, and in order to implement each function in the method provided in the embodiments of the present application, the test equipment serving as an execution subject may include a hardware structure and/or a software module, and implement each function in the form of a hardware structure, a software module, or a hardware structure plus a software module. Whether any of the above functions is implemented as a hardware structure, a software module, or a combination of a hardware structure and a software module depends upon the particular application and design constraints imposed on the technical solution.

For example, fig. 5 is a schematic diagram of a chip testing apparatus provided in the present application, where the chip testing apparatus 1000 shown in fig. 5 may be used to perform a chip testing method shown in fig. 3, and the chip testing apparatus 1000 shown in fig. 5 includes an obtaining module 1001, a determining module 1002, a compensating module 1003, and an analyzing module 1004. The obtaining module 1001 is configured to obtain first current data when a chip executes a test instruction; the determining module 1002 is configured to determine a compensation parameter corresponding to a test environment where a chip is located; the compensation parameters are used for representing the influence of the test environment on the current data; the compensation module 1003 is configured to compensate the first current data based on the compensation parameter to obtain second current data; the analysis module 1004 is configured to perform power analysis on the chip according to the second current data to obtain a test result.

In an embodiment, the determining module 1002 is specifically configured to determine at least one environmental factor of a test environment in which the chip is located; environmental factors include: the method comprises the steps of obtaining screen brightness of electronic equipment where a chip is located, volume of the electronic equipment, signal intensity of the electronic equipment, current value of equipment for obtaining first current data and standby condition of the electronic equipment; determining a compensation grade corresponding to each environmental factor in at least one environmental factor according to the mapping relation; the mapping relation comprises a plurality of environment factors and the corresponding relation between a plurality of environment factor grades and a plurality of compensation grades of each environment factor; a compensation parameter is determined based on a compensation level of at least one environmental factor.

In an embodiment, the determining module 1002 is specifically configured to perform weighted summation on the compensation levels of at least one environmental factor to obtain a compensation parameter.

In one embodiment, the determining module 1002 is specifically configured to calculate a product of the compensation level of each environmental factor and the duration of the environmental factor; and weighting and summing the products of the compensation level and the duration of all the at least one environmental factor to obtain the compensation parameter.

In an embodiment, the testing apparatus 1000 of the chip shown in fig. 5 further includes a mapping relation determining module, configured to obtain standard current data of the chip in a standard testing environment; acquiring measurement current data of a chip under a plurality of measurement test environments; the plurality of measurement test environments comprise measurement test environments with at least one environmental factor respectively taking different environmental factor grades; obtaining a mapping relation according to the standard current data and the plurality of measured current data

In one embodiment, the mapping relation determining module is further configured to obtain a mapping relation input by a tester; or when the testing environment where the chip is located is different from the standard testing environment, sending a mapping relation obtaining request to the server, and receiving the mapping relation sent by the server.

In one embodiment, the compensation module 1003 is specifically configured to calculate a product of the first current data and the compensation parameter to obtain the second current data.

The implementation manner and principle of the chip testing apparatus provided in the embodiment of the present application may refer to the description in the chip testing method, and are not repeated.

It should be noted that the division of each module of the above apparatus is only a logical division, and all or part of the actual implementation may be integrated into one physical entity or may be physically separated. And these modules can be realized in the form of software called by processing element; or may be implemented entirely in hardware; and part of the modules can be realized in the form of calling software by the processing element, and part of the modules can be realized in the form of hardware. The processing element may be a separate processing element, or may be integrated into a chip of the apparatus, or may be stored in the memory of the apparatus in the form of program code, and a processing element of the apparatus may call and execute the functions of the above determination module. Other modules are implemented similarly. In addition, all or part of the modules can be integrated together or can be independently realized. The processing element described herein may be an integrated circuit having signal processing capabilities. In implementation, each step of the above method or each module above may be implemented by an integrated logic circuit of hardware in a processor element or an instruction in the form of software.

For example, the above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more Digital Signal Processors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs), etc. For another example, when some of the above modules are implemented in the form of a processing element calling program code, the processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. As another example, these modules may be integrated together, implemented in the form of a system-on-a-chip (SOC).

In the above embodiments, the steps performed by the test equipment may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The procedures or functions described in accordance with the embodiments of the application are all or partially generated when the computer program instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that includes one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), among others.

For example, fig. 6 is a schematic structural diagram of an embodiment of an electronic device provided in the present application, and an electronic device 2000 shown in fig. 6 includes a processor 2001 and a memory 2002. The processor 2001 is communicatively coupled to the memory 2002. Among other things, the memory 2002 stores a computer program. When the processor 2001 executes the computer program, the processor 2001 may perform the steps of the method of testing the chip as any one of the previous embodiments of the present application performed by the test apparatus. In one embodiment, the electronic device 2000 further includes a communication interface 2003 operable to obtain first current data, and the like.

The present application also provides a computer readable storage medium storing computer instructions which, when executed, are operable to perform the steps of the method for testing a chip as performed by the testing device in any of the previous embodiments of the present application.

The embodiment of the present application further provides a chip for executing the instruction, where the chip is used to execute the steps of the method for testing the chip executed by the testing device according to any one of the foregoing embodiments of the present application.

Embodiments of the present application further provide a computer program product, where the computer program product includes a computer program, where the computer program is stored in a storage medium, and the computer program can be read from the storage medium by at least one processor, and the at least one processor can implement the steps of the method for testing a chip, which is executed by a testing device according to any one of the foregoing embodiments of the present application, when executing the computer program.

Those of ordinary skill in the art will understand that: all or a portion of the steps for implementing the above embodiments may be performed by hardware associated with program instructions. The foregoing program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; the storage medium includes various media that can store program codes, such as ROM, magnetic disk, or optical disk.

Those of ordinary skill in the art will understand that: for convenience of describing the technical solution of the present application, the functional modules in the embodiments of the present application are separately described, and circuit devices in the respective modules may partially or completely overlap, which is not intended to limit the scope of the present application.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and these modifications or substitutions do not depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for testing a chip, comprising:

acquiring first current data when the chip executes a test instruction;

determining a compensation parameter corresponding to a test environment where the chip is located; the compensation parameter is used for representing the influence of the test environment on the current data;

compensating the first current data based on the compensation parameter to obtain second current data;

and carrying out power analysis on the chip according to the second current data to obtain a test result.

2. The method of claim 1, wherein the determining the compensation parameter corresponding to the test environment in which the chip is located comprises:

determining a plurality of environmental factors of a test environment where the chip is located; the plurality of environmental factors include: the screen brightness of the electronic equipment where the chip is located, the volume of the electronic equipment, the signal intensity of the electronic equipment, the current value of the equipment for obtaining the first current data and the standby condition of the electronic equipment;

determining a compensation grade corresponding to each environmental factor in the plurality of environmental factors according to the mapping relation; the mapping relation comprises a plurality of environment factors and the corresponding relation between a plurality of environment factor grades and a plurality of compensation grades of each environment factor;

and determining the compensation parameters according to the compensation levels of the plurality of environmental factors.

3. The method of claim 2, wherein determining the compensation parameter based on the compensation levels for the plurality of environmental factors comprises:

and carrying out weighted summation on the compensation grades of the plurality of environmental factors to obtain the compensation parameter.

4. The method of claim 2, wherein determining the compensation parameter based on the compensation levels for the plurality of environmental factors comprises:

calculating a product of a compensation level of each of the environmental factors and a duration of the environmental factor;

and weighting and summing the products of the compensation grades and the duration of all the plurality of environmental factors to obtain the compensation parameter.

5. The method according to claim 3 or 4, wherein the mapping relationship is determined by:

acquiring standard current data of the chip in a standard test environment;

acquiring measurement current data of the chip under a plurality of measurement test environments; the plurality of measurement test environments comprise measurement test environments with the plurality of environmental factors respectively taking different environmental factor grades;

and obtaining the mapping relation according to the standard current data and the plurality of measured current data.

6. The method of claim 5, further comprising:

acquiring the mapping relation input by a tester;

or when the testing environment where the chip is located is determined to be different from the standard testing environment, sending a mapping relation obtaining request to a server, and receiving the mapping relation sent by the server.

7. The method of any of claims 1-6, wherein compensating the first current data based on the compensation parameter to obtain second current data comprises:

and calculating the product of the first current data and the compensation parameter to obtain the second current data.

8. An apparatus for testing a chip, comprising:

the acquisition module is used for acquiring first current data when the chip executes a test instruction;

the determining module is used for determining the compensation parameters corresponding to the test environment where the chip is located; the compensation parameter is used for representing the influence of the test environment on the current data;

the compensation module is used for compensating the first current data based on the compensation parameters to obtain second current data;

and the analysis module is used for carrying out power analysis on the chip according to the second current data to obtain a test result.

9. An electronic device, comprising: a processor and a memory communicatively coupled; wherein the memory has stored therein a computer program which, when executed by the processor, performs the method of any one of claims 1-7.

10. A storage medium having stored thereon computer instructions for implementing the method of any one of claims 1-7 when executed.