CN115882712A - Enabling circuit of power supply chip, power supply chip and control method - Google Patents
Enabling circuit of power supply chip, power supply chip and control method Download PDFInfo
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Abstract
The invention discloses an enabling circuit of a power supply chip, the power supply chip and a control method, wherein the enabling circuit is used for controlling the power supply chip to be started and shut down and comprises a micro constant current source circuit, a voltage-stabilized power supply module and an accelerated shutdown module; the output end of the micro constant current source circuit is connected with the stabilized voltage supply module, and the stabilized voltage supply module is connected with the accelerated shutdown module; the micro constant current source circuit is used for generating a first current according to an enable signal input from the outside, and the first current controls the voltage-stabilized power supply module to generate a stabilized voltage and a second current; the stabilized voltage is output by the stabilized voltage supply module and used for supplying power to a power circuit of the power supply chip; the accelerated shutdown module is used for generating a state signal for controlling the external power supply state of the power supply chip according to the stabilized voltage and the second current, the power supply state comprises accelerated shutdown power supply and power supply maintenance, and the enabling circuit can reduce the circuit complexity and power consumption of the EN module and shorten the startup and shutdown time.
Description
Technical Field
The invention relates to the field of power supply circuits, in particular to an enabling circuit of a power supply chip, the power supply chip and a control method.
Background
For a chip, an enable pin (typically EN) is usually designed to enable the chip to operate or not operate. Specifically, the EN is generally used to implement the power on/off function of the control chip.
When the power supply chip works normally, the power supply chip can be started and shut down by the EN pin of the control chip. The user controls the EN pin through the high-frequency signal, and the purpose of adjusting the output voltage is realized by controlling the state of the chip to be switched between the starting state and the shutdown state. When EN is higher (lower) than a certain voltage, the chip works normally; when EN is lower than (higher than) a certain voltage, the voltage stabilizing module is closed, and other modules (such as an error amplifier, a comparator, a latch, a thermal shutdown, an oscillator generator and a driver) which use the voltage stabilizing module to provide power are correspondingly closed, so that the purpose of closing the chip is achieved, and power consumption is reduced and energy is saved.
As shown in fig. 1, in order to improve the reliability of a power chip, an existing EN shutdown control circuit has the problems of complex circuit, large power consumption, and long time (long delay time), and an existing EN shutdown control circuit usually has three signal output ends, and when an EN high level exists, an output a signal of an EN module output end a is a high level, so that a power tube of the chip is rapidly turned off, and after the power tube is forcibly turned off, the chip does not output voltage. The output ends B and C of the EN control circuit generate signals B and C (the signals B and C are both high level, the high level of the default signal is generally effective) after being delayed by the delay circuit, the high level signal B finishes discharging residual charges in a compensation capacitor in the error amplifier, and the signal C is responsible for quickly switching off power supply of an internal circuit of the chip; the three signals control the internal module of the chip in sequence, and the chip is not abnormal when EN is shut down. As shown in fig. 2, when the power chip is turned on, EN is at a low level, all the three signal output terminals are at a low level, a power supply module of an internal circuit of the chip starts to work and supplies power to an error amplifier circuit, a logic control circuit and other circuits, the error amplifier is powered on, the voltage of a compensation capacitor in the error amplifier starts to be established from 0V, and the chip normally works. Because the circuit control logic is relatively complex and has more devices, the power consumption and the time required by shutdown are long.
In order to prevent chip failure caused by abnormal logic of power-on and power-off time sequences or abnormal logic circuits in a chip in the process of startup and shutdown, an EN module of a complex logic circuit is arranged in a conventional chip, and the abnormal chip is prevented by controlling the power-on and power-off time sequences; the problems of long time consumption, slow response speed and large power consumption in startup and shutdown are caused.
Disclosure of Invention
The invention provides an enabling circuit of a power chip, the power chip and a control method, aiming at reducing the complexity and power consumption of an enabling module circuit and shortening the on-off time.
In order to achieve the above object, in a first aspect, the present invention provides an enabling circuit of a power chip, the enabling circuit is used for controlling a power chip to be turned on and turned off, and includes a micro constant current source circuit, a regulated power supply module and an accelerated turn-off module;
the output end of the micro constant current source circuit is connected with the stabilized voltage power supply module, and the stabilized voltage power supply module is connected with the accelerated shutdown module; the micro constant current source circuit is used for generating a first current according to an enable signal input from the outside, and the first current controls the voltage-stabilized power supply module to generate a stabilized voltage and a second current; the stabilized voltage power supply module outputs the stabilized voltage to be used for supplying power to a power circuit of the power supply chip; the accelerated shutdown module is used for generating a state signal for controlling the external power supply state of the power supply chip according to the stabilized voltage and the second current, wherein the power supply state comprises accelerated power supply disconnection and power supply maintenance.
Optionally, the power supply circuit includes an upper power tube, the upper power tube is used for controlling an external power supply state of the power supply chip, and the state signal generated at the output end of the accelerated shutdown module is used for controlling the upper power tube to be accelerated to be shut down or to keep a normal working state.
Optionally, the micro constant current source circuit includes a current mirror circuit and a current source circuit, the current mirror circuit is connected to the current source circuit, the current mirror circuit is configured to output a control voltage according to a voltage value of the enable signal, and the control voltage controls a current value of a first current of the current source circuit.
Optionally, the current mirror circuit includes 10 triodes, 3 resistors and a transistor, wherein the first to third triodes, the seventh to eighth triodes are PNP-type triodes, the fourth to sixth triodes are NPN-type triodes, and the transistor is an N-channel junction field effect transistor;
emitting electrodes of the first triode, the second triode, the seventh triode and the eighth triode are all connected with a power supply VCC, and bases of the first triode, the second triode, the seventh triode and the eighth triode are all connected together and connected with a collector electrode of the first triode;
the collector electrode of the first triode is connected with the drain electrode of the transistor, the grid electrode of the transistor is grounded, and the source electrode of the transistor is connected with one end of the first resistor; the other end of the first resistor is respectively connected with an emitting electrode of a third triode and a collecting electrode of a fourth triode, the collecting electrode of the fourth triode is connected with a base electrode, the emitting electrode of the fourth triode is connected with a base electrode of a fifth triode, the collecting electrode of the third triode is connected with the base electrode of the third triode, the connection part is connected with an enabling signal, and the enabling signal is used for controlling the voltage of the connection part of the third triode and the fourth triode;
the collector of the fifth triode is connected with the collector of the second triode, the junction is connected with the base of the sixth triode, the emitter of the sixth triode is grounded, the collector of the sixth triode is connected with the collector of the seventh triode, the junction is connected with the collector of the ninth triode, the base of the ninth triode is connected with the base of the thirteenth polar tube and the collector of the thirteenth polar tube, the emitter of the ninth triode and the emitter of the thirteenth polar tube are respectively connected with one end of the second resistor and one end of the third resistor, and the other ends of the second resistor and the third resistor are grounded to form a mirror image constant current source circuit.
Optionally, the current source circuit (212) is connected to a current mirror circuit for generating a first current, and the current source circuit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fifteenth transistor; the twelfth to thirteenth triodes are PNP type triodes, and the eleventh and fifteenth triodes are NPN type triodes;
the base electrode of the eleventh triode is connected with the joint of the seventh triode and the ninth triode, the collector electrode of the eleventh triode is connected with the base electrodes of the twelfth triode and the thirteenth triode, and the emitter electrode of the eleventh triode and the collector electrode of the twelfth triode are both connected with one end of the third resistor;
and the emitting electrodes of the twelfth triode and the thirteenth triode are connected with a power supply VCC, the collecting electrode of the thirteenth triode is connected with the collecting electrode and the base electrode of the fifteenth triode, the emitting electrode of the fifteenth triode is grounded, and the base electrode of the fifteenth triode is used for generating a first current.
Optionally, the voltage-stabilized power supply module includes a current source input circuit and a vdd voltage-stabilized power supply circuit, where the current source input circuit is configured to input a first current, and the vdd voltage-stabilized power supply circuit generates a stabilized voltage and a second current according to the first current;
the current source input circuit includes: a fourteenth transistor and a sixteenth transistor. The base electrode of the sixteenth triode is connected with the base electrode of the fifteenth triode and the current input end of the vdd voltage-stabilized source circuit, the collector electrode of the sixteenth triode is connected with the collector electrode of the fourteenth triode and the base electrode of the fourteenth triode, the emitter electrode of the sixteenth triode is grounded, and the emitter electrode of the fourteenth triode is connected with a power supply VCC;
the fourteenth triode is a PNP triode and the sixteenth triode is an NPN triode.
Optionally, the shutdown acceleration module includes a charging current control module and a delay output module, where the delay output module includes a capacitor; the input end of the charging current control module is connected with the second current output end of the voltage-stabilized power supply module and used for controlling the capacitor in the time-delay output module to be charged so as to control the normal working state of the upper power tube or controlling the capacitor in the time-delay output module to be discharged so as to control the accelerated closing working state of the upper power tube.
Optionally, the charging current control module includes seventeenth to twenty-second triodes, wherein emitters of the seventeenth and eighteenth triodes and a collector of the twenty-first triode are connected to the regulated voltage output terminal of the regulated power supply module, a base of the seventeenth triode is connected to the second current output terminal of the regulated power supply module, a collector of the seventeenth triode and a collector of the twenty-second triode are both connected to a base of the twenty-first triode, an emitter of the twenty-first triode is connected to bases of the twenty-second triode and the twenty-second triode, emitters of the twenty-second triode are grounded, a collector of the twenty-second triode is connected to a collector of the eighteenth triode and a base of the nineteenth triode, a base of the eighteenth triode is connected to an emitter of the nineteenth triode, and a collector of the nineteenth triode is grounded;
the seventeenth to nineteenth triodes are PNP-type triodes, and the twentieth to twenty-second triodes are NPN-type triodes.
Optionally, the delay output module further includes a twenty-third to twenty-seventh triodes and a fourth resistor, where the twenty-third, twenty-sixth to twenty-seventh triodes are PNP triodes, and the twenty-fourth to twenty-fifth triodes are NPN triodes;
the emitter of the twenty-third triode, the base of the twenty-sixth triode is connected with the stabilized voltage output end of the stabilized voltage power supply module, the base of the twenty-third triode is connected with the base of the eighteenth triode, the collector of the twenty-third triode is connected with the base and collector of the twenty-fourth triode, the emitter of the twenty-fourth triode is connected with one end of a capacitor and the base of the twenty-fifth triode, the other end of the capacitor is grounded, the collector of the twenty-fifth triode is connected with one end of a fourth resistor and the base of the twenty-seventh triode, the other end of the fourth resistor is connected with a power supply VCC, the emitter of the twenty-fifth triode is connected with the emitter of the twenty-sixth triode, the collector of the twenty-sixth triode is grounded, the emitter of the twenty-seventh triode is connected with the power supply VCC, and the output state signal of the collector of the twenty-seventh triode controls the power supply tube to accelerate the closing working state or keep the normal working state.
In a second aspect, a power chip is provided, where the power chip includes the enable circuit and a power circuit, and the power circuit includes an internal power circuit and a power output circuit;
the internal power supply circuit includes: a bias current and reference voltage circuit, an error amplifier circuit, a comparator circuit, an oscillator circuit, a constant current circuit, an overheat protection circuit and a logic controller circuit;
the voltage stabilizing power supply module outputs stable voltage for supplying power to the bias current and reference voltage circuit, the error amplifier circuit, the comparator circuit, the oscillator circuit, the constant current circuit, the overheating protection circuit and the logic controller circuit;
the power output circuit includes: a PMOS gate clamp driver and an upper power transistor;
the output end of the accelerating shutdown module of the enabling circuit is connected with the PMOS grid clamping driver and the upper power tube, and a state signal of the output end of the accelerating shutdown module is used for controlling the upper power tube to be closed in an accelerating mode or to be kept in a normal working state.
In a third aspect, a method for controlling the power supply chip is provided, which includes the following steps:
step S100: inputting an enable signal, generating a first current according to the enable signal, and generating a stable voltage and a second current in response to the first current signal;
step S200: providing a supply voltage to a power circuit of the power chip in response to the voltage signal;
step S300: and generating a state signal in response to the voltage signal and the second current signal, and controlling the external power supply voltage of the power supply chip.
Optionally, when the enable signal is at a floating or high level, the first current is a constant current greater than 0A, the regulated voltage is a regulated voltage greater than 0V, the second current is a constant current greater than 0A, the state signal is in a high-resistance state, and the external supply voltage is at an expected voltage level;
when the enable signal is at a low level, the first current is equal to 0A, the stable voltage is decreased until 0V, the second current is decreased until 0A, the state signal is at a high level, and the external supply voltage is at a high impedance state.
In summary, the present invention includes the following beneficial effects:
1. when the power supply chip is shut down, the upper power tube is closed by the accelerated shutdown module to shorten the shutdown delay time. When the EN pin is at a low level, under the combined action of the micro constant current source circuit and the voltage stabilizing power supply module, the stabilized voltage is at a low level, the state signal is at a high level, the state signal is connected to the grid electrode of the upper power tube, the discharging speed of the parasitic capacitor in the upper power tube can be accelerated after the state signal is at the high level, the closing speed of the upper power tube is accelerated, the logic time sequence is not required to be considered, and the shutdown delay time is reduced.
2. Through EN pin control little constant current source circuit, constant voltage power supply module, the shutdown module with higher speed, the internal power supply circuit power supply of power chip is realized to the constant voltage power supply module. When the EN pin is at a low level, under the combined action of the micro constant current source circuit and the voltage stabilizing power supply module, the stabilized voltage is at a low level, the stabilized voltage stops supplying power for the internal power supply circuit in the power supply chip rapidly, and when the EN pin is at a high level, the stabilized voltage is at a high level, and the internal power supply circuit of the power supply chip can supply power rapidly. Thereby realizing the reduction of the on-off time. Meanwhile, the enabling circuit is simple in design, low in power consumption during shutdown, free of more signals for controlling a chip, low in requirement on driving capability of control signals, capable of avoiding the phenomenon of unstable output voltage during startup and shutdown, capable of reducing startup and shutdown delay due to the fact that a shutdown module is accelerated, and capable of achieving the startup and shutdown function of the EN pin by using a simple circuit and control logic.
3. The low-power-consumption enabling circuit and the control method for the power supply chip have low shutdown current. In the transistor process, each device is isolated from each other, so the circuit has good latch-up resistance and higher anti-interference capability, the design difficulty of the whole system is reduced, and the reliability of the system is improved.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic diagram of a control method for shutdown of a power chip in the prior art;
FIG. 2 is a diagram illustrating a control method of a power chip during power-on according to the prior art;
FIG. 3 is a schematic diagram of a power chip in one embodiment;
FIG. 4 is a schematic diagram showing the connection of an enable circuit of the power supply chip in one embodiment;
FIG. 5 is a power chip power-on simulation waveform in one embodiment;
FIG. 6 is a power chip shutdown simulation waveform in one embodiment.
The reference numbers illustrate:
a power supply chip 100; a bias current and reference voltage circuit 101; an error amplifier circuit 102; a comparator circuit 103; an oscillator circuit 104; a constant current circuit 105; an overheat protection circuit 106; a logic controller circuit 107; an NMOS gate clamp driver 108; a current limiting circuit 109; PMOS gate clamp driver 110; an enable circuit 200; a micro constant current source circuit 210; a current mirror circuit 211; a current source circuit 212; a regulated power supply module 220; a current source input circuit 221; a vdd regulator circuit 222; an accelerated shutdown module 230; a charging current control module 231; a delay output module 232.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, embodiments accompanying figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
Referring to fig. 3-4, a preferred embodiment of an enabling circuit 200 of a power chip 100 according to the invention is shown, wherein the enabling circuit 200 is used for controlling the power chip 100 to be powered on and powered off, and includes a micro constant current source circuit 210, a regulated power supply module 220 and an accelerated power-off module 230. The power supply chip includes an internal power supply circuit and a power supply output circuit.
The output end of the micro constant current source circuit 210 is connected to the regulated power supply module 220, and the regulated power supply module 220 is connected to the accelerated shutdown module 230. The micro constant current source circuit 210 is configured to generate a first current bias1 according to an externally input enable signal EN, and the first current bias1 controls the regulated power supply module 220 to generate a regulated voltage vdd and a current bias2. Regulated power supply module 220 outputs regulated voltage vdd for powering the power circuits of power chip 100. The accelerated shutdown module 230 is configured to generate a state signal GATEP for controlling the power supply state of the power chip to supply power to the outside according to the magnitude of the stabilized voltage vdd and the second current bias2 output by the voltage stabilizing power supply module 220, where the power supply state includes accelerated shutdown of power supply and power supply maintenance.
Further, the power supply circuit includes an internal power supply circuit and a power supply output circuit, and the power supply output circuit includes: upper power tube Q P . The internal power circuit is used for generating power for supplying power to external equipment and the upper power tube Q P The power supply chip 100 is a switch for controlling the external power supply state and the magnitude of the power supply voltage. The output end state signal GATEP of the shutdown acceleration module 230 is used for controlling the upper power transistor Q P Accelerate shutdown or maintain normal operating conditions.
Further, the EN state of the enable signal includes three states of high level, floating and low level, and the GATEP state of the status signal includes two states of high impedance state and high level. The enable signal EN is input through the EN pin.
Further, the input end of the micro constant current source circuit 210 is connected to the EN pin, and the output end thereof is connected to the regulated power supply module 220, and outputs a first current bias1 to the regulated power supply module 220 according to the voltage (voltage of high level, floating, low level) of the EN pin, so as to control the regulated power supply module 220 to generate the stabilized voltage vdd and a second current bias2. The signal output terminal of the regulated power supply module 220 is connected to the accelerated shutdown module 230, and the accelerated shutdown module 230 is controlled to control the upper power transistor Q by the voltage value of the regulated voltage vdd and the current value of the second current bias2 respectively P The working state comprises a closing state and a normal working state. The regulated voltage vdd is also used to power the internal power supply circuitry.
Further, the internal power supply circuit includes:a bias current and reference voltage circuit 101, an error amplifier circuit 102, a comparator circuit 103, an oscillator circuit 104, a constant current circuit 105, an overheat protection circuit 106, and a logic controller circuit 107. The power output circuit further includes: NMOS gate clamp driver 108, current limiting circuit 109, PMOS gate clamp driver 110, and lower power transistor Q N . Regulated power supply module 220 outputs regulated voltage vdd for powering bias current and reference voltage circuit 101, error amplifier circuit 102, comparator circuit 103, oscillator circuit 104, constant current circuit 105, over-temperature protection circuit 106, and logic controller circuit 107.
Upper power tube Q P And a lower power tube Q N Respectively a PMOS tube and an NMOS tube. State signal GATEP high-level turn-off upper power tube Q P High resistance state holding upper power tube Q P And (5) working state. The current limiting circuit 109 is a comparator circuit.
Upper power tube Q P Is connected with a power supply VCC, and an upper power tube Q P Drain electrode of and lower power tube Q N The drain of the power supply chip 100 is connected, the connection part is the external power supply voltage SW of the power supply chip 100, meanwhile, the connection part is connected with the input end of the current limiting circuit 109, the other input end of the current limiting circuit 109 is connected with VCC, the output end of the current limiting circuit 109 is connected with the logic controller circuit, and the upper power tube Q P Is connected to the PMOS gate clamp driver 110. Lower power tube Q N Is connected to an NMOS gate clamp driver 108, and a lower power transistor Q N Is connected to ground GND.
The logic controller circuit 107 is connected to the upper power transistor Q through a PMOS gate clamp driver 110 P Grid electrode, and by controlling the upper power transistor Q P Gate voltage controlled upper power tube Q P And conducting current, so as to control the external power supply state of the power supply chip 100 and the external power supply voltage SW, where the power supply state includes maintaining power supply or accelerating power off.
The logic controller circuit 107 controls the upper power transistor Q through the PMOS gate clamp driver 110 and the NMOS gate clamp driver 108 respectively P And a lower power tube Q N Thereby controlling the upper power transistor Q P Lower power tube Q N On-state currentTherefore, the external power supply state of the power supply chip 100 and the magnitude of the external power supply voltage SW are controlled, and the power supply state includes maintaining power supply or accelerating power supply disconnection.
Further, the micro constant current source circuit 210 includes a current mirror circuit 211 and a current source circuit 212. The current mirror circuit 211 is connected to the current source circuit 212. The current mirror circuit 211 is configured to output a control voltage according to the magnitude of the external EN pin input voltage, and control the voltage control current source circuit 212 to output the first current bias1 of the current source.
Further, the current mirror circuit 211 includes first to thirteenth diode tubes Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, first to third resistors R0, R1, R2, and a transistor J0.
The triodes Q1, Q2, Q7 and Q8 form a current mirror, emitting electrodes of the triodes Q1, Q2, Q7 and Q8 are all connected with a power supply VCC, and bases of the triodes Q1, Q2, Q7 and Q8 are all connected together and connected with a collector electrode of the triode Q1. The collector of the triode Q1 is connected with the drain of the transistor J0, the grid of the transistor J0 is grounded, and the source of the transistor J0 is connected with one end of the resistor R0 and used for generating micro-current I1. The other end of the resistor R0 is connected with an emitting electrode of the triode Q3 and a collecting electrode of the triode Q4, the collecting electrode of the triode Q4 is connected with the base electrode, the emitting electrode of the triode Q4 is connected with the base electrode of the triode Q5, the collecting electrode of the triode Q3 is connected with the base electrode and the connection part is connected with the EN pin, the EN pin is used for controlling the voltage of the f point of the connection part of the triode Q3 and the triode Q4, and therefore the conduction state of the triode Q4 and the triode Q5 and the current after conduction are controlled.
The collector of triode Q5 is connected with the collector of triode Q2, junction h is connected with the base of triode Q6, the emitter of triode Q6 is grounded, the collector of triode Q6 is connected with the collector of triode Q7, junction j is connected with the collector of triode Q9, the base of triode Q9 is connected with the base and collector of triode Q10 respectively, the emitter of triode Q9 and the emitter of triode Q10 are connected with one end of resistors R1 and R2 respectively, the other end of resistors R1 and R2 is grounded, and a mirror image constant current source circuit is formed.
Further, the Transistor J0 is an N-channel Junction Field Effect Transistor (JFET). The triodes Q1, Q2, Q3, Q7 and Q8 are PNP triodes, and the triodes Q4, Q5, Q6, Q9 and Q10 are NPN triodes.
Further, the current source circuit 212 is used for connecting the current mirror circuit 211 to control and generate a first current bias1, and includes eleventh to thirteenth and fifteenth transistors Q11, Q12, Q13 and Q15.
The base electrode of the triode Q11 is connected with the j point of the connection part of the triode Q7 and the triode Q9, the collector electrode of the triode Q11 is connected with the base electrode of the triode Q12 and the base electrode of the triode Q13, and the emitter electrode of the triode Q11 is connected with the collector electrode of the triode Q12 and one end of the resistor R2.
The emitting electrode of the triode Q12 and the emitting electrode of the triode Q13 are connected with a power supply VCC, the collecting electrode of the triode Q13 is connected with the collecting electrode and the base electrode of the triode Q15, and the emitting electrode of the triode Q15 is grounded. The base of the transistor Q15 is used to generate the first current bias1.
Further, the transistors Q12 and Q13 are PNP transistors, and the transistors Q11 and Q15 are NPN transistors.
Further, the regulated power supply module 220 includes a current source input circuit 221 and a vdd regulator circuit 222. The current source input circuit 221 is used for inputting a first current bias1, and the vdd regulator circuit 222 generates a regulated voltage vdd and a second current bias2 according to the magnitude of the first current bias1.
The current source input circuit 221 includes: a fourteenth transistor Q14 and a sixteenth transistor Q16. The base electrode of the triode Q16 is connected with the base electrode of the triode Q15 and the current input end of the vdd regulator circuit 222, namely the current input end of the vdd regulator circuit 222 flows into a first current bias1, the collector electrode of the triode Q16 is connected with the collector electrode and the base electrode of the triode Q14, the emitter electrode of the triode Q16 is grounded, and the emitter electrode of the triode Q14 is connected with the power supply VCC. The vdd regulator circuit 222 generates a stable voltage and current, i.e., a stable voltage vdd and a second current bias2, according to the first current bias1.
Further, the transistor Q14 is a PNP transistor, and the transistor Q16 is an NPN transistor.
Further, the shutdown acceleration module230 includes a charging current control module 231 and a delay output module 232. The delay output module 232 includes a capacitor C1. The input end of the charging current control module 231 is connected with the second current bias2 output end of the vdd regulator circuit 222, and is used for controlling the capacitor C1 in the delay output module 232 to charge or discharge so as to respectively control the upper power tube Q P And keeping a normal working state or accelerating to close the working state.
The charging current control module 231 includes seventeenth to twenty second transistors Q17-Q22. The emitting electrodes of the triodes Q17 and Q18 and the collecting electrode of the triode Q21 are connected with the stabilized voltage vdd of the stabilized voltage supply module 220, the base electrode of the triode Q17 is connected with the second current bias2 output end of the vdd stabilized voltage supply circuit 222, the collecting electrode of the triode Q17 is connected with the collecting electrode of the triode Q20 and the base electrode of the triode Q21, the emitting electrode of the triode Q20 is grounded, and the emitting electrode of the triode Q21 is connected with the base electrodes of the triodes Q20 and Q22. The emitting electrode of the triode Q22 is grounded, the collecting electrode of the triode Q22 is connected with the collecting electrode of the triode Q18 and the base electrode of the triode Q19, the base electrode of the triode Q18 is connected with the emitting electrode of the triode Q19, and the collecting electrode of the triode Q19 is grounded.
The delay output module 232 further includes twenty-third to twenty-seventh triodes Q23 to Q27 and a resistor R3. The emitting electrode of the triode Q23 and the base electrode of the triode Q26 are connected with the stabilized voltage vdd output end of the stabilized voltage power supply module 220, the base electrode of the triode Q23 is connected with the base electrode of the triode Q18, the collecting electrode of the triode Q23 is connected with the base electrode of the triode Q24 and the collecting electrode of the triode Q24, the emitting electrode of the triode Q24 is connected with one end of the capacitor C1 and the base electrode of the triode Q25, the connecting position is marked as a point k, and the other end of the capacitor C1 is grounded. Triode Q25's collecting electrode is connected with resistance R3 one end, triode Q27's base, and the junction is marked as m point, and the resistance R3 other end is connected with power VCC, and triode Q25's projecting pole is connected with triode Q26's projecting pole, and the junction is marked as n point, and triode Q26's collecting electrode ground connection, triode Q26's base is connected with constant voltage power supply module 220's steady voltage vdd output. The emitter of the triode Q27 is connected with the power supply VCC, and the collector of the triode Q27 outputs a state signal GATEP to control the upper power tube Q P Accelerating the closing of the working state or maintaining itAnd (5) normal working state.
The triodes Q17-Q19, Q23 and Q26-Q27 are PNP type triodes, and the triodes Q20-22 and Q24-25 are NPN type triodes.
The working principle is as follows: the transistor J0 is a JFET transistor, a micro-current source I1 is generated by utilizing the characteristics of the transistor J0, the triodes Q1, Q2, Q7 and Q8 are current mirror devices, and the triodes Q2, Q7 and Q8 always have current output.
When the power chip is started, the EN pin is suspended or at a high level, the triode Q3 is a PNP triode, the voltage of the emitting electrode, namely the f point, of the triode Q3 is increased along with the voltage of the EN pin and is about 0.7V high, namely the voltage drop of a PN junction of Vbe, when the voltage of the EN pin is higher than 0.7V, the voltage of the f point is larger than 1.4V, the triode Q5 can be in saturated conduction at the moment, the voltage of the h point is close to 0V, and the triode Q6 is in a closed state, namely a cut-off state. At this time, a circuit composed of triodes Q7, Q8, Q9, Q10, Q11, Q12 and resistors R1 and R2 can work normally, the voltage difference between a base electrode and an emitting electrode of the triode Q10, namely delta Vbe, is generated by utilizing the different proportion relation of the triodes Q9 and Q10, the voltage of a point j rises at this time, the triode Q11 is conducted, the base electrodes of the triodes Q12 and Q13 are connected with a collector electrode of the triode Q11, so the base electrodes of the triodes Q12 and Q13 have conducting voltage, the triodes Q12 and Q13 work, the stable current I2 can be generated by combining the resistance value of the resistor R2, the triodes Q13 and Q15 are conducted, the current, namely the first current bias1 is generated, a starting power supply is provided for the vdd voltage stabilizing source module 220, and the vdd voltage stabilizing source module works to output the stable voltage vdd and generate the second current bias2; the stabilized voltage vdd is used for supplying power to the logic controller circuit and other circuits, the error amplifier circuit and the internal circuit so as to normally work, and the chip normally works.
The second current bias2 provides base current for the transistor Q17 in the shutdown accelerating module 230, the transistor Q17 is conducted, thereby making the base of the transistor Q21 have conduction voltage, meanwhile, the stabilization voltage vdd of the transistor Q21 is large enough, thereby making the transistor Q21 conducted, the emitter of the transistor Q21 is connected with the bases of the transistors Q20 and Q22, thereby making the transistors Q20 and Q22 have conduction voltage, namely, the transistors Q20 and Q22 are conducted, thereby making the transistors Q18 and Q19 conducted, the base of the transistor Q18 and the base of the transistor Q23 are connectedThe base electrodes are connected, so that the triodes Q23 and Q24 are conducted to charge the capacitor C1, when vdd rises from 0V to high voltage, the base electrode voltage of the triode Q26 is vdd, the base electrode voltage of the triode Q25 is the voltage of the capacitor C1, namely the voltage at the point k, the voltage at the point k is less than or equal to vdd, two conducting voltages (1.4V) which are greater than vdd cannot be met, namely the triodes Q25, Q26 and Q27 are cut off, the state signal GATEP high-resistance state cannot influence a rear-stage circuit, namely the upper power tube Q23 cannot be closed P Therefore, power-on logic is not considered, and the device can work normally as long as the vdd voltage rises to a certain value, and the response speed is high.
When the power supply chip is shut down, the EN pin is at a low level, the f point potential is reduced, at the moment, the triodes Q4 and Q5 are not conducted, after the triode Q6 is conducted, because the triode Q6 is in saturated conduction, the j point voltage is lower than the conduction voltage, the triode Q11 is not conducted, at the moment, the base electrode of the triode Q12 is in a high-resistance state, the triodes Q12 and Q13 do not work, the first current bias1 cannot be generated, the vdd voltage stabilization source module stops working, the voltage of the stabilized voltage vdd starts to be reduced from a high level to 0V, in the process, in order to quickly close the chip, the output of the chip is ensured not to be disordered, in the embodiment, the upper power tube Q inside the power supply chip is closed in a time period that the voltage of the stabilized voltage vdd is reduced to 0V P The principle is as follows: when the voltage of the regulated voltage vdd is reduced to a preset value, which is 2.1V lower than the regulated voltage vdd in this embodiment, the transistor Q26 is turned on, the transistor Q25 is turned on, the transistor Q27 is turned on, and the state signal GATEP is at a high level, so as to rapidly turn off the power-up transistor Q P Upper power tube Q P For PMOS transistor, high level is off. Even though the vdd voltage drops to 0V instantly, the capacitor is charged when the EN pin is at a high level, and the voltage keeps a voltage value when the voltage value of the stable voltage vdd is high, so that the potential at the point k can be kept for a period of time higher than that at the point n by one Vbe due to the existence of the capacitor C1, namely the triode Q25 is kept turned on, so that the triode Q27 is kept turned on for a period of time, the state signal GATEP can continuously output a high level for a period of time, and the upper power tube Q is realized P And completely closed. The GATEP current of the status signal becomes larger, because the GATEP signal is connected to the gate of PMOS, the increase of GATEP current will speed up PMOS internal parasitic capacitance's discharge velocity, thereby reduce shutdown delay time, thereby turn off the power tube of chip rapidly, the power tube was closed earlier when guaranteeing that the EN pin shuts down, with this condition of avoiding output voltage unstability, the voltage of steady voltage vdd is less than triode Q26's emitter voltage this moment, triode Q26, Q25 switch on, state signal GATEP's electric current grow, because state signal GATEP can control power supply chip inside last power tube Q P Driving current of state signal GATEP and original upper power tube Q P After the driving currents are superposed, the discharging speed of the internal parasitic capacitor of the upper power tube can be accelerated, so that the shutdown delay time is reduced, in addition, the internal circuit power supply circuit of the voltage vdd control power supply is stabilized, and the power supply of the internal circuit of the chip is turned off.
Namely when the EN is shut down, the vdd voltage stabilization source module stops working immediately, the voltage of the stabilized voltage vdd output by the module starts to be reduced, and when the voltage is reduced to a preset value, an upper power tube in the power supply chip starts to be forcibly turned off; meanwhile, in order to prevent EN foot burr signal interference from causing misoperation, the upper power tube Q is caused P The EN pin is closed in normal work and can set a hysteresis window; in order to prevent the output voltage of the vdd regulator module from being reduced too fast and the upper power transistor from being completely turned off when the EN pin of the power chip 100 is turned off, the accelerated turn-off module 230 is provided with the energy storage device capacitor C1, and even if the voltage of the regulated voltage vdd is reduced to 0V, the module can continue to turn off the upper power transistor Q P . The whole circuit is simple, when the power supply chip 100 is shut down, only four tubes (triodes Q1-Q3 and Q6) work, the shutdown current is extremely low, so that the shutdown power consumption is low, and the circuit complexity is reduced and the startup and shutdown delay time is reduced because the special design does not need startup and shutdown time sequence control.
The embodiment of the invention also provides a power supply chip, and the power supply chip 100 comprises the low-power-consumption enabling circuit 200 and the power supply circuit. The power supply circuit includes an internal power supply circuit and a power supply output circuit.
The internal power supply circuit includes: a bias current and reference voltage circuit 101, an error amplifier circuit 102, a comparator circuit 103, an oscillator circuit 104, a constant current circuit 105, an overheat protection circuit 106, and a logic controller circuit 107. The regulated power supply module 220 outputs a regulated voltage vdd for powering the bias current and reference voltage circuit 101, the error amplifier circuit 102, the comparator circuit 103, the oscillator circuit 104, the constant current circuit 105, the overheating protection circuit 106, and the logic controller circuit 107.
The power output circuit further includes: PMOS gate clamp driver 110 and upper power transistor Q N . The output of the shutdown acceleration module 230 in the low power consumption enable circuit 200, the PMOS gate clamp driver 210 and the upper power transistor Q N The state signal GATEP at the output of the connection and acceleration shutdown module 230 is used for controlling the upper power transistor Q P Accelerate shutdown or maintain normal operating conditions.
The embodiment of the invention also provides an enabling control method of the power supply chip, which comprises the following steps:
step S100: inputting an enable signal EN pin signal, generating a first current bias1 according to the enable signal, and generating a stable voltage vdd and a second current bias2 in response to the first current signal;
step S200: supplying a power supply voltage to a power supply circuit of the power supply chip 100 in response to the voltage signal vdd;
step S300: generating a state signal GATEP in response to the voltage signal vdd and the second current signal bias2, and controlling the power supply chip 100 to supply the external power voltage SW;
as shown in fig. 5, step S100, step S200, and step S300 are steps of controlling the power-on process of the power chip by the enabling control method of the present invention, wherein the enabling signal EN pin signal is a floating or high level signal, the first current bias1 is a constant current greater than 0A, the stable voltage vdd is a stable voltage greater than 0V, the second current bias2 is a constant current greater than 0A, the state signal GATEP is in a high-resistance state, and the external supply voltage SW is a desired voltage.
As shown in fig. 6, step S100, step S200 and step S300 are steps of controlling the power-off process of the power chip according to the enabling control method of the present invention, wherein the enabling signal EN pin is a low level signal, the first current bias1 is equal to 0A, the stable voltage vdd decreases until it is 0V, the second current bias2 decreases until it is 0A, the status signal GATEP is a high level, and the external power supply voltage SW is a high resistance state.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (12)
1. An enabling circuit (200) of a power supply chip is used for controlling the power-on and power-off of the power supply chip (100), and comprises a micro constant current source circuit (210), a voltage-stabilized power supply module (220) and an accelerated power-off module (230);
the output end of the micro constant current source circuit (210) is connected with the stabilized voltage power supply module (220), and the stabilized voltage power supply module (220) is connected with the accelerated shutdown module (230); the micro constant current source circuit (210) is used for generating a first current according to an enable signal input from the outside, and the first current controls the stabilized voltage supply module (220) to generate a stabilized voltage and a second current; the stabilized voltage supply module (220) outputs the stabilized voltage for supplying power to a power circuit of the power chip (100); the accelerated shutdown module (230) is configured to generate a state signal for controlling an external power supply state of the power supply chip (100) according to the stabilized voltage and the second current, where the power supply state includes accelerated shutdown of power supply and power supply maintenance.
2. The enabling circuit of the power chip as claimed in claim 1, wherein the power circuit includes an upper power transistor, the upper power transistor is configured to control an external power supply state of the power chip (100), and the state signal generated at the output terminal of the shutdown acceleration module (230) is configured to control the upper power transistor to be shut down or to maintain a normal operating state.
3. The enable circuit of the power supply chip according to claim 1, wherein the micro constant current source circuit (210) includes a current mirror circuit (211) and a current source circuit (212), the current mirror circuit (211) being connected to the current source circuit (212), the current mirror circuit (211) being configured to output a control voltage according to a voltage value of the enable signal, the control voltage controlling the current value of the first current of the current source circuit (212).
4. The enable circuit of the power supply chip according to claim 3, wherein the current mirror circuit (211) includes 10 transistors, 3 resistors and a transistor, wherein the first to third transistors, the seventh to eighth transistors are PNP type transistors, the fourth to sixth transistors are NPN type transistors, and the transistor is an N-channel junction field effect transistor;
emitting electrodes of the first triode, the second triode, the seventh triode and the eighth triode are all connected with a power supply VCC, and bases of the first triode, the second triode, the seventh triode and the eighth triode are all connected together and connected with a collector electrode of the first triode;
the collector of the first triode is connected with the drain of the transistor, the grid of the transistor is grounded, and the source of the transistor is connected with one end of the first resistor; the other end of the first resistor is respectively connected with an emitting electrode of a third triode and a collecting electrode of a fourth triode, the collecting electrode of the fourth triode is connected with a base electrode, the emitting electrode of the fourth triode is connected with a base electrode of a fifth triode, the collecting electrode of the third triode is connected with the base electrode of the third triode, the connection part is connected with an enabling signal, and the enabling signal is used for controlling the voltage of the connection part of the third triode and the fourth triode;
the collector electrode of the fifth triode is connected with the collector electrode of the second triode, the connection part is connected with the base electrode of the sixth triode, the emitter electrode of the sixth triode is grounded, the collector electrode of the sixth triode is connected with the collector electrode of the seventh triode, the connection part is connected with the collector electrode of the ninth triode, the base electrode of the ninth triode is connected with the base electrode of the thirteenth triode and the collector electrode of the thirteenth triode, the emitter electrode of the ninth triode and the emitter electrode of the thirteenth triode are respectively connected with one end of the second resistor and one end of the third resistor, and the other ends of the second resistor and the third resistor are grounded, so that a mirror image constant current source circuit is formed.
5. The enable circuit of the power supply chip according to claim 4, wherein the current source circuit (212) is connected to a current mirror circuit (211) for generating a first current, and the current source circuit (212) includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fifteenth transistor; the twelfth to thirteenth triodes are PNP type triodes, the eleventh and fifteenth triodes are NPN type triodes;
the base electrode of the eleventh triode is connected with the joint of the seventh triode and the ninth triode, the collector electrode of the eleventh triode is connected with the base electrodes of the twelfth triode and the thirteenth triode, and the emitter electrode of the eleventh triode and the collector electrode of the twelfth triode are both connected with one end of the third resistor;
emitting electrodes of the twelfth triode and the thirteenth triode are connected with a power supply VCC, a collecting electrode of the thirteenth triode is connected with a collecting electrode and a base electrode of the fifteenth triode, an emitting electrode of the fifteenth triode is grounded, and the base electrode of the fifteenth triode is used for generating a first current.
6. The enabling circuit of the power supply chip as claimed in claim 5, wherein the regulated power supply module (220) comprises a current source input circuit (221) and a vdd regulator circuit (222), the current source input circuit (221) is used for inputting a first current, and the vdd regulator circuit (222) generates a regulated voltage and a second current according to the first current;
a current source input circuit (221) includes: a fourteenth triode and a sixteenth triode, wherein the base of the sixteenth triode is connected with the base of the fifteenth triode and the current input end of the vdd voltage regulator circuit (222), the collector of the sixteenth triode is connected with the collector of the fourteenth triode and the base of the fourteenth triode, the emitter of the sixteenth triode is grounded, and the emitter of the fourteenth triode is connected with a power supply VCC;
the fourteenth triode is a PNP triode and the sixteenth triode is an NPN triode.
7. The enabling circuit of the power supply chip according to claim 1, wherein the shutdown acceleration module (230) comprises a charging current control module (231) and a delay output module (232), and the delay output module (232) comprises a capacitor; the input end of the charging current control module (231) is connected with the second current output end of the voltage-stabilized power supply module (220) and is used for controlling the capacitor in the delay output module (232) to be charged so as to control the normal working state of the upper power tube, or controlling the capacitor in the delay output module (232) to be discharged so as to control the accelerated closing working state of the upper power tube.
8. The enabling circuit of the power supply chip according to claim 7, wherein the charging current control module (231) comprises seventeenth to twenty second triodes, wherein the emitters of the seventeenth and eighteenth triodes and the collector of the twenty-first triode are connected to the regulated voltage output terminal of the regulated power supply module (220), the base of the seventeenth triode is connected to the second current output terminal of the regulated power supply module (220), the collector of the seventeenth triode and the collector of the twentieth triode are both connected to the base of the twenty-first triode, the emitters of the twenty-first triode and the twenty-second triode are connected to the base, the emitters of the twentieth triode and the twenty-second triode are grounded, the collector of the twenty-second triode is connected to the collector of the eighteenth triode and the base of the nineteenth triode, the base of the eighteenth triode is connected to the emitter of the nineteenth triode, and the collector of the nineteenth triode is grounded;
the seventeenth to nineteenth triodes are PNP-type triodes, and the twentieth to twenty-second triodes are NPN-type triodes.
9. The enabling circuit of the power supply chip according to claim 7, wherein the delay time output module (232) further comprises twenty-third to twenty-seventh triodes and a fourth resistor, wherein the twenty-third, twenty-sixth to twenty-seventh triodes are PNP type triodes, and the twenty-fourth to twenty-fifth triodes are NPN type triodes;
the emitter of the twenty-third triode, the base of the twenty-sixth triode and the stabilized voltage output end of the stabilized voltage power supply module (220) are connected, the base of the twenty-third triode is connected with the base of the eighteenth triode, the collector of the twenty-third triode is connected with the base and collector of the twenty-fourth triode, the emitter of the twenty-fourth triode is connected with one end of a capacitor and the base of the twenty-fifth triode, the other end of the capacitor is grounded, the collector of the twenty-fifth triode is connected with one end of a fourth resistor and the base of the twenty-seventh triode, the other end of the fourth resistor is connected with a power supply VCC, the emitter of the twenty-fifth triode is connected with the emitter of the twenty-sixth triode, the collector of the twenty-sixth triode is grounded, the emitter of the twenty-seventh triode is connected with the power supply VCC, and the collector output state signal of the twenty-seventh triode controls the power supply tube to accelerate the closing of the working state or keep the normal working state.
10. A power supply chip, the power supply chip (100) comprising an enable circuit (200) as claimed in any one of claims 1-9 and a power supply circuit, the power supply circuit comprising an internal power supply circuit and a power supply output circuit;
the internal power supply circuit includes: a bias current and reference voltage circuit (101), an error amplifier circuit (102), a comparator circuit (103), an oscillator circuit (104), a constant current circuit (105), an overheat protection circuit (106), and a logic controller circuit (107);
the voltage stabilizing power supply module (220) outputs stable voltage for supplying power to the bias current and reference voltage circuit (101), the error amplifier circuit (102), the comparator circuit (103), the oscillator circuit (104), the constant current circuit (105), the overheating protection circuit (106) and the logic controller circuit (107);
the power output circuit includes: a PMOS gate clamp driver (110) and an upper power transistor;
the output end of an accelerated shutdown module (230) of the enabling circuit (200) is connected with the PMOS grid clamping driver (110) and the upper power tube, and a state signal of the output end of the accelerated shutdown module (230) is used for controlling the upper power tube to be shut down in an accelerated mode or to be kept in a normal working state.
11. A control method of the power supply chip as claimed in claim 10, comprising the steps of:
step S100: inputting an enable signal, generating a first current according to the enable signal, and generating a stable voltage and a second current in response to the first current signal;
step S200: providing a supply voltage to a power circuit of the power chip (100) in response to the voltage signal;
step S300: and generating a state signal in response to the voltage signal and the second current signal, and controlling the external power supply voltage of the power supply chip (100).
12. The control method according to claim 11, wherein when the enable signal is floating or high level, the first current is a constant current greater than 0A, the regulated voltage is a regulated voltage greater than 0V, the second current is a constant current greater than 0A, the status signal is in high impedance state, and the external power supply voltage is a desired voltage level;
when the enable signal is at low level, the first current is equal to 0A, the stable voltage is decreased to 0V, the second current is decreased to 0A, the status signal is at high level, and the external power supply voltage is at high impedance state.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11264845A (en) * | 1998-03-17 | 1999-09-28 | Nec Ic Microcomput Syst Ltd | Power voltage monitoring circuit and input signal level monitoring circuit |
| US20110122659A1 (en) * | 2009-11-20 | 2011-05-26 | Bcd Semiconductor Manufacturing Limited | Power transistor driving circuits and methods for switching mode power supplies |
| US20110261596A1 (en) * | 2010-04-27 | 2011-10-27 | Bcd Semiconductor Manufacturing Limited | Control circuit for primary side control of switching power supply |
| CN103956905A (en) * | 2014-04-18 | 2014-07-30 | 昂宝电子（上海）有限公司 | System and method for adjusting output currents in power source transformation system |
| US20160156171A1 (en) * | 2014-11-27 | 2016-06-02 | Monolithic Power Systems, Inc. | High voltage current source with short circuit protection |
| CN111969838A (en) * | 2020-10-20 | 2020-11-20 | 上海芯龙半导体技术股份有限公司南京分公司 | PMOS power tube grid clamping driving module, driving circuit and switching power supply |
| CN114785098A (en) * | 2022-06-14 | 2022-07-22 | 上海芯龙半导体技术股份有限公司南京分公司 | Drive circuit and power supply chip |
-
2023
- 2023-02-01 CN CN202310048719.1A patent/CN115882712B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11264845A (en) * | 1998-03-17 | 1999-09-28 | Nec Ic Microcomput Syst Ltd | Power voltage monitoring circuit and input signal level monitoring circuit |
| US20110122659A1 (en) * | 2009-11-20 | 2011-05-26 | Bcd Semiconductor Manufacturing Limited | Power transistor driving circuits and methods for switching mode power supplies |
| US20110261596A1 (en) * | 2010-04-27 | 2011-10-27 | Bcd Semiconductor Manufacturing Limited | Control circuit for primary side control of switching power supply |
| CN103956905A (en) * | 2014-04-18 | 2014-07-30 | 昂宝电子（上海）有限公司 | System and method for adjusting output currents in power source transformation system |
| US20160156171A1 (en) * | 2014-11-27 | 2016-06-02 | Monolithic Power Systems, Inc. | High voltage current source with short circuit protection |
| CN111969838A (en) * | 2020-10-20 | 2020-11-20 | 上海芯龙半导体技术股份有限公司南京分公司 | PMOS power tube grid clamping driving module, driving circuit and switching power supply |
| CN114785098A (en) * | 2022-06-14 | 2022-07-22 | 上海芯龙半导体技术股份有限公司南京分公司 | Drive circuit and power supply chip |
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Application publication date: 20230331 Assignee: Shanghai Kangjian Electronic Technology Co.,Ltd. Assignor: SHANGHAI XINLONG SEMICONDUCTOR TECHNOLOGY CO.,LTD. Contract record no.: X2024980003846 Denomination of invention: Enabling circuit, power chip, and control method of a power chip Granted publication date: 20230512 License type: Common License Record date: 20240403 |