CN115881202B - Repair circuit and method, memory and electronic equipment - Google Patents
Repair circuit and method, memory and electronic equipment Download PDFInfo
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- CN115881202B CN115881202B CN202310087550.0A CN202310087550A CN115881202B CN 115881202 B CN115881202 B CN 115881202B CN 202310087550 A CN202310087550 A CN 202310087550A CN 115881202 B CN115881202 B CN 115881202B
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Abstract
The embodiment of the disclosure provides a repair circuit and method, a memory and electronic equipment, wherein the repair circuit is applied to the memory comprising a plurality of memory blocks, the repair circuit comprises a plurality of address modules, and each address module outputs a candidate repair code of one memory block; the candidate repair codes indicate that all redundant rows in the storage block are occupied, or the candidate repair codes indicate that redundant rows which are unoccupied and have the highest priority in the storage block; the repair circuit further includes: the selection module is connected with the address modules and is configured to receive a plurality of candidate repair codes; selecting and outputting a target repair code from a plurality of candidate repair codes under the condition that a failure line exists in a memory; and the repair module is connected with the selection module and is configured to carry out redundancy repair processing on the failure line by utilizing the target repair code. The repair circuit provided by the embodiment of the disclosure can improve the repair efficiency of redundant rows.
Description
Technical Field
The disclosure relates to the technical field of semiconductor memories, and in particular relates to a repair circuit and method, a memory and electronic equipment.
Background
The memory provides Post-Package-Repair (PPR) functions, specifically, the redundant row address is used to replace the failed row address, so as to Repair the failed memory row (failure row for short). However, in the current PPR function, some fixed redundant rows need to be set to repair the corresponding storage rows, so that the repair efficiency is low, and the user operation space is small.
Disclosure of Invention
A repair circuit and method, a memory and an electronic device are provided.
The technical scheme of the present disclosure is realized as follows:
in a first aspect, embodiments of the present disclosure provide a repair circuit applied to a memory including a plurality of memory blocks, the repair circuit including a plurality of address modules, and each of the address modules outputting a candidate repair code for the memory block; the candidate repair codes indicate that all redundant rows in the storage block are occupied, or the candidate repair codes indicate that redundant rows which are unoccupied and have the highest priority in the storage block;
the repair circuit further includes:
the selection module is connected with the address modules and is configured to receive the candidate repair codes; selecting and outputting a target repair code from a plurality of candidate repair codes under the condition that a failure line exists in the memory;
And the repair module is connected with the selection module and is configured to carry out redundancy repair processing on the failure line by utilizing the target repair code.
In some embodiments, each of the address modules includes a plurality of address sub-modules;
the address module is configured to output the candidate repair codes by using the address submodule in an active state;
if all the redundant rows managed by the ith-1 address sub-module are occupied and all the redundant rows managed by the ith address sub-module are not occupied, the ith address sub-module is in an active state; and if all the redundant rows managed by the ith address sub-module are occupied, the ith address sub-module exits from the active state.
In some embodiments, each of the address sub-modules manages a redundancy groups, and each of the redundancy groups includes B redundancy rows;
the address submodule comprises A address units, and each address unit outputs a first intermediate code of the redundancy group; wherein the first intermediate code indicates that all redundant rows in the redundant group are occupied, or the first intermediate code indicates that redundant rows in the redundant group are unoccupied and have highest priority;
The address sub-module further includes:
the first logic unit is connected with the A address units and is configured to receive A first intermediate codes; outputting a second intermediate code based on the a first intermediate codes; the second intermediate code indicates that all redundant rows managed by the address submodule are occupied, or the second intermediate code is used for indicating that unoccupied redundant rows exist and a redundant group with highest priority exists;
and an output unit configured to output the candidate repair codes based on a number of the first intermediate codes and the second intermediate codes.
In some embodiments, the first intermediate code includes a first state code and a first level index code, the first state code indicating whether redundant rows in the redundancy group are all occupied; in the case where not all of the redundant rows in the redundant set are occupied, the first level index code indicates the redundant row in the redundant set that is unoccupied and has the highest priority.
In some embodiments, the address unit includes B memory elements;
each of the memory cells stores a row address and a third status code for one of the redundant rows; wherein the third status code is valid if the redundant row is unoccupied; in the case that the redundant row is occupied, the third status code is invalid;
The address unit further comprises a second logic unit;
the second logic unit is connected with the B storage elements and is configured to receive the B third state codes; outputting the invalid first state code under the condition that all B third state codes are invalid; or outputting the valid first state code under the condition that at least one third state code is valid, and outputting the serial number of the storage element with the valid third state code and the forefront ordering as the first-stage index code.
In some embodiments, the second intermediate code includes a second state code and a second level index code, the second state code indicating whether all redundant rows managed by the address submodule are occupied; and in the case that the redundant rows managed by the address sub-module are not all occupied, the second-level index code indicates a redundant group to which the unoccupied and highest-priority redundant row belongs.
In some embodiments, the first logic is configured to output the second status code that is invalid if all a of the first status codes are invalid; or outputting the second state code which is valid under the condition that at least one first state code is valid, and outputting the serial number of the address unit which is valid and ordered forefront by the first state code as the second-stage index code.
In some embodiments, the output unit is specifically configured to determine a first-level index code of the address unit corresponding to the second-level index code as a first-level target index code;
the first-stage target index code, the second-stage index code and the second state code jointly form the candidate repair code.
In some embodiments, the target repair code refers to a candidate repair code of a memory block to which the failed line belongs; the repair circuit further comprises a repair control module;
the repair control module is configured to output a block selection signal when a failure line exists in the memory; wherein the block select signal indicates a memory block to which the failed row belongs;
the selection module is specifically configured to receive the block selection signal, and determine the target repair code from a plurality of candidate repair codes based on the block selection signal.
In some embodiments, the repair module is specifically configured to receive the target repair code and the block selection signal; and under the condition that the second state code of the target repair code is effective, determining a target redundant row by using the first-stage target index code of the target repair code, the second-stage index code of the target repair code and the block selection signal, and mapping the signal path of the invalid row to the target redundant row so as to realize redundant repair processing.
In some embodiments, the repair control module is further configured to output a repair enable signal and a failed row address; wherein the repair enable signal is valid in the event that there is a fail line in the memory;
the repair module comprises a decoding module and an anti-fuse module, and the anti-fuse module is connected with the repair control module and the decoding module;
the decoding module is configured to receive the target repair code and the block selection signal; under the condition that a second state code in the target repair codes is effective, decoding the first-stage target index code in the target repair codes, the second-stage index code in the target repair codes and the block selection signal, and outputting a fuse address;
the antifuse module includes an antifuse array configured to receive the repair enable signal, the fail row address, and the fuse address; and in the case that the repair enable signal is valid, performing a blowing process on the antifuse array based on the fuse address and the fail row address, so that a signal path of the fail row is mapped to the target redundancy row.
In some embodiments, a=4 and b=4.
In a second aspect, embodiments of the present disclosure provide a repair method applied to a memory including a plurality of memory blocks, the method including:
determining candidate repair codes of each storage block; the candidate repair codes indicate that all redundant rows in the storage block are occupied, or the candidate repair codes indicate that redundant rows which are unoccupied and have the highest priority in the storage block;
selecting and outputting a target repair code from a plurality of candidate repair codes under the condition that a failure line exists in the memory;
and performing redundancy repair processing on the failure line by using the target repair code.
In a third aspect, embodiments of the present disclosure provide a memory comprising a plurality of memory blocks and a repair circuit as described in the first aspect.
In a fourth aspect, embodiments of the present disclosure provide an electronic device comprising a memory as described in the third aspect.
The embodiment of the disclosure provides a repair circuit and method, a memory and electronic equipment, wherein redundant rows of a memory block are managed through an address module, so that the repair efficiency of the redundant rows is improved, and more operation space is provided for a user.
Drawings
Fig. 1 is a schematic structural diagram of a repair circuit according to an embodiment of the disclosure;
fig. 2 is a schematic structural diagram of an address sub-module according to an embodiment of the disclosure;
fig. 3 is a schematic structural diagram of an address unit according to an embodiment of the disclosure;
fig. 4 is a schematic diagram of an operating principle of an address submodule according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of another repair circuit according to an embodiment of the disclosure;
FIG. 6 is a schematic diagram of a memory provided in an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a specific structure of a repair circuit according to an embodiment of the disclosure;
FIG. 8 is a schematic flow chart of a repair method according to an embodiment of the disclosure;
FIG. 9 is a schematic diagram of a memory according to an embodiment of the disclosure;
fig. 10 is a schematic structural diagram of an electronic device according to an embodiment of the disclosure.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the application and not limiting of the application. It should be noted that, for convenience of description, only a portion related to the related application is shown in the drawings. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure. In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict. It should be noted that the term "first/second/third" in relation to the embodiments of the present disclosure is merely used to distinguish similar objects and does not represent a particular ordering for the objects, it being understood that the "first/second/third" may be interchanged with a particular order or sequencing, if allowed, to enable the embodiments of the present disclosure described herein to be implemented in an order other than illustrated or described.
Dynamic random access memory (Dynamic Random Access Memory, DRAM);
a synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM);
double Data Rate memory (DDR);
low Power DDR (LPDDR).
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
In one embodiment of the present disclosure, referring to fig. 1, a schematic diagram of a repair circuit 10 provided by an embodiment of the present disclosure is shown. The repair circuit 10 is applied to a memory including a plurality of memory blocks (e.g., bank0, bank1, bank2 … …), as shown in fig. 1, the repair circuit 10 includes a plurality of address blocks 11, and each address block 11 outputs a candidate repair code of one memory block; the candidate repair codes indicate that all redundant rows in the corresponding storage blocks are occupied, or the candidate repair codes indicate that redundant rows which are unoccupied and have the highest priority in the corresponding storage blocks.
The repair circuit 10 further includes:
a selection module 12, connected to each of the plurality of address modules 11, configured to receive a plurality of candidate repair codes; selecting and outputting a target repair code from a plurality of candidate repair codes under the condition that a failure line exists in a memory;
And the repair module 13 is connected with the selection module 12 and is configured to perform redundancy repair processing on the failure line by utilizing the target repair code.
It should be noted that the repair circuit 10 of the embodiment of the present disclosure may be applied to, but not limited to, a memory, such as DRAM, SDRAM, DDR, LPDDR. In addition, in other analog/digital circuits, the repair circuit 10 provided by the embodiments of the present disclosure may implement an Auto-find (Auto-find) function of redundant rows to implement repair of failed rows.
Here, the address modules 11 and the storage blocks are in one-to-one correspondence, and each address module 11 manages redundant rows in the corresponding storage block and outputs a corresponding candidate repair code; the selection module 12 further selects a target repair code from the candidate repair codes of each memory block, so that the repair module 13 repairs the failed row by using the corresponding redundant row. In this way, the redundant rows in each storage block are orderly managed, and an Auto-Find (Auto-Find) function of the redundant rows is realized, so that not only is the repair efficiency and flexibility of the redundant rows improved, but also more operation space is provided for users.
It should be further noted that the priority rules of different redundant rows may be set according to the actual scenario.
In some embodiments, each address module 11 includes a plurality of address sub-modules; an address module 11 configured to output candidate repair codes using the address submodule in an active state; if all the redundant rows managed by the i-1 address submodule are occupied and all the redundant rows managed by the i address submodule are not occupied, the i address submodule is in an active state; if all the redundant rows managed by the ith address submodule are occupied, the ith address submodule exits the active state. Here, i is a positive integer.
It should be noted that, a large number of redundant rows are provided for each memory block, and in this embodiment of the disclosure, a plurality of address sub-modules are provided for each memory block, so that these redundant rows are separately managed, and management efficiency is improved. Here, different address sub-modules can be implemented by adopting the same or similar circuit structures, so that the difficulty of hardware production is reduced. Meanwhile, the specific setting number of the address sub-modules needs to be determined according to the actual application scene.
In addition, the different address sub-modules are also in an active state, and the address sub-module which has the highest priority and is not fully occupied by the managed redundant lines is in an ordered priority, so that the candidate repair codes of the storage block are output; the remaining address sub-modules are all in a sleep (not enabled) state.
In a specific embodiment, repair circuit 10 further includes:
the logic circuit is configured to output an enabling signal of each address sub-module based on the occupation condition of all redundant rows in the storage block; wherein only one address sub-module is enabled to indicate that the corresponding address sub-module is in an active state; the enable signals of the remaining address sub-modules are disabled to indicate that the corresponding address sub-module is in a sleep state.
In other embodiments, for the address module 11, all address sub-modules output respective repair codes, and candidate repair codes are further selected from the repair codes output from all address sub-modules.
In still other embodiments, each address module 11 may also include only one address sub-module, and after the redundant rows managed by the address sub-module are fully occupied, the address sub-module may automatically refresh the managed redundant row addresses, thereby managing other redundant rows, and reducing the circuit area.
In particular, in still other embodiments, the number of address sub-modules may be 1, which is essentially equivalent to unified management of redundant rows throughout the memory block, without further division of the hierarchy of "address sub-modules".
In the following description of the address sub-modules, the description of "hardware configuration" applies to all the address sub-modules, but the description of "actions of signal reception, processing, output" applies only to the address sub-modules in the active state.
In some embodiments, each address submodule manages a redundancy groups, and each redundancy group includes B redundancy rows. Here, a and B are both positive integers. As shown in fig. 2, the address submodule includes a number a of address units 21, and each address unit 21 outputs a first intermediate code of a redundancy group (i.e., a redundancy group corresponding to the address unit 21); wherein the first intermediate code indicates that all redundant rows in the redundant set are occupied, or the first intermediate code indicates that redundant rows in the redundant set that are unoccupied and have the highest priority.
The address sub-module further includes:
a first logic unit 22, connected to each of the a address units 21, configured to receive a first intermediate codes; outputting a second intermediate code based on the a first intermediate codes; the second intermediate code indicates that all redundant rows managed by the address submodule are occupied, or the second intermediate code is used for indicating that unoccupied redundant rows exist and a redundant group with highest priority exists;
An output unit 23 configured to output candidate repair codes based on the a first intermediate codes and the second intermediate codes.
Thus, each address submodule manages a×b redundant rows, and the redundant rows are subdivided into different redundancy groups, each of which is managed by one address unit 21, further improving management efficiency.
The first logic unit 22 is designed based on a preset priority rule, and is configured to perform a logic operation on the basis of the first intermediate code, so as to obtain candidate repair codes subsequently. In addition, in other embodiments, different redundancy groups may include different numbers of redundant rows, and different address sub-modules may also manage different numbers of redundant rows, as examples only and not by way of limitation.
Taking a=4 and b=4 as an example, referring to fig. 4, a schematic diagram of the working principle of an address sub-module in an active state is provided. In particular, in fig. 4, each connection line does not represent a real physical or signal path, and is understood in conjunction with the text. As shown in fig. 4, the address submodule includes an address unit 0, an address unit 1, an address unit 2, an address unit 3, a first logic unit 22, and an output unit 23. Address unit 0 outputs a first intermediate code M 0 N 0 en 0 The address unit 1 outputs a first intermediate code M 1 N 1 en 1 The address unit 2 outputs a first intermediate code M 2 N 2 en 2 The address unit 3 outputs a first intermediate code M 3 N 3 en 3 。
Correspondingly, the first intermediate code comprises a first status code (e.g., en in fig. 4 0 Or en 1 Or en 2 Or en 3 ) And a first level index code (e.g., M in FIG. 4 0 N 0 Or M 1 N 1 Or M 2 N 2 Or M 3 N 3 ) The first status code indicates whether all redundant rows in the redundant set are occupied; in the case where not all of the redundant rows in the redundant set are occupied, the first level index code indicates the redundant row in the redundant set that is unoccupied and has the highest priority.
It should be noted that the first state code is generally one-bit data, and the first level index code may be multi-bit data, which depends on the value of B. Since fig. 4 is a schematic diagram of b=4, the first level index code includes 2-bit data.
In this way, the first intermediate code carries redundant row information managed by the corresponding address unit, so as to implement an automatic search function.
In some embodiments, as shown in FIG. 3, address unit 21 includes B memory elements 31; each memory cell 31 stores a row address (e.g., addr0, or Addr1, or Addr2, or Addr3 in fig. 4) and a third status code (e.g., en0, or En1, or En2, or En3 in fig. 4) of one redundant row; wherein the third status code is valid if the redundant row is unoccupied; in the case that the redundant row is occupied, the third status code is invalid. Here Addr0 in different address units indicates addresses of different redundant rows.
The address unit 21 further includes a second logic unit 32; a second logic unit 32, connected to the B memory cells 31, configured to receive B third status codes; outputting invalid first state codes under the condition that all the B third state codes are invalid; or, if at least one third status code is valid, outputting the valid first status code, and outputting the serial number of the storage element 31 with the valid third status code and the forefront ordered storage element as the first-level index code.
It should be appreciated that redundant row addresses are stored in the memory cells in accordance with respective priority sizes. Illustratively, the embodiments of the present disclosure employ low-order priority logic, i.e., the priority of the memory cells 31 (corresponding redundant rows) with smaller order numbers of 0, 1, 2, 3 … … for the memory cells 31 in the same address unit 21 is higher. In addition, in the embodiment of the present disclosure, the high level state "1" is effectively referred to as the high level state "0", but the above rule may be modified according to the actual application scenario, and is not particularly limited.
Referring to fig. 4, if the third status code en0=1, the redundant row (address Addr 0) corresponding to the memory cell 0 is unoccupied, and if the third status code en0=0, the redundant row (address Addr 0) corresponding to the memory cell 0 is occupied.
Taking address unit 0 and low sequence number priority logic as examples, the following applies to the first midamble M 0 N 0 en 0 Specifically speaking: referring to FIG. 4, if En0 of the memory cell 0, en1 of the memory cell 1, en2 of the memory cell 2, and En3 of the memory cell 3 are all 0, then the first status code En 0 =0, representing that the redundant rows managed by address unit 0 are all occupied; if en0=1 of memory element 0, then the first status code En 0 =1, first level index code M 0 N 0 =00, indicating that the redundant row corresponding to bin 0 (address Addr 0) is unoccupied and has the highest priority; if en0=0 for memory element 0 and en1=1 for memory element 1, then the first state code En 0 =1, first level index code M 0 N 0 =01, indicating that the redundant row corresponding to bin 1 (address Addr 1) is unoccupied and highest priority … …, and so on.
In some embodiments, the second intermediate code includes a second state code (EN in fig. 4) and a second level index code (XY in fig. 4), the second state code indicating whether all of the redundant rows managed by the corresponding address sub-module are occupied; in the case where not all of the redundant rows managed by the address submodule are occupied, the second-level index code indicates the redundant group to which the unoccupied and highest-priority redundant row belongs.
It should be noted that the second state code is generally one-bit data, and the second level index code may be multi-bit data, which depends on the value of a. Since fig. 4 is a schematic diagram taking a=4 as an example, the second level index code includes 2-bit data, but this is not a specific limitation.
In some embodiments, the first logic 22 is configured to output an invalid second status code if all a first status codes are invalid; or, in the case that at least one of the first status codes is valid, outputting a valid second status code, and outputting the serial number of the address unit 21 with the first status code valid and the forefront of the first status code as the second-stage index code.
In the embodiment of the present disclosure, in the same address sub-module, the priority of the redundant row managed by the address unit 21 with the smaller sequence number is higher.
Referring to fig. 4, the following details of the logic for determining the second midamble are described:
if en of address unit 0 0 En of address unit 1 1 En of address unit 2 2 And en of address unit 3 3 All are 0, then the second state code en=0, which indicates that all the redundant rows managed by the present address submodule are occupied; meanwhile, since the next address sub-module automatically enters the active state after the redundant line managed by each address sub-module is fully occupied, if the redundant line of the address sub-module in the active state is fully occupied and no new address sub-module enters the active state, the redundant line in the storage block can be considered to be fully occupied (i.e. the address sub-module in the current active state is already the last address sub-module in the storage block); if en of address unit 0 0 =1, then the second state code en=1, the second level index code xy=00, indicating that there are unoccupied redundant rows in the redundancy group managed by address unit 0; if en of address unit 0 0 En of address unit 1 and=0 1 The second state code en=1, the second level index code xy=01, which indicates that the redundant rows managed by address unit 0 are all occupied, the redundant rows managed by address unit 1 are not all occupied … …, and so on.
It should be appreciated that the first logic unit 22 and the second logic unit 32 may each implement the above rule by using a variety of logic devices, such as an and gate, an or gate, an exclusive or gate, and the like.
In some embodiments, as shown in fig. 4, the output unit 23 is specifically configured to determine, as the first level target index code (for example, MN in fig. 4), the first level index code of the address unit corresponding to the second level index code XY; the first-stage target index code MN, the second-stage index code XY and the second state code EN jointly form a candidate repair code.
If the second level index xy=00, the first level index M is output from the address unit 0 0 N 0 Outputting as a first-stage target index code MN; if the second level index code xy=01, the first level index code M output from the address unit 1 1 N 1 And finally, outputting the first-stage target index code MN … …, wherein the first-stage target index code MN, the second-stage index code XY and the second state code EN jointly form a candidate repair code M+N+X+Y+EN of the storage block. As described above, the embodiment of the disclosure describes the working process by using the address submodule in the active state, so that the candidate repair codes output by the address submodule are also candidate repair codes of the whole memory block.
In other words, for the candidate repair codes m+n+x+y+en, EN is used to indicate whether there is an unoccupied redundant row in the present memory block, where x+y indicates a specific address unit and m+n indicates a specific memory cell, so that the unoccupied redundant row address with the highest priority can be obtained from the designated memory cell according to m+n+x+y, thereby implementing the function of automatically searching the redundant row.
In the disclosed embodiment, the output unit 23 may be implemented by a plurality of data selectors, buffers, registers, or flip-flops.
From the above, it can be seen that each memory block has a plurality of address sub-modules of the same architecture as shown in fig. 4, whose function is to display redundant rows that are unoccupied and highest in priority under a preset priority rule (e.g., low sequence number priority logic). Specifically, only 1 of the plurality of address sub-modules is in an active state, and for the address sub-modules in the active state, the address unit 21 managed by the address sub-modules generates a first intermediate code, where the first intermediate code includes a first level index code of 2 bits and a first state code of 1 bit, the first level index code is used for displaying which redundant row is idle (i.e. not occupied), and the first state code is used for displaying whether an idle redundant row exists in the redundant group; then, the first logic unit 22 generates a second intermediate code according to the first status codes of all address units, and similarly, the second intermediate code includes a 2-bit second-level index code and a 1-bit second status code, where the second-level index code is used to display which redundancy row in the redundancy group is free, and the second status code is used to display whether the redundancy row exists in the memory block; finally, the output module 23 outputs the candidate repair codes according to the first intermediate code and the second intermediate code, thereby displaying whether the memory block has available redundant rows and index information of the available redundant rows.
In some embodiments, the target repair code refers to a candidate repair code for the memory block to which the failed row belongs, since it is desired to repair the failed row with redundant rows in the same memory block. As shown in fig. 5, the repair circuit 10 further includes a repair control module 14;
a repair control module 14 configured to output a block selection signal in the event that there is a failed row in the memory; wherein the block selection signal indicates a memory block to which the failed row belongs;
the selection module 12 is specifically configured to receive a block selection signal, and determine a target repair code from a plurality of candidate repair codes based on the block selection signal.
Based on the block selection signal, the selection module 12 outputs the candidate repair code of the memory block to which the failed line belongs as the target repair code, so that the failed line is repaired by using the redundant line pair of the same memory block. The selection module 12, which may also be referred to herein as a Mux, may be implemented by a plurality of data selectors and other devices.
In some implementations, as shown in fig. 5, the repair module 13 is specifically configured to receive a target repair code and a block selection signal; and under the condition that the second state code of the target repair code is effective, determining a target redundant row by using the first-stage target index code of the target repair code, the second-stage index code of the target repair code and the block selection signal, and mapping the signal path of the failure row to the target redundant row to realize redundancy repair processing.
It should be noted that, if the second state code EN is valid, there are available redundant rows in the memory block, so that the failed row can be repaired, and the first-stage target index code MN, the second-stage index code XY and the block selection signal are used to determine the target redundant row; if the second state code EN is not valid, then there are no redundant rows available in the memory block to repair the failed row, requiring other handling strategies to be enabled.
In some embodiments, repair control module 14 is further configured to output a repair enable signal and a failed row address; wherein, in case of a memory having a fail line, the repair enable signal is valid; in the case that the memory has no invalid line, the repair enable signal is invalid;
the repair module comprises a decoding module 131 and an anti-fuse module 132, wherein the anti-fuse module 132 is connected with the repair control module 14 and the decoding module 131;
a decoding module 131 configured to receive the target repair code and the block selection signal; under the condition that a second state code in the target repair code is effective, decoding the first-stage target index code in the target repair code, the second-stage index code in the target repair code and the block selection signal, and outputting a fuse address;
An antifuse module 132 comprising an array of antifuses configured to receive a repair enable signal, a fail row address, and a fuse address; in the case where the repair enable signal is valid, the antifuse array is blown based on the fuse address and the failed row address, so that the signal path of the failed row is mapped to the target redundant row.
It should be noted that, after the antifuse unit corresponding to the fuse address is blown, the signal path of the failed line is mapped onto the target redundant line, and meanwhile, after the antifuse unit is blown, the blown information is automatically sent into the relevant control module, and then the target redundant line replaces the failed line to perform the data storage function.
In summary, the embodiments of the present disclosure relate to a PPR function, and a user generally repairs a failed Row Address (Fail Row Address) through the PPR function, however, the number of redundant rows in the PPR function is limited, the repair efficiency is low, and the user operation space is small. The repair circuitry provided by embodiments of the present disclosure will support users to repair more addresses using additional redundancy, but these addresses are not included in conventional PPR functionality.
Referring to fig. 6, a schematic diagram of a memory according to an embodiment of the present disclosure is shown. As shown in FIG. 6, there are normal memory rows and redundant rows (Red.0-Red 9) in the memory block. When a certain memory row fails, the redundant row address needs to be used to replace the failed row address, and at this time, an Auto-find (Auto-find) is performed by the address module 11 and the selection module 12, so as to generate a target repair code Fuse red. Final (used to indicate the redundant row with the highest priority and free), and the target repair code Fuse red. Final is transmitted to an antifuse array (Anti-Fuse, AF) for repair.
For example, as shown in fig. 6, assuming that redundant rows red.0, red.1, red.2, red.5, and red.6 are all used, the remaining redundant rows are not used, if the memory row addressed to Fail Addr fails, the repair circuit 10 will automatically look up (under low sequence number priority logic) to red.3, providing red.3 as output and transmitting to the antifuse array corresponding to the memory block for redundancy repair.
Referring to fig. 7, a specific structural diagram of a repair circuit 10 according to an embodiment of the disclosure is shown. In particular, the internal structure of the address sub-module in fig. 7 is only schematically shown, and the internal structure of the address sub-module is subject to the text description and fig. 2. In fig. 7, the decoding module 131 is configured to decode the index information (the first level target index address, the second level index address, and the block selection signal) of the redundant row into an address in the antifuse Array (i.e., the fuse address AF Array Addr), the fuse address AF Array Addr is sent to the antifuse module 132, and the antifuse module 132 is configured to control the antifuse Array, and after the Auto find (Auto find) process, the antifuse module 132 can blow the corresponding antifuse cell to implement the redundancy repair function. The repair control module 14 is configured to output a repair enable signal Auto-find_en, register a Fail row address Fail Addr, and output a block selection signal Bank SEL, where the block selection signal Bank SEL is configured to select a candidate repair code Fuse red# of a memory block to which a memory row belongs as a target repair code Fuse Red.
The workflow of repair circuit 10 is as follows: as shown in fig. 7, first, the address module of each memory block outputs a candidate repair code Fuse red#, which indicates the available redundant rows; next, after the Auto-find function is enabled, the repair control module 14 outputs its registered Fail row address Fail Addr, outputs a block selection signal Bank SEL based on the Fail row address Fail Addr, and feeds the block selection signal Bank SEL into the selection module 12; then, the selecting module 12 selects the corresponding candidate repair code Fuse red# to be output as the target repair code Fuse red.final according to the block selection signal Bank SEL, and the decoding module 131 decodes and outputs the Fuse address AF Array Addr according to the target repair code Fuse red.final and the block selection signal Bank SEL; thereafter, the repair control module 14 sends the valid repair enable signal Auto-find_EN and the Fail row address Fail Addr into the antifuse module 132; finally, upon receiving the valid repair enable signal Auto-find_en, the antifuse module 132 performs a blowing process according to the Fail row address Fail Addr and the fuse address AF Array Addr, completing redundancy repair.
The embodiment of the disclosure provides a repair circuit which is applied to a memory comprising a plurality of memory blocks, wherein the repair circuit comprises a plurality of address modules, and each address module outputs a candidate repair code of one memory block; the candidate repair codes indicate that all redundant rows in the storage block are occupied, or the candidate repair codes indicate that redundant rows which are unoccupied and have the highest priority in the storage block; the repair circuit further includes: the selection module is connected with the address modules and is configured to receive a plurality of candidate repair codes; selecting and outputting a target repair code from a plurality of candidate repair codes under the condition that a failure line exists in a memory; and the repair module is connected with the selection module and is configured to carry out redundancy repair processing on the failure line by utilizing the target repair code. In this way, the address module orderly manages the redundant rows in each storage block, so that an automatic searching function of the redundant rows can be provided, specifically, after the memory fails, the repairing circuit can determine the target redundant row through the automatic searching (Auto-Find) function, so that the target redundant row is utilized to repair the failed row, the repairing efficiency and flexibility of the redundant row are improved, and more operation space is provided for users.
In another embodiment of the present disclosure, reference is made to fig. 8, which shows a schematic flow chart of a repair method provided by an embodiment of the present disclosure. The repair method is applied to a memory including a plurality of memory blocks, as shown in fig. 8, and includes:
s401: determining candidate repair codes of each storage block; the candidate repair codes indicate that all redundant rows in the storage block are occupied, or the candidate repair codes indicate that redundant rows in the storage block are unoccupied and have the highest priority.
S402: in the case where there is a fail line in the memory, a target repair code is selected and output from a plurality of candidate repair codes.
S403: and performing redundancy repair processing on the failure line by using the target repair code.
It should be noted that the repair method provided in the embodiment of the disclosure is applied to the repair circuit 10 described above.
In this way, the redundant rows in each storage block are orderly managed, and an Auto-Find (Auto-Find) function of the redundant rows is realized, so that not only is the repair efficiency and flexibility of the redundant rows improved, but also more operation space is provided for users.
In some embodiments, redundant rows in each memory block are divided into multiple redundancy groups, each redundant row having a third status code, and the third status code indicates whether the corresponding redundant row is occupied. The determining candidate repair codes for each memory block includes:
Determining a first intermediate code for each redundancy group based on a third status code for the redundancy row in the redundancy group;
outputting a second intermediate code based on the respective first intermediate codes of the plurality of redundancy groups;
candidate repair codes are determined based on the respective first and second midambles of the plurality of redundancy groups.
In some embodiments, the first intermediate code includes a first state code and a first level index code, the first state code indicating whether all redundant rows in the redundancy group are occupied; in the case where not all of the redundant rows in the redundant set are occupied, the first level index code indicates the redundant row in the redundant set that is unoccupied and has the highest priority.
In some embodiments, the determining the first intermediate code of each redundancy group based on the third status code of the redundancy row in the redundancy group includes:
outputting an invalid first state code under the condition that the third state codes of all redundant rows in the redundant group are invalid; or when the third status code of at least one redundant row in the redundant group is valid, outputting the valid first status code, and outputting the serial number of the redundant row with the valid third status code and the forefront sequence as the first-level index code.
In some embodiments, the second intermediate code includes a second state code and a second level index code, the second state code indicating whether all of the redundant rows managed by the codebook memory block are occupied; in the case where not all the redundant rows managed by the present memory block are occupied, the second-level index code indicates the redundant group to which the unoccupied and highest-priority redundant row belongs.
In some embodiments, the outputting the second intermediate code based on the respective first intermediate codes of the plurality of redundancy groups includes:
outputting an invalid second state code when the first state codes of the plurality of first intermediate codes are all invalid; or outputting a valid second state code under the condition that a first state code in at least one first intermediate code is valid, and outputting the serial number of the redundancy group with the valid first state code and the forefront sequence as a second-stage index code.
In some embodiments, the determining the candidate repair code based on the respective first and second midambles of the plurality of redundancy groups comprises:
determining a first-level index code of the redundancy group corresponding to a second-level index code as a first-level target index code;
the first-stage target index code, the second-stage index code and the second state code form candidate repair codes together.
In some embodiments, the target repair code refers to a candidate repair code of a memory block to which the failed line belongs, and thus, selecting and outputting the target repair code from the plurality of candidate repair codes includes:
outputting a block selection signal in case that a fail line exists in the memory; wherein the block selection signal indicates a memory block to which the failed row belongs;
A target repair code is determined from the plurality of candidate repair codes based on the block selection signal.
In some embodiments, the performing redundancy repair processing on the failed line by using the target repair code includes:
under the condition that a second state code of the target repair code is effective, determining a target redundant row by using a first-stage target index code of the target repair code, a second-stage index code of the target repair code and a block selection signal;
and mapping the signal path of the failure row to the target redundant row to realize redundancy repair processing.
The embodiment of the disclosure provides a repairing method, which orderly manages redundant rows in each storage block, and determines a target redundant row through an Auto-Find (Auto-Find) function after the failed row occurs, so that the failed row is repaired by using the target redundant row, the repairing efficiency and flexibility of the redundant row are improved, and more operation space is provided for users.
In another embodiment of the present disclosure, reference is made to fig. 9, which illustrates a schematic diagram of the composition and structure of a memory 50 provided by an embodiment of the present disclosure. As shown in fig. 9, the memory 50 includes at least a plurality of memory blocks and the repair circuit 10 described above.
In another embodiment of the present disclosure, referring to fig. 10, a schematic diagram of the composition and structure of an electronic device 60 provided by an embodiment of the present disclosure is shown. As shown in fig. 10, the electronic device 60 includes at least the aforementioned memory 50.
The foregoing is merely a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. It should be noted that in this disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment. The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments. The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (15)
1. A repair circuit for use with a memory comprising a plurality of memory blocks, said repair circuit comprising a plurality of address modules, each of said address modules outputting a candidate repair code for said memory block; the candidate repair codes indicate that all redundant rows in the storage block are occupied, or the candidate repair codes indicate that redundant rows which are unoccupied and have the highest priority in the storage block;
the repair circuit further includes:
the selection module is connected with the address modules and is configured to receive the candidate repair codes; selecting and outputting a target repair code from a plurality of candidate repair codes under the condition that a failure line exists in the memory;
the repair module is connected with the selection module and is configured to carry out redundancy repair processing on the failure line by utilizing the target repair code;
the redundant rows in each storage block are divided into a plurality of redundant groups, and the address module is configured to determine first intermediate codes of A redundant groups; outputting a second intermediate code based on the a first intermediate codes; outputting the candidate repair codes based on a number of the first intermediate codes and the second intermediate codes; wherein the first intermediate code indicates that all redundant rows in the redundant group are occupied, or the first intermediate code indicates that redundant rows in the redundant group are unoccupied and have highest priority; the second intermediate code indicates that all redundant rows managed by the address sub-module are occupied, or the second intermediate code is used for indicating that unoccupied redundant rows exist and the redundant group with the highest priority exists.
2. The repair circuit of claim 1, wherein each of the address modules comprises a plurality of address sub-modules;
the address module is configured to output the candidate repair codes by using the address submodule in an active state;
if all the redundant rows managed by the ith-1 address sub-module are occupied and all the redundant rows managed by the ith address sub-module are not occupied, the ith address sub-module is in an active state; and if all the redundant rows managed by the ith address sub-module are occupied, the ith address sub-module exits from the active state.
3. The repair circuit of claim 2, wherein each of said address sub-modules manages a redundancy groups, and each of said redundancy groups comprises B redundancy rows;
the address submodule comprises A address units, and each address unit outputs a first intermediate code of the redundancy group;
the address sub-module further includes:
the first logic unit is connected with the A address units and is configured to receive A first intermediate codes; outputting a second intermediate code based on the a first intermediate codes;
And an output unit configured to output the candidate repair codes based on a number of the first intermediate codes and the second intermediate codes.
4. A repair circuit according to claim 3, wherein,
the first intermediate code comprises a first state code and a first-level index code, wherein the first state code indicates whether all redundant rows in the redundant group are occupied; in the case where not all of the redundant rows in the redundant set are occupied, the first level index code indicates the redundant row in the redundant set that is unoccupied and has the highest priority.
5. The repair circuit of claim 4, wherein the address unit comprises B memory cells;
each of the memory cells stores a row address and a third status code for one of the redundant rows; wherein the third status code is valid if the redundant row is unoccupied; in the case that the redundant row is occupied, the third status code is invalid;
the address unit further comprises a second logic unit;
the second logic unit is connected with the B storage elements and is configured to receive the B third state codes; outputting the invalid first state code under the condition that all B third state codes are invalid; or outputting the valid first state code under the condition that at least one third state code is valid, and outputting the serial number of the storage element with the valid third state code and the forefront ordering as the first-stage index code.
6. The repair circuit of claim 4, wherein,
the second intermediate code comprises a second state code and a second-level index code, and the second state code indicates whether all redundant rows managed by the address submodule are occupied; and in the case that the redundant rows managed by the address sub-module are not all occupied, the second-level index code indicates a redundant group to which the unoccupied and highest-priority redundant row belongs.
7. The repair circuit of claim 6, wherein,
the first logic unit is configured to output the invalid second state code when all of A first state codes are invalid; or outputting the second state code which is valid under the condition that at least one first state code is valid, and outputting the serial number of the address unit which is valid and ordered forefront by the first state code as the second-stage index code.
8. The repair circuit of claim 7, wherein,
the output unit is specifically configured to determine a first-stage index code of the address unit corresponding to the second-stage index code as a first-stage target index code;
the first-stage target index code, the second-stage index code and the second state code jointly form the candidate repair code.
9. The repair circuit according to any one of claims 1 to 8, wherein the target repair code refers to a candidate repair code of a memory block to which the failed row belongs; the repair circuit further comprises a repair control module;
the repair control module is configured to output a block selection signal when a failure line exists in the memory; wherein the block select signal indicates a memory block to which the failed row belongs;
the selection module is specifically configured to receive the block selection signal, and determine the target repair code from a plurality of candidate repair codes based on the block selection signal.
10. The repair circuit of claim 9, wherein the repair circuit comprises a repair circuit,
the repair module is specifically configured to receive the target repair code and the block selection signal; and under the condition that the second state code of the target repair code is effective, determining a target redundant row by using the first-stage target index code of the target repair code, the second-stage index code of the target repair code and the block selection signal, and mapping the signal path of the invalid row to the target redundant row so as to realize redundant repair processing.
11. The repair circuit of claim 10, wherein the repair circuit comprises a repair circuit,
The repair control module is further configured to output a repair enable signal and a failure row address; wherein the repair enable signal is valid in the event that there is a fail line in the memory;
the repair module comprises a decoding module and an anti-fuse module, and the anti-fuse module is connected with the repair control module and the decoding module;
the decoding module is configured to receive the target repair code and the block selection signal; under the condition that a second state code in the target repair codes is effective, decoding the first-stage target index code in the target repair codes, the second-stage index code in the target repair codes and the block selection signal, and outputting a fuse address;
the antifuse module includes an antifuse array configured to receive the repair enable signal, the fail row address, and the fuse address; and in the case that the repair enable signal is valid, performing a blowing process on the antifuse array based on the fuse address and the fail row address, so that a signal path of the fail row is mapped to the target redundancy row.
12. A repair circuit according to claim 3, wherein a=4 and b=4.
13. A repair method for a memory comprising a plurality of memory blocks, the method comprising:
determining candidate repair codes of each storage block; the candidate repair codes indicate that all redundant rows in the storage block are occupied, or the candidate repair codes indicate that redundant rows which are unoccupied and have the highest priority in the storage block;
selecting and outputting a target repair code from a plurality of candidate repair codes under the condition that a failure line exists in the memory;
performing redundancy repair processing on the failure line by using the target repair code;
the redundant rows in each of the memory blocks are divided into a plurality of redundant groups, and the determining the candidate repair codes for each of the memory blocks includes:
determining a first midamble of A redundancy groups; wherein the first intermediate code indicates that all redundant rows in the redundant group are occupied, or the first intermediate code indicates that redundant rows in the redundant group are unoccupied and have highest priority;
outputting a second intermediate code based on the first intermediate code of each of the a redundancy groups; the second intermediate code indicates that all redundant rows managed by the address submodule are occupied, or the second intermediate code is used for indicating that unoccupied redundant rows exist and a redundant group with highest priority exists;
The candidate repair codes are determined based on the first midamble and the second midamble of each of A redundancy groups.
14. A memory comprising a plurality of memory blocks and a repair circuit according to any one of claims 1-12.
15. An electronic device comprising the memory of claim 14.
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| KR20170036884A (en) * | 2015-09-18 | 2017-04-03 | 에스케이하이닉스 주식회사 | Repair circuit, semiconductor apparatus and semiconductor system using the same |
| KR20190060527A (en) * | 2017-11-24 | 2019-06-03 | 삼성전자주식회사 | Semiconductor memory device and method of operating the same |
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| CN114830241A (en) * | 2019-12-31 | 2022-07-29 | 华为技术有限公司 | Failure repair method and device for memory |
| CN114388048A (en) * | 2020-10-20 | 2022-04-22 | 长鑫存储技术有限公司 | Repair circuit and memory |
| US11417411B2 (en) * | 2020-11-04 | 2022-08-16 | Micron Technology, Inc. | Systems and methods for power savings in row repaired memory |
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