CN114830241A - Failure repair method and device for memory - Google Patents
Failure repair method and device for memory Download PDFInfo
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- CN114830241A CN114830241A CN201980103189.8A CN201980103189A CN114830241A CN 114830241 A CN114830241 A CN 114830241A CN 201980103189 A CN201980103189 A CN 201980103189A CN 114830241 A CN114830241 A CN 114830241A
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
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Abstract
The embodiment of the application discloses a failure recovery method and device of a memory, relates to the technical field of chips, and can improve the utilization rate of recovery resources and improve the yield of the memory. The specific scheme is as follows: the device is applied to an apparatus, the apparatus comprises a Logic die, the Logic die comprises a repair memory resource, and the method comprises the following steps: acquiring an access request, wherein the access request comprises a read-write instruction and a destination address of a data unit which is requested to be accessed; and inquiring a failure recovery information table based on the destination address, if the destination address has table entry hit in the failure recovery information table, executing a read-write instruction in the access request to a recovery storage resource corresponding to the hit table entry, wherein the failure recovery information table is used for indicating the failed address in the memory and the recovery storage resource corresponding to the failed address.
Description
The embodiment of the application relates to the technical field of chips, in particular to a failure recovery method and device for a memory.
Dynamic Random Access Memory (DRAM) is a common type of random access memory and has wide applications in the field of memory. With the larger and larger scale of DRAM chips, the working frequency is higher and higher, and the chips have local failure probability of different degrees in the chip production process or in the chip working state.
One existing method for repairing failed cells of a DRAM chip is to allocate redundant memory resources at each Bank in the DRAM chip, where the redundant memory resources are typically allocated 16 redundant rows every 2K rows, and the minimum granularity of redundant replacement is a row. However, in the method, as the redundant line storage resources are uniformly deployed in each Bank according to the proportion of 16 redundancies allocated in every 2K lines, the repair capability for non-uniformly distributed failure scenes is limited. For example, when a data unit failure occurs in 17 rows of a group of 2K rows sharing 16 redundant row resources, even if other banks of the chip have no failed units at all, the chip cannot be repaired completely. Therefore, the method has limited repair capability and low utilization rate of redundant storage resources.
Disclosure of Invention
The embodiment of the application provides a failure recovery method and device for a memory, which can improve the utilization rate of recovery resources and improve the yield of the memory.
In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:
in a first aspect of the embodiments of the present application, a method for repairing a memory failure is provided, where the method is applied to an apparatus, where the apparatus includes a Logic die, and the Logic die includes a repair memory resource, where the method includes: acquiring an access request, wherein the access request comprises a read-write instruction and a destination address of a data unit which is requested to be accessed; and inquiring a failure recovery information table based on the destination address, if the destination address has table entry hit in the failure recovery information table, executing a read-write instruction in the access request to a recovery storage resource corresponding to the hit table entry, wherein the failure recovery information table is used for indicating a failed address in the memory and the recovery storage resource corresponding to the failed address. Based on the scheme, the restoration storage resources are intensively deployed in the Logic die, so that when the failure of the accessed destination address is determined, the read-write instruction in the access request can be executed through the restoration storage resources. Therefore, when the failed data units in the memory are uniformly or nonuniformly distributed, the read-write instruction in the access request can be executed through the centrally deployed restoration storage resource, and therefore the utilization rate of the restoration storage resource is improved. It can be understood that the repair storage resource may be a redundant storage resource in a memory, and the failure repair information table may be implemented by one table or two tables, which is not limited in this embodiment.
With reference to the first aspect, in a possible implementation manner, when the read-write instruction is a write instruction, the executing the read-write instruction in the access request to the repair storage resource corresponding to the hit table entry includes: sending a first repair instruction to a read-write data repair module, wherein the first repair instruction comprises the destination address and the write instruction; receiving write data from the read-write data repair module and the destination address; and storing the write data in the repair storage resource corresponding to the hit table entry. Based on the scheme, the write data can be stored in the repair storage resource corresponding to the hit table entry.
With reference to the first aspect and the foregoing possible implementation manner, in another possible implementation manner, when the read-write instruction is a read instruction, the executing the read-write instruction in the access request to the repair storage resource corresponding to the hit table entry includes: reading the read data stored in the repair storage resource corresponding to the hit table entry; and sending a second repair instruction to the read-write data repair module, wherein the second repair instruction comprises the destination address, the read data and the read instruction. Based on the scheme, the read data stored in the repair storage resource corresponding to the hit table entry can be read, and the read data is sent to the read-write data repair module, so that the read-write data repair module sends the read data to an external data bus to complete the process of the read request.
With reference to the first aspect and the foregoing possible implementation manner, in another possible implementation manner, the failure repair information table includes a first failure information table and a first repair data table, where an entry in the first failure information table is used to indicate a failed first address in a memory, and an entry in the first repair data table is used to indicate a repair storage resource corresponding to the failed first address. Based on the scheme, the failure information table can be realized by two tables, wherein the first failure information table stores the failed first address, and the first repair data table stores the repair storage resource corresponding to the failed first address.
With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the first failure information table is stored in a content addressable memory CAM, and the first repair data table is stored in a static random access memory SRAM. Based on this scheme, the first failure information table and the first repair data table may be stored in different memories. It will be appreciated that when the first table of failure information is stored in the CAM, since the CAM is a content addressable memory, the destination address can be directly looked up in the CAM to determine whether the destination address has an entry hit in the CAM.
With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, an entry in the CAM is used to store a failed first address, and a position of the entry in the CAM corresponds to address information of the repair storage resource. Based on the scheme, the position of the table entry in the CAM corresponds to the address information of the repair storage resource in the first repair data table.
With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the first failure information table and the first repair data table are stored in an SRAM. Based on the scheme, the first failure information table and the first repair data table can be stored in different SRAMs.
With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the querying a failure recovery information table based on the destination address includes: converting the destination address into a reference address by adopting a preset algorithm, wherein the address length of the reference address corresponds to the size of the first failure information table; inquiring the first failure information table based on the reference address; correspondingly, the step of the destination address having an entry hit in the failover information table includes: the destination address has a hit in an entry in the first table of invalidation information. Based on the scheme, when the first failure information table is stored in the SRAM, the destination address is converted into the reference address with the address length corresponding to the depth of the SRAM by performing address conversion on the destination address, and then the first failure information table is inquired based on the reference address.
With reference to the first aspect and the possible implementations described above, in another possible implementation, the preset algorithm is a hash algorithm, a double hash algorithm, or a multiple hash bucket algorithm. Based on the scheme, the destination address can be converted into the reference address through a hash algorithm, a double hash algorithm or a multi-hash bucket algorithm. It is understood that different invalid addresses may be converted into the same reference address by using a hashing algorithm, that is, hash collisions may occur between different invalid addresses during address conversion. In order to reduce the probability of hash collision, a double hash algorithm or a multi-hash bucket algorithm may be used for address conversion.
With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the failure repair information table further includes a second failure information table and a second repair data table, where an entry in the second failure information table is used to indicate a failed second address in the memory, and an entry in the second repair data table is used to indicate a repair storage resource corresponding to the failed second address. Based on the scheme, the failure repair information table may further include a second failure information table storing a second address that fails, and a second repair data table storing a repair storage resource corresponding to the second address that fails. It is understood that the invalidated second address in the second invalidation information table is different from the invalidated first address in the first invalidation information table, and the invalidated second address may be an address which has a hash collision with the invalidated first address in the address translation.
With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the second failure information table and the second repair data table are stored in a register. Based on this scheme, a second failure information table and a second repair data table are stored in registers.
With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the querying a failure recovery information table based on the destination address further includes: if the destination address is not hit in the first failure information table, querying the second failure information table based on the destination address; correspondingly, the step of the destination address having an entry hit in the failover information table includes: the destination address has a hit in an entry in the second table of invalidation information. Based on the scheme, under the condition that the destination address does not have the table entry hit in the first failure information table, the second failure information table can be further inquired based on the destination address, and whether the destination address has the table entry hit in the second failure information table or not is determined, so that whether the destination address fails or not can be determined more accurately when address conversion conflicts.
With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the repair granularity of the repair memory resource is less than or equal to 2 times the bit Width DQ Width of the data bus, or N bytes, where N is greater than or equal to 1. Based on the scheme, the repair granularity of the repair storage resources can be finer, so that the repair storage resources are suitable for different scenes that failure units are scattered or not scattered among lines, and the refinement of the repair granularity can further improve the utilization rate of the repair storage resources.
In a second aspect of the embodiments of the present application, there is provided an integrated circuit, the integrated circuit comprising a logic die, the logic die comprising a memory interface, a memory controller and repair memory resources, the memory controller being configured to: managing a failure recovery information table, wherein the failure recovery information table is used for indicating a failed address in a memory and a recovery storage resource corresponding to the failed address; acquiring an access request, wherein the access request comprises a read-write command and a destination address of a data unit requested to be accessed; and inquiring the failure recovery information table based on the destination address, and if the destination address has a hit table entry in the failure recovery information table, executing the read-write command to a recovery storage resource corresponding to the hit table entry.
With reference to the second aspect, in a possible implementation manner, when the read/write instruction is a write instruction, the memory controller is specifically configured to: sending a first repair instruction to a read-write data repair module, wherein the first repair instruction comprises the destination address and the write instruction; receiving write data from the read-write data repair module and the destination address; and storing the write data in the repair storage resource corresponding to the hit table entry.
With reference to the second aspect and the foregoing possible implementation manner, in another possible implementation manner, when the read-write instruction is a read instruction, the memory controller is specifically further configured to: reading the read data stored in the repair storage resource corresponding to the hit table entry; and sending a second repair instruction to the read-write data repair module, wherein the second repair instruction comprises the destination address, the read data and the read instruction.
With reference to the second aspect and the foregoing possible implementation manner, in another possible implementation manner, the failure repair information table includes a first failure information table and a first repair data table, where an entry in the first failure information table is used to indicate a failed first address in a memory, and an entry in the first repair data table is used to indicate a repair storage resource corresponding to the failed first address.
With reference to the second aspect and the foregoing possible implementation manners, in another possible implementation manner, the first failure information table is stored in a content addressable memory CAM, and the first repair data table is stored in a static random access memory SRAM.
With reference to the second aspect and the foregoing possible implementation manner, in another possible implementation manner, the entry in the CAM is used to store a failed first address, and a position of the entry in the CAM corresponds to address information of the repair storage resource.
With reference to the second aspect and the foregoing possible implementation manners, in another possible implementation manner, the first failure information table and the first repair data table are stored in an SRAM.
With reference to the second aspect and the foregoing possible implementation manners, in another possible implementation manner, the memory controller is further specifically configured to: converting the destination address into a reference address by adopting a preset algorithm, wherein the address length of the reference address corresponds to the size of the first failure information table; inquiring the first failure information table based on the reference address; correspondingly, the step of the destination address having an entry hit in the failover information table includes: the destination address has a hit in an entry in the first table of invalidation information.
With reference to the second aspect and the foregoing possible implementation manners, in another possible implementation manner, the preset algorithm is a hash algorithm, a double hash algorithm, or a multiple hash bucket algorithm.
With reference to the second aspect and the foregoing possible implementation manner, in another possible implementation manner, the failure repair information table further includes a second failure information table and a second repair data table, where an entry in the second failure information table is used to indicate a failed second address in the memory, and an entry in the second repair data table is used to indicate a repair storage resource corresponding to the failed second address.
With reference to the second aspect and the foregoing possible implementation manners, in another possible implementation manner, the second failure information table and the second repair data table are stored in a register.
With reference to the second aspect and the foregoing possible implementation manners, in another possible implementation manner, the memory controller is further specifically configured to: if the destination address is not hit in the first failure information table, querying the second failure information table based on the destination address; correspondingly, the step of the destination address having an entry hit in the failover information table includes: the destination address has a hit in an entry in the second table of invalidation information.
With reference to the second aspect and the foregoing possible implementation manners, in another possible implementation manner, the repair granularity of the repair memory resource is less than or equal to 2 times the bit Width DQ Width of the data bus, or N bytes, where N is greater than or equal to 1.
In a third aspect of the embodiments of the present application, there is provided a failure recovery apparatus for a memory, which is applied to a chip, where the chip includes a Logic die, and the Logic die includes a recovery memory resource, where the apparatus includes: the device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is used for acquiring an access request which comprises a read-write instruction and a destination address of a data unit requested to be accessed; and the processing unit is used for inquiring a failure recovery information table based on the destination address, if the destination address has an entry hit in the failure recovery information table, executing a read-write instruction in the access request to a recovery storage resource corresponding to the hit entry, and the failure recovery information table is used for indicating a failed address in a memory and the recovery storage resource corresponding to the failed address.
With reference to the third aspect, in a possible implementation manner, when the read-write instruction is a write instruction, the apparatus further includes a communication unit, where the communication unit is configured to send a first repair instruction to a read-write data repair module, where the first repair instruction includes the destination address and the write instruction; receiving the write data from the read-write data repair module and the destination address; the processing unit is specifically configured to store the write data in the repair storage resource corresponding to the hit entry.
With reference to the third aspect and the foregoing possible implementation manners, in another possible implementation manner, when the read-write instruction is a read instruction, the apparatus further includes a communication unit, and the processing unit is further configured to read data stored in the repair storage resource corresponding to the hit table entry; the communication unit is configured to send a second repair instruction to the read-write data repair module, where the second repair instruction includes the destination address, the read data, and the read instruction.
With reference to the third aspect and the foregoing possible implementation manner, in another possible implementation manner, the failure repair information table includes a first failure information table and a first repair data table, where an entry in the first failure information table is used to indicate a failed first address in a memory, and an entry in the first repair data table is used to indicate a repair storage resource corresponding to the failed first address.
With reference to the third aspect and the foregoing possible implementation manners, in another possible implementation manner, the first failure information table is stored in a content addressable memory CAM, and the first repair data table is stored in a static random access memory SRAM.
With reference to the third aspect and the foregoing possible implementation manners, in another possible implementation manner, the entry in the CAM is used to store a failed first address, and a position of the entry in the CAM corresponds to address information of the repair storage resource.
With reference to the third aspect and the foregoing possible implementation manners, in another possible implementation manner, the first failure information table and the first repair data table are stored in an SRAM.
With reference to the third aspect and the foregoing possible implementation manners, in another possible implementation manner, the processing unit is specifically configured to: converting the destination address into a reference address by adopting a preset algorithm, wherein the address length of the reference address corresponds to the size of the first failure information table; based on the reference address, the first failure information table is queried.
With reference to the third aspect and the foregoing possible implementation manners, in another possible implementation manner, the preset algorithm is a hash algorithm, a double hash algorithm, or a multiple hash bucket algorithm.
With reference to the third aspect and the foregoing possible implementation manners, in another possible implementation manner, the failure repair information table further includes a second failure information table and a second repair data table, where an entry in the second failure information table is used to indicate a failed second address in the memory, and an entry in the second repair data table is used to indicate a repair storage resource corresponding to the failed second address.
With reference to the third aspect and the foregoing possible implementation manners, in another possible implementation manner, the second failure information table and the second repair data table are stored in a register.
With reference to the third aspect and the foregoing possible implementation manners, in another possible implementation manner, the processing unit is further configured to: if the destination address is not hit in the first failure information table, the second failure information table is queried based on the destination address.
With reference to the third aspect and the foregoing possible implementation manners, in another possible implementation manner, the repair granularity of the repair memory resource is less than or equal to 2 times the bit Width DQ Width of the data bus, or N bytes, where N is greater than or equal to 1.
In a fourth aspect of the embodiments of the present application, an apparatus for repairing a memory failure is provided, where the apparatus includes a Logic die, where the Logic die includes a failure repair control module and a repair memory resource; the failure recovery control module is configured to: acquiring an access request, wherein the access request comprises a read-write instruction and a destination address of a data unit which is requested to be accessed; and inquiring a failure recovery information table based on the destination address, if the destination address has an entry hit in the failure recovery information table, executing a read-write instruction in the access request to a recovery storage resource corresponding to the hit entry, wherein the failure recovery information table is used for indicating a failed address in a memory and the recovery storage resource corresponding to the failed address.
With reference to the fourth aspect, in a possible implementation manner, the logic die further includes a read-write data repair module, and when the read-write instruction is a write instruction, the failure repair control module is specifically configured to send a first repair instruction to the read-write data repair module, where the first repair instruction includes the destination address and the write instruction; the read-write data repair module is configured to receive the first repair instruction, and send write data and the destination address to the failure repair control module; the failure recovery control module is further specifically configured to receive the write data and the destination address from the read-write data recovery module, and store the write data in a recovery storage resource corresponding to the hit table entry.
With reference to the fourth aspect and the foregoing possible implementation manner, in another possible implementation manner, the logic die further includes a read-write data repair module, where when the read-write instruction is a read instruction, the failure repair control module is specifically configured to read data stored in a repair storage resource corresponding to the hit table entry, and send a second repair instruction to the read-write data repair module, where the second repair instruction includes the destination address, the read data, and the read instruction; the read-write data recovery module is configured to receive the second recovery instruction from the failure recovery control module.
With reference to the fourth aspect and the foregoing possible implementation manner, in another possible implementation manner, the failure repair information table includes a first failure information table and a first repair data table, where an entry in the first failure information table is used to indicate a failed first address in a memory, and an entry in the first repair data table is used to indicate a repair storage resource corresponding to the failed first address.
With reference to the fourth aspect and the foregoing possible implementation manners, in another possible implementation manner, the first failure information table is stored in a content addressable memory CAM, and the first repair data table is stored in a static random access memory SRAM.
With reference to the fourth aspect and the foregoing possible implementation manners, in another possible implementation manner, an entry in the CAM is used to store a failed first address, and a position of the entry in the CAM corresponds to address information of the repair storage resource.
With reference to the fourth aspect and the foregoing possible implementation manners, in another possible implementation manner, the first failure information table and the first repair data table are stored in an SRAM.
With reference to the fourth aspect and the foregoing possible implementation manners, in another possible implementation manner, the failure recovery control module is specifically configured to: converting the destination address into a reference address by adopting a preset algorithm, wherein the address length of the reference address corresponds to the size of the first failure information table; based on the reference address, the first failure information table is queried.
With reference to the fourth aspect and the foregoing possible implementation manners, in another possible implementation manner, the preset algorithm is a hash algorithm, a double hash algorithm, or a multiple hash bucket algorithm.
With reference to the fourth aspect and the foregoing possible implementation manners, in another possible implementation manner, the failure repair information table further includes a second failure information table and a second repair data table, where an entry in the second failure information table is used to indicate a failed second address in the memory, and an entry in the second repair data table is used to indicate a repair storage resource corresponding to the failed second address.
With reference to the fourth aspect and the foregoing possible implementation manners, in another possible implementation manner, the second failure information table and the second repair data table are stored in a register.
With reference to the fourth aspect and the foregoing possible implementation manners, in another possible implementation manner, the failure recovery control module is further specifically configured to: if the destination address is not hit in the first failure information table, the second failure information table is queried based on the destination address.
With reference to the fourth aspect and the foregoing possible implementation manners, in another possible implementation manner, the repair granularity of the repair memory resource is less than or equal to 2 times the bit Width DQ Width of the data bus, or N bytes, where N is greater than or equal to 1.
With reference to the fourth aspect and the possible implementation manners, in another possible implementation manner, the Logic die further includes a self-checking module, a controller, and an address registration module, where the self-checking module is connected to the controller, the address registration module, and the failover control module, respectively; the self-checking module is used for sending a self-checking request to the controller; the controller is used for receiving the self-checking request; the self-checking module is also used for sending an address to be detected to the address registering module; the self-checking module is further configured to determine that the address to be detected is a failed address based on a preset self-checking algorithm.
With reference to the fourth aspect and the foregoing possible implementation manners, in another possible implementation manner, the self-checking module is further configured to send the failed address to the failure recovery control module; the failure repair control module is further configured to receive a failure address from the self-checking module, and store the failure address in the failure repair information table.
The descriptions of the effects of the various implementations of the second aspect to the fourth aspect may refer to the descriptions of the corresponding effects of the various implementations of the first aspect, and are not repeated here.
In a fifth aspect of the embodiments of the present application, there is provided an apparatus in the form of a chip, where the apparatus includes a processor in a structure, and the processor is configured to execute the method for repairing the memory failure.
FIG. 1 is a schematic structural diagram illustrating a failure recovery scheme for a memory according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of another failure recovery scheme for a memory according to an embodiment of the present disclosure;
fig. 3 is a schematic flowchart illustrating a method for repairing a failure of a memory according to an embodiment of the present disclosure;
FIG. 4 is a flowchart illustrating another method for repairing a memory failure according to an embodiment of the present disclosure;
FIG. 5 is a first schematic diagram illustrating an application of a method for repairing a memory failure according to an embodiment of the present disclosure;
fig. 6 is a schematic application diagram of a failure recovery method for a memory according to an embodiment of the present disclosure;
FIG. 7 is a flowchart illustrating another method for repairing a failure of a memory according to an embodiment of the present disclosure;
FIG. 8 is a flowchart illustrating another method for repairing a failure of a memory according to an embodiment of the present disclosure;
FIG. 9 is a flowchart illustrating another method for repairing a failure of a memory according to an embodiment of the present disclosure;
Fig. 10 is a schematic composition diagram of a failure recovery control device according to an embodiment of the present application;
fig. 11 is a schematic diagram of an integrated circuit according to an embodiment of the present disclosure.
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b, a and c, b and c or a and b and c, wherein a, b and c can be single or multiple.
It is noted that, in the present application, words such as "exemplary" or "for example" are used to mean exemplary, illustrative, or descriptive. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present relevant concepts in a concrete fashion.
Illustratively, as the size of the DRAM chip is larger and larger, the operating frequency is higher and higher, and the chip has different degrees of local failure probability in the chip production process and the chip operating state. In order to improve the yield of the chip, a method for repairing a failed cell of a DRAM chip is shown in fig. 1, and the minimum granularity of redundancy repair in a DRAM die (DRAM die) is a row because only simple control logic can be implemented in the DRAM die by uniformly distributing redundancy storage resources for failure repair, which are usually configured with 16 redundancy rows every 2K rows, in each Bank (e.g., B0 to Bn in fig. 1) or Sub Bank in the DRAM chip.
As shown in FIG. 1, in chip test mode, a self-test operation may be initiated by the self-test module in a configurable algorithm. In the self-Checking process of the DRAM, a failed data unit is found through an Error Checking and Correcting (ECC) mechanism, and the information record of the failed data unit is reported to test software. And the determined failure repair strategy is issued to the redundancy control register or the fusing control circuit of each Bank of the DRAM by test software. The entire row of memory cells corresponding to a failed data cell needs to be replaced entirely by the redundant row. Under the normal working mode of the chip, when the read-write operation reaches a certain failure row address of a certain Bank, the DRAM can carry out the read-write operation on the storage space of the redundancy row, and the replacement operation of the redundancy row outside the chip is not sensed.
However, in the method, as the redundant line storage resources are uniformly deployed in each Bank according to the proportion of 16 redundancies allocated in every 2K lines, the repair capability for non-uniformly distributed failure scenes is limited. For example, when a data cell failure occurs in 17 rows of a group of 2K rows sharing 16 redundant row resources, the chip cannot be completely repaired even if other banks of the chip have no failed cells at all. Therefore, the method has limited repair capability and low utilization rate of redundant storage resources. And because the repair granularity of the method is a row (8Kbit), even if only 1bit in a row fails, the whole row needs to be replaced by a redundant row. For a scene in which the failed cells are discretely distributed among rows, the repair capability is limited. For example, when 17 single bits of data in a group of 2K rows sharing 16 redundant row resources fail and the 17 failed bits belong to 17 different rows, the chip cannot be fully repaired.
In order to adapt to different scenes that failure units are uniformly or non-uniformly distributed among banks, improve the utilization rate of repair resources, improve the repair capability of a chip and further improve the yield of the chip, the embodiment of the application provides a failure repair method of a memory.
For example, the failure recovery method of the memory may be applied to a chip including a Logic die (Logic die), where the Logic die includes a repair memory resource, and the repair memory resource is a redundant memory resource in the memory. When the data unit in the memory fails, the corresponding read-write instruction can be executed through the repair memory resource.
An apparatus as shown in fig. 2 includes a plurality of DRAM dies (DRAM die) for executing read and write commands and a Logic die for implementing more complex control Logic.
Illustratively, the Logic die includes a repair storage resource, the repair storage resource is a redundant storage resource in the memory, and the repair storage resource is centrally deployed in the Logic die. That is, when a data unit requested to be accessed fails, the Bank or Sub Bank or Channel where the failed data unit is located may be not distinguished, and the read-write instruction in the access request may be executed through the repair storage resource centrally deployed in the Logic die. Therefore, the utilization rate of the repair storage resources can be improved when the failed data units in the memory are uniformly or nonuniformly distributed.
As shown in fig. 2, the Logic die may include hardware modules such as a failure recovery control module, a read-write data recovery module, a self-checking module, a controller, and an address registration module.
The failure recovery control module is used for acquiring the access request, determining whether a destination address of the data unit which is requested to be accessed is a failure address, and executing a read-write instruction in the access request to a recovery storage resource corresponding to the destination address when the destination address is determined to be the failure address. The repair storage resources may be centrally deployed in the failover control module. The failure recovery control module may store a failure recovery information table, where an entry in the failure recovery information table is used to indicate a failed address in the memory and a recovery storage resource corresponding to the failed address.
For example, the failure recovery information table may be implemented by using one table or two tables, which is not limited in this embodiment of the application. When the failure repair information is implemented with two tables, the failure repair information table includes a failure information table and a repair data table. The entry in the failure information table is used for indicating a failed address in the memory, and the entry in the repair data table is used for indicating a repair storage resource corresponding to the failed address. The address of the failure in the failure information table can come from the self-checking module.
For example, the fail-over control module may be a memory controller.
And the read-write data repairing module is used for reading the data of the DRAM die or writing the write data into the DRAM. And under the condition that the destination address is the failure address, the read-write data repair module is also used for receiving a repair instruction sent by the failure repair control module and sending the read data to an external data bus based on the repair instruction, or sending the write data to the failure repair control module based on the repair instruction so that the failure repair control module writes the write data into a repair data table.
And the self-checking module is used for detecting the failed address in the memory. When detecting whether the data unit to be detected fails, the self-checking module may send a self-checking request to the controller, send an address (which may also be referred to as a self-checking address) of the data unit to be detected to the address registering module, and determine whether the data unit to be detected fails based on an ECC error detection mechanism. For example, the memory carries ECC check bits when data is written, and checks whether an ECC check error exists when data is read back. The ECC check can be completed in the read-write data repair module, and the self-check module only needs to collect ECC error detection information. The ECC error detection information may include an error address and error data. When the self-checking module determines that the data unit to be detected fails, the self-checking module can send the failed address to the failure recovery control module. Optionally, the self-checking module may perform self-checking once every other period of time, or may perform self-checking when the memory is idle, so as to update the address of the failed data unit in the memory.
And the controller is used for processing the read-write operation of the external memory. The controller can process external read-write operation and can also process self-checking requests sent by the self-checking module.
And the address registering module is used for acquiring the destination address of the data unit which is requested to be accessed and the self-checking address sent by the self-checking module. The failure repair control module can also grab the address of the data unit accessed by the read-write operation request from the address register module.
It can be understood that, in the apparatus provided in this embodiment of the present application, since the repair storage resources are centrally deployed in the Logic die, when the failure units of the memory are non-uniformly distributed, the non-uniformly distributed failure units can all execute corresponding read-write instructions through the centrally deployed repair storage resources, so that the utilization rate of the repair storage resources is improved, and the yield of the chip is improved.
For example, in the embodiment of the present application, the repair storage resource is deployed in a failure repair control module in the Logic die, and the failure repair control module may implement a more complex control Logic. The repair granularity for repairing the storage resource in the embodiment of the application can be finer. Illustratively, the size of the repair granularity of the repair memory resource may be less than or equal to 2 times the size of the bit Width DQ Width of the data bus, or N bytes, N being greater than or equal to 1. The DQ Width is determined by a design architecture of the DRAM, and the DQ Width may be 64 bits, 128 bits, or other sizes, which is not limited in the embodiment of the present application. In the following examples, only the DQ Width is described as an example of 128 bits. For example, the size of the smallest data unit requested to be accessed by an access request may be 2 times the size of DQ Width, e.g., 256 bits.
For example, the repair granularity of the repair memory resource may be 2 times DQ Width (256 bits), or may also be 8 bits (1 Byte). It should be noted that the repair granularity in the embodiment of the present application may be finer than the repair granularity of the row redundancy.
It can be understood that, because the repair granularity of the embodiment of the present application is finer than the repair granularity of the row redundancy, the method is suitable for different scenarios where the failure unit is scattered or non-scattered among rows, and the refinement of the repair granularity can further improve the utilization rate of the repair storage resource.
For example, referring to fig. 2, as shown in fig. 3, a method for repairing a memory failure provided in an embodiment of the present application may be applied to the Logic die, as shown in fig. 3, and the method may include steps S301 to S303.
S301, obtaining an access request.
It is understood that the step S301 may be executed by the failure recovery control module shown in fig. 2, and the failure recovery control module may be a memory controller.
Illustratively, the access request may include a read-write instruction and a destination address of the data unit requested for access. The destination address may be 26 bits. For example, the destination Address may be composed of a Bank Address of 6 bits (Bank Address), a Row Address of 14 bits (Row Address), and a Column Address of 6 bits (Column Address). The address length of the destination address of the data unit requested to be accessed is not limited in the embodiment of the present application, and is only exemplified by the address length being 26 bits.
For example, the read/write instruction in the access request may be a read instruction or a write instruction, which is not limited in this embodiment of the application.
For example, the obtaining, by the failover control module, an access request may include: the failure repair control module obtains an access request for each access to the memory. Each access request to the memory is visible to the failover control module.
S302, based on the destination address, inquiring the failure recovery information table, and determining that the destination address has table entry hit in the failure recovery information table.
It is understood that the step S302 may be executed by the failure recovery control module shown in fig. 2, and the failure recovery control module may be a memory controller.
The entry in the failure recovery information table is used to indicate a failed address in the memory and a recovery storage resource corresponding to the failed address. The address of the failure stored in the failure repair information table may be detected by the self-test module.
For example, the content indicated by the failure recovery information table may be implemented by one table, or may be implemented by two tables.
For example, when the fail-over information table is implemented by a table, the fail-over information table may be stored in a Static Random Access Memory (SRAM). And the table entry of the failure repair information table in the SRAM is used for indicating the failed address in the memory and the repair storage resource corresponding to the failed address.
For another example, when the failure recovery information table is implemented by two tables, the failure recovery information table may include a first failure information table and a first recovery data table, where an entry in the first failure information table is used to indicate a failed first address in the memory, and an entry in the first recovery data table is used to indicate a recovery storage resource corresponding to the failed first address.
In the embodiment of the present application, it is not limited whether the failure recovery information table is implemented by using one table or two tables. The following embodiments are described only by taking the failure repair information table as an example implemented by two tables.
In a first implementation manner, the first failure information table is stored in the first SRAM, and the first repair data table is stored in the second SRAM. The depths (depth) of the first SRAM and the second SRAM are the same, namely, the position of the failed first address in the first failure information table corresponds to the position of the repair storage resource corresponding to the failed first address in the first repair data table.
In a second implementation manner, the first failure information table is stored in a content-addressable memory (CAM), and the first repair data table is stored in an SRAM. The entries in the CAM are used for storing the failed first addresses, and the positions of the entries in the CAM correspond to the address information of the repair storage resources.
Corresponding to the first implementation manner, when the first failure information table is stored in the first SRAM, as shown in fig. 4, the step S302 of querying the failure repair information table based on the destination address and determining that the destination address has an entry hit in the failure repair information table includes steps S3021 to S3023.
And S3021, converting the destination address into a reference address by adopting a preset algorithm.
The address length of the reference address corresponds to the size of the first revocation information table. For example, the address length of the reference address corresponds to the depth (depth) of the first failure information table.
Illustratively, the address length of the destination address is 26 bits, and the size of the first SRAM is 26 bits × 1K, that is, 1K (1K — 1024) failed addresses can be stored in the first SRAM, and the address length of each failed address is 26 bits. If the destination address is to be determined to be the failed address in the first failure information table, the address length of 26 bits needs to be compressed to the address length of 10 bits, and since the address length of 10 bits matches with the depth of the SRAM, the lookup can be performed in the first failure information table based on the address length of 10 bits.
For example, in step S3021, a hash algorithm may be used to compress the address length of 26 bits into an address length of 10 bits. However, when the hash algorithm is used to compress the 26-bit address length to the 10-bit address length, there is a possibility that different 26-bit address lengths are compressed to the same 10-bit address length, that is, there is a problem of hash collision with a certain probability. Therefore, the preset algorithm can adopt a double hash algorithm or a multi-hash bucket algorithm to reduce the probability of hash collision. For example, an address X of 26 bits is compressed to an address Z of 10 bits by using a hash algorithm, and an address Y of 26 bits is also compressed to an address Z of 10 bits by using a hash algorithm. If both the 26-bit address X and the 26-bit address Y are addresses of failed data units, then during address compression, the address X may be compressed to a 10-bit address by using one hash algorithm, and the address Y may be compressed to a 10-bit address by using another hash algorithm, so as to reduce the probability of collision after the address X and the address Y are compressed. The specific algorithm for converting the destination address into the reference address in the embodiment of the present application is not limited, and is only an exemplary illustration here.
For example, as shown in fig. 5, a hash algorithm may be used to convert the destination address of 26 bits into a reference address of 10 bits, which is 0000000010.
It should be noted that, in the case where the address length of the destination address does not match the size of the first SRAM storing the first failure information table, the destination address needs to be converted into a reference address whose address length matches the size of the first SRAM storing the first failure information table.
Optionally, the size of the first SRAM storing the first failure information table may also be 27 bits × 1K, where 1bit is an indication bit, and different values of the indication bit are used to indicate whether an address indicated by a certain entry in the first SRAM is a failed address. When the indication bit indicates that the address indicated by an entry is a failed address and the destination address hits in the entry, it may be determined that the destination address is a failed address, i.e., the data unit requested to be accessed is failed.
And S3022, inquiring the first failure information table based on the reference address.
For example, as shown in fig. 5, based on the reference address 0000000010, the first failure information table is queried, and the address of the failure stored in the first failure information table is determined to be the address C. If the destination address is also address C, it is determined that the destination address has a hit in an entry in the first table of invalidation information.
For example, when the entry of the destination address hits in the first invalidation information table, the destination address may be determined to be an invalidated address. That is, the data unit requesting access is invalidated.
For example, if in step S3022, the first failure information table is queried based on the reference address, it is determined that the destination address has a hit in the first failure information table, and step S303 is continued. If the first failure information table is queried based on the reference address in step S3022, it is determined that the destination address does not have a hit in the first failure information table, and step S3023 is continued.
For example, in step S3022, if the first invalidation information table is queried based on the reference address, it is determined that the destination address does not have a hit in the first invalidation information table, and it cannot be determined that the destination address is definitely an address that has not been invalidated. Since there is a possibility that the hash collision problem still exists when the address of 26 bits is converted into the address of 10 bits by using the preset algorithm in step S3021.
For example, the address X of 26bit and the address Y of 26bit are compressed to the address Z of 10bit by using a hash algorithm, and the address X of 26bit and the address Y of 26bit are both failed addresses, then the position corresponding to the address Z of 10bit in the first failure information table only stores the address X or the address Y, and the position corresponding to the address Z of 10bit in the first failure information table only stores the address Y as an example. After compressing the destination address X into a 10-bit address Z, the address X has no entry hit in the first invalidation information table, but it cannot be determined that the destination address must not be invalidated.
In order to solve the problem that the hash collision may still exist when the address conversion is performed in step S3021. The failure repair information table may further include a second failure information table and a second repair data table, where an entry in the second failure information table is used to indicate a failed second address in the memory, and an entry in the second repair data table is used to indicate a repair storage resource corresponding to the failed second address. It is understood that the invalidated second address in the second invalidation information table is different from the invalidated first address in the first invalidation information table, and the invalidated second address may be an address which has a hash collision with the invalidated first address in the address translation. For example, when performing address conversion, both the failing address X of 26 bits and the failing address Y of 26 bits are converted into the address Z of 10 bits, so that one of the failing addresses X of 26 bits and the failing address Y of 26 bits can be stored in the first failing information table, and the other one can be stored in the second failing information table.
Optionally, if the first failure information table is queried based on the destination address, and the destination address is determined to miss in the first failure information table, step S302 may further include step S3023.
S3023, if the destination address is not hit in the first failure information table, querying a second failure information table based on the destination address, and determining that the destination address has a table entry hit in the second failure information table.
For example, the second failure information table and the second repair data table may be stored in a register.
For example, if the destination address misses in the first table, the second table may be further queried to determine whether the destination address is invalid. And if the destination address has an entry hit in the second invalidation information table, determining that the destination address is an invalidated address, namely, the data unit requested to be accessed is invalidated.
For example, when performing address conversion, both the invalid address X of 26 bits and the invalid address Y of 26 bits are converted into the address Z of 10 bits, the first invalid information table includes the invalid address Y, and the second invalid information table includes the invalid address X. If the destination address is address X, and the destination address X does not have an entry hit in the first failure information table, it may be further determined whether the destination address X has an entry hit in the second failure information table. And if the destination address X has the table entry hit in the second failure information table, determining that the destination address is a failed address.
In this embodiment, in the case that the first failure information table is queried based on the destination address to determine that the destination address is not hit in the first failure information table, the second failure information table may be further queried based on the destination address to determine whether the destination address is hit in an entry in the second failure information table. Therefore, when address conversion conflicts, whether the destination address is invalid or not can be accurately determined.
Corresponding to the second implementation manner, when the first failure information table is stored in the CAM, the querying the failure recovery information table based on the destination address in step S302 to determine that the destination address has an entry hit in the failure recovery information table includes: and based on the destination address, searching whether the destination address is hit in the first failure information table or not in the first failure information table, and if yes, determining the destination address as a failed address.
For example, as shown in fig. 6, the size of the CAM is 26 bits by 1K, 1K invalid addresses are stored in the CAM, and the address length of each invalid address is 26 bits. Since the CAM is a content addressable memory, the destination address can be directly searched in the CAM, and if the destination address has an entry hit in the CAM, the destination address is determined to be a failed address, that is, the data unit requested to be accessed is failed. For example, if the destination address is the same as the invalidation address C stored in the CAM, i.e. the destination address has an entry hit in the CAM, it is determined that the data unit requested to be accessed is invalid. As another example, if the destination address misses in an entry in the CAM, it may be determined that the data unit requested to be accessed is not stale.
It is to be understood that since the CAM is a content addressable memory, when the first failure information table is stored in the CAM, it is possible to directly perform a lookup in the CAM based on the destination address to determine whether the destination address is a failed address, and address conversion is not required when the first failure information table is stored in the CAM as compared with when the first failure information table is stored in the SRAM.
Optionally, the size of the CAM storing the first failure information table may also be 27 bits × 1K, where 1bit is an indication bit, and different values of the indication bit are used to indicate whether an address indicated by a certain entry in the CAM is a failed address. When the indication bit indicates that the address indicated by an entry is a failed address and the destination address hits in the entry, it may be determined that the destination address is a failed address, i.e., the data unit requested to be accessed is failed.
And S303, executing a read-write instruction in the access request to the repair storage resource corresponding to the hit table entry.
For example, if the read-write instruction is a write instruction, as shown in fig. 7, the executing the read-write instruction in the access request to the repair storage resource corresponding to the hit entry in step S303 includes: steps S3031-S3035.
S3031, the failure repair control module sends a first repair instruction to the read-write data repair module.
The first repair instruction includes a destination address and a write instruction.
Optionally, the first repair instruction may further include an address of the repair memory resource corresponding to the destination address.
S3032, the read-write data repairing module receives a first repairing instruction.
Illustratively, the read-write data repair module receives the first repair instruction to know that the data unit currently requesting access is invalid.
S3033, the read-write data repair module sends the write data and the destination address to the failure repair control module.
For example, the read-write data repair module may send the write data to the failover control module.
S3034, the failure repair control module receives the write data and the destination address.
S3035, the failure repair control module writes write data in the repair storage resource corresponding to the hit table entry.
For example, the destination address hits in the first failure information table in step S302. And the entry in the first repair data table in the failure repair control module is used for indicating the repair storage resource corresponding to the failed first address, and the first repair data table is stored in the SRAM.
Illustratively, the size of the repair storage resource indicated by each entry in the first repair data table is the repair granularity. For example, as shown in fig. 5 and fig. 6, taking the repair granularity as 256 bits as an example, the size of the repair storage resource indicated by each entry in the SRAM is 256 bits.
For example, the failure repair control module may write the write data in the repair storage resource corresponding to the hit entry in the failure information table in the first repair data table.
Illustratively, the depth (depth) of the first failure information table and the first repair data table may be the same. That is, the number of the failed first addresses stored in the first failure information table is the same as the number of the repair storage resources stored in the first repair data table, and the position of the failed first address in the first failure information table is the position of the corresponding repair storage resource in the first repair data table.
For example, as shown in fig. 5, the first failure information table may store 1K failed addresses, and the first repair data table may store 1K repair memory resources. The position of the failed first address in the first failure information table is the same as the position of the corresponding repair storage resource in the first repair data table. For example, the destination address C, which is the same as the invalidated first address C stored at position 0000000010 in the first invalidation information table, may be converted into the 10-bit reference address 0000000010, and the destination address is determined to be the invalidated address. The repair memory resource corresponding to the destination address C in the first repair data table is the repair memory resource at position 0000000010. As shown in fig. 5, the repair memory resource corresponding to the destination address C is the repair memory resource 3 in fig. 5. When the read-write instruction is a write instruction, the failure repair control module writes write data in the repair storage resource at 0000000010 in fig. 5.
For another example, as shown in fig. 6, when the first failure information table is stored in the CAM, and the first repair data table is stored in the SRAM, 1K failed addresses may be stored in the CAM, and 1K repair storage resources may be stored in the SRAM. The location of the failed first address in the CAM is the same as the location of its corresponding repair storage resource in the SRAM. As shown in fig. 6, the location of the failed address C in the CAM is the same as the location of the repair memory resource corresponding to the failed address in the SRAM, that is, the repair memory resource corresponding to the failed address C is repair memory resource 3.
Optionally, if the repair granularity of the repair storage resource is 256 bits, the size of the SRAM storing the first repair data table in fig. 5 may also be 257 bits × 1K, that is, the size indicated by each entry in the SRAM may be 257 bits. Wherein 256 bits are repair storage resources, 1bit is an indication bit, and different values of the indication bit are used for indicating whether the repair storage resources indicated by a certain entry have been written with data. If the 1-bit indication bit indicates that the repair storage resource indicated by the table entry has written data, the repair storage resource indicated by the table entry can be read when the destination address is a failed address and the read-write instruction is a read instruction. If the 1-bit indicating bit indicates that the repair storage resource indicated by the table entry is not written with data, when the destination address is a failed address and the read-write instruction is a read instruction, the failure repair control module may not read the repair storage resource indicated by the table entry, and the read-write data repair module reads the data stored in the destination address of the DRAM die.
Optionally, if the repair granularity of the repair storage resource is 1Byte (8bit), the size of the SRAM storing the first repair data table in fig. 5 may also be 14bit × 1K, that is, the size indicated by each entry in the SRAM may be 14 bit. Wherein, 8 bits are the repair storage resource, 1bit is the first indicator bit, 5 bits are the repair indicator bit, different values of the first indicator bit are used to indicate whether the repair storage resource indicated by a certain entry has written data, and different values of the repair indicator bit are used to indicate that the repair storage resource indicated by a certain entry repairs the specific position of the Byte to be repaired on the data bus of 2 DQ Width.
For example, if the read-write instruction is a read instruction, as shown in fig. 8, the executing the read-write instruction in the access request to the repair storage resource corresponding to the hit entry in step S303 includes: steps S3036-S3038.
S3036, the failure repair control module reads the read data stored in the repair storage resource corresponding to the hit table entry.
For example, the destination address hits in the first failure information table in step S302. When the failure recovery control module determines that the destination address fails, the failure recovery control module may read, in the first recovery data table, read data stored in the recovery storage resource corresponding to the entry hit in the first failure information table.
And S3037, the failure repair control module sends a second repair instruction to the read-write data repair module.
The second repair instruction includes a destination address, read data, and a read instruction.
For example, the failure repair control module may send the read data stored in the repair memory resource corresponding to the failed address, and send the read data, the destination address, and the read command to the read-write data repair module.
S3038, the read-write data repairing module receives a second repairing instruction.
Illustratively, the read-write data repair module receives the second repair instruction, and obtains read data, a destination address, and a read instruction. Optionally, the read-write data recovery module may further send the read data to an external data bus to complete a read request process.
It should be noted that, in the embodiment of the present application, when a data unit requested to be accessed fails (a destination address fails), and a read/write instruction in an access request is executed by repairing a storage resource, the repairing and replacing operations of the failed data unit outside the memory are not sensed.
According to the failure recovery method of the memory, the recovery storage resources are intensively deployed in the Logic die, so that when the failure recovery control module determines that the destination address fails, the read-write instruction in the access request is executed through the centrally deployed recovery storage resources, and the operation of replacing the failed data unit by the recovery storage resources outside the memory is not sensed. In the scheme in this embodiment, when determining that a data unit requested to be accessed fails, it is not possible to distinguish which Bank or which Sub Bank or which Channel the data unit belongs to, but it is uniform to execute a read-write instruction in an access request by using a repair storage resource in a failure repair module. Therefore, when the failed data units in the memory are not uniformly distributed, the utilization rate of the repair storage resources is improved, and the yield of the chip is improved. In addition, the repair granularity of repairing the storage resource in the embodiment of the application may be finer, for example, the repair granularity may use Byte as the granularity, so that the utilization rate of the repair resource can be further improved.
Optionally, an embodiment of the present application further provides a method for repairing a memory failure, as shown in fig. 9, before step S301, the method may further include S901 to S905.
S901, the self-checking module sends a self-checking request to the controller.
S902, the self-checking module sends the address to be detected to the address register module.
S903, the self-checking module determines the address to be detected as a failed address based on a preset self-checking algorithm.
Illustratively, the introspection module may detect failed addresses in the memory based on an ECC error detection mechanism. Optionally, since the memory may have a data unit that fails during the operation process, the self-checking module may detect the failed address in the memory at intervals to update the failed address. Alternatively, the self-check module may detect a failed address in the memory when the memory is idle.
Optionally, when the self-checking module detects a failed address in the memory in step S901, the self-checking module may send a self-checking request to the controller, and then detect the address to be detected in combination with the read-write data recovery module, so as to determine the failed address.
And S904, the self-checking module sends the failed address to the failure repair control module.
And S905, receiving and storing the failed address by the failure repair control module.
For example, when the failure repair control module stores the failed address, the failed address may be stored in the SRAM. In this implementation, the failure repair control module may store the failed address in the first failure information table or the second failure information table. If the two failed addresses are compressed by the preset algorithm in step S3021, a hash collision occurs. For example, when two 26-bit failed addresses are compressed into the same 10-bit address, the failover control module may store one of the failed addresses in the first failure information table, and store the other failed address in the second failure information table.
For example, when the failover control module stores the failed address, the failed address may be stored in the CAM. Since the CAM is a content addressable memory, in this implementation, all failed addresses can be stored in the CAM without concern for address compression conflicts.
For example, the failover control module may set the repair granularity of the repair storage resource to Byte, for example, set the repair granularity to 256 bits or 8 bits.
In the scheme of this embodiment, the self-checking module may determine a failed address in the memory, and send the failed address to the failure recovery control module, and the failure recovery control module stores the failed address, so that when a certain destination address of the memory is requested to be accessed, the failure recovery control module may determine whether the destination address fails based on the stored failed address. And under the condition that the destination address fails, the read-write instruction in the access request is executed by adopting the repair storage resource. According to the scheme of the embodiment of the application, the restoration storage resources can be intensively deployed on the Logic die, so that the utilization rate of the restoration storage resources can be improved under the condition that the failed data units are not uniformly distributed, and the yield of the memory can be improved. In addition, the failure recovery control module in the embodiment of the present application may implement complex logic, for example, the granularity of recovery may be set to Byte, and the refinement of the granularity of recovery may further improve the utilization rate of the redundant storage resource.
The above description has mainly introduced the scheme provided in the embodiments of the present application from the perspective of method steps. It will be appreciated that the computer, in order to carry out the above-described functions, may comprise corresponding hardware structures and/or software modules for performing the respective functions. Those of skill in the art will readily appreciate that the present application is capable of implementing the exemplary modules and algorithm steps described in connection with the embodiments disclosed herein in a combination of hardware and computer software. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiment of the present application, the functional modules of the failure recovery control module may be divided according to the above method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. It should be noted that, in the embodiment of the present application, the division of the module is schematic, and is only one logic function division, and there may be another division manner in actual implementation.
In the case of dividing each functional module in correspondence with each function, fig. 10 shows a failure recovery control device, which may be a chip. The failure recovery control device may be the failure recovery control module according to the above embodiment, and the failure recovery control device 1000 includes: acquisition section 1001, processing section 1002, and communication section 1003.
Wherein, the obtaining unit 1001 may be configured to support the failure recovery control apparatus 1000 to execute S301 in fig. 3; the processing unit 1002 may be configured to support the failure recovery control apparatus 1000 to execute S302 and S303 in fig. 3, or S3021 to S3023 in fig. 4, or S3035 in fig. 7, or S3036 in fig. 8; the communication unit 1003 is used to support the failover control device 1000 to execute S3031 and S3034 in fig. 3, or S3037 in fig. 8, or S905 in fig. 9. All relevant contents of each step related to the above method embodiment may be referred to the functional description of the corresponding functional module, and are not described herein again.
Illustratively, the embodiment of the present application further provides an integrated circuit, as shown in fig. 11, including a Logic die, where the Logic die includes a memory interface, a memory controller, and a repair memory resource. The repair memory resource is a redundant memory resource in the memory.
Wherein the memory interface is used for communicating with other devices or equipment. The memory controller is used for managing a failure repair information table, and the failure repair information table is used for indicating failed addresses in the memory and repair memory resources corresponding to the failed addresses; acquiring an access request, wherein the access request comprises a read-write command and a destination address of a data unit requested to be accessed; and inquiring the failure recovery information table based on the destination address, and if the destination address has a hit table entry in the failure recovery information table, executing a read-write command to a recovery storage resource corresponding to the hit table entry. The memory controller is also configured to perform the functions of the fail-over control module in the fail-over method of the memory in any of the embodiments of fig. 3, 4, 7, 8, or 9.
The embodiment of the present application further provides a device, which exists in a product form of a chip, and the structure of the device includes a processor, optionally, a memory; a memory for storing a failure repair information table; a processor configured to perform the method for repairing the memory failure in any one of the embodiments of fig. 3, 4, 7, 8, or 9. Illustratively, the apparatus may be deployed in Logic die.
The embodiment of the present application further provides an apparatus, which may exist in the form of a chip product, and the apparatus includes a processor and an interface circuit, where the processor is configured to communicate through the interface circuit, so that the apparatus performs the method for repairing the memory failure in any one of the embodiments of fig. 3, fig. 4, fig. 7, fig. 8, or fig. 9.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied in hardware or in software instructions executed by a processor. The software instructions may be comprised of corresponding software modules that may be stored in Random Access Memory (RAM), flash Memory, Erasable Programmable read-only Memory (EPROM), Electrically Erasable Programmable read-only Memory (EEPROM), registers, a hard disk, a removable disk, a compact disc read-only Memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an ASIC. Additionally, the ASIC may reside in a core network interface device. Of course, the processor and the storage medium may reside as discrete components in a core network interface device.
Those skilled in the art will recognize that in one or more of the examples described above, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.
The above-mentioned embodiments, objects, technical solutions and advantages of the present application are further described in detail, it should be understood that the above-mentioned embodiments are only examples of the present application, and are not intended to limit the scope of the present application, and any modifications, equivalent substitutions, improvements and the like made on the basis of the technical solutions of the present application should be included in the scope of the present application.
Claims (54)
- A method for memory failure recovery, applied to an apparatus including a Logic die including a recovery memory resource, the method comprising:Acquiring an access request, wherein the access request comprises a read-write instruction and a destination address of a data unit which is requested to be accessed;and inquiring a failure recovery information table based on the destination address, if the destination address has table entry hit in the failure recovery information table, executing a read-write instruction in the access request to a recovery storage resource corresponding to the hit table entry, wherein the failure recovery information table is used for indicating a failed address in a memory and the recovery storage resource corresponding to the failed address.
- The method according to claim 1, wherein when the read-write instruction is a write instruction, the executing the read-write instruction in the access request to the repair storage resource corresponding to the hit table entry includes:sending a first repair instruction to a read-write data repair module, wherein the first repair instruction comprises the destination address and the write instruction;receiving write data from the read-write data recovery module and the destination address;and storing the write data in a repair storage resource corresponding to the hit table entry.
- The method according to claim 1, wherein when the read-write instruction is a read instruction, the executing the read-write instruction in the access request to the repair storage resource corresponding to the hit table entry includes:Reading read data stored in the repair storage resource corresponding to the hit table entry;and sending a second repair instruction to a read-write data repair module, wherein the second repair instruction comprises the destination address, the read data and the read instruction.
- The method according to any of claims 1-3, wherein the failure repair information table comprises a first failure information table and a first repair data table, wherein an entry in the first failure information table is used for indicating a failed first address in the memory, and an entry in the first repair data table is used for indicating a repair storage resource corresponding to the failed first address.
- The method of claim 4, wherein the first failure information table is stored in a Content Addressable Memory (CAM) and the first repair data table is stored in a Static Random Access Memory (SRAM).
- The method of claim 5, wherein entries in the CAM are used to hold the invalidated first address, and wherein the locations of the entries in the CAM correspond to address information of the repair storage resource.
- The method of claim 4, wherein the first failure information table and the first repair data table are stored in SRAM.
- The method of claim 7, wherein querying a failover information table based on the destination address comprises:converting the destination address into a reference address by adopting a preset algorithm, wherein the address length of the reference address corresponds to the size of the first failure information table;querying the first failure information table based on the reference address;correspondingly, the entry hit of the destination address in the failover information table includes: the destination address has an entry hit in the first table of invalidation information.
- The method of claim 8, wherein the predetermined algorithm is a hash algorithm, a double hash algorithm, or a multi-hash bucket algorithm.
- The method according to any of claims 7-9, wherein the failure repair information table further comprises a second failure information table and a second repair data table, wherein an entry in the second failure information table is used for indicating a failed second address in the memory, and an entry in the second repair data table is used for indicating a repair memory resource corresponding to the failed second address.
- The method of claim 10, wherein the second failure information table and the second repair data table are saved in registers.
- The method according to claim 10 or 11, wherein the querying a failure recovery information table based on the destination address further comprises:if the destination address is not hit in the first failure information table, inquiring the second failure information table based on the destination address;correspondingly, the entry hit of the destination address in the failover information table includes: the destination address has an entry hit in the second failure information table.
- The method according to any of claims 1-12, characterized in that the repair granularity of the repair memory resources is less than or equal to 2 times the size of the bit Width DQ Width of the data bus, or N bytes, said N being greater than or equal to 1.
- An integrated circuit comprising a logic die, the logic die comprising a memory interface, a memory controller, and repair memory resources,the memory controller is to:managing a failure recovery information table, wherein the failure recovery information table is used for indicating failed addresses in a memory and recovery storage resources corresponding to the failed addresses;acquiring an access request, wherein the access request comprises a read-write command and a destination address of a data unit requested to be accessed;And inquiring the failure recovery information table based on the destination address, and if the destination address has a hit table entry in the failure recovery information table, executing the read-write command to a recovery storage resource corresponding to the hit table entry.
- The ic of claim 14, wherein when the read/write command is a write command, the memory controller is specifically configured to:sending a first repair instruction to a read-write data repair module, wherein the first repair instruction comprises the destination address and the write instruction;receiving write data from the read-write data recovery module and the destination address;and storing the write data in a repair storage resource corresponding to the hit table entry.
- The ic of claim 14, wherein when the read/write command is a read command, the memory controller is further configured to:reading read data stored in the repair storage resource corresponding to the hit table entry;and sending a second repair instruction to a read-write data repair module, wherein the second repair instruction comprises the destination address, the read data and the read instruction.
- The integrated circuit of any of claims 14-16, wherein the failure repair information table comprises a first failure information table and a first repair data table, wherein entries in the first failure information table are used to indicate failed first addresses in the memory, and entries in the first repair data table are used to indicate repair storage resources corresponding to the failed first addresses.
- The integrated circuit of claim 17, wherein the first failure information table is stored in a Content Addressable Memory (CAM) and the first repair data table is stored in a Static Random Access Memory (SRAM).
- The integrated circuit of claim 18, wherein entries in the CAM are configured to hold the invalidated first address, the locations of the entries in the CAM corresponding to address information of the repair storage resource.
- The integrated circuit of claim 17, wherein the first failure information table and the first repair data table are stored in SRAM.
- The integrated circuit of claim 20, wherein the memory controller is further configured to:converting the destination address into a reference address by adopting a preset algorithm, wherein the address length of the reference address corresponds to the size of the first failure information table;Querying the first failure information table based on the reference address;correspondingly, the entry hit of the destination address in the failover information table includes: the destination address has an entry hit in the first table of invalidation information.
- The integrated circuit of claim 21, wherein the predetermined algorithm is a hash algorithm, a double hash algorithm, or a multi-hash bucket algorithm.
- The integrated circuit of any of claims 20-22, wherein the failure repair information table further comprises a second failure information table and a second repair data table, wherein entries in the second failure information table are used to indicate failed second addresses in the memory, and entries in the second repair data table are used to indicate repair memory resources corresponding to the failed second addresses.
- The integrated circuit of claim 23, wherein the second failure information table and the second repair data table are stored in registers.
- The integrated circuit of claim 23 or 24, wherein the memory controller is further configured to:if the destination address is not hit in the first failure information table, inquiring the second failure information table based on the destination address;Correspondingly, the entry hit of the destination address in the failover information table includes: the destination address has an entry hit in the second failure information table.
- The integrated circuit of any of claims 14-25, wherein the repair granularity of the repair memory resource is less than or equal to 2 times the size of the bit Width DQ Width of the data bus, or N bytes, where N is greater than or equal to 1.
- A failure recovery device for a memory, applied to a chip, wherein the chip comprises a Logic die, and the Logic die comprises a recovery memory resource, the device comprises:the device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is used for acquiring an access request, and the access request comprises a read-write instruction and a destination address of a data unit which requests to be accessed;and the processing unit is used for inquiring a failure recovery information table based on the destination address, if the destination address has table entry hit in the failure recovery information table, executing a read-write instruction in the access request to a recovery storage resource corresponding to the hit table entry, and the failure recovery information table is used for indicating a failure address in a memory and the recovery storage resource corresponding to the failure address.
- The apparatus according to claim 27, wherein when the read/write command is a write command, the apparatus further comprises a communication unit,the communication unit is configured to send a first repair instruction to a read-write data repair module, where the first repair instruction includes the destination address and the write instruction; receiving write data from the read-write data recovery module and the destination address;the processing unit is specifically configured to store the write data in a repair storage resource corresponding to the hit entry.
- The apparatus of claim 27, wherein when the read/write command is a read command, the apparatus further comprises a communication unit,the processing unit is further configured to read data stored in the repair storage resource corresponding to the hit table entry;the communication unit is configured to send a second repair instruction to a read-write data repair module, where the second repair instruction includes the destination address, the read data, and the read instruction.
- The apparatus according to any of claims 27-29, wherein the failure repair information table comprises a first failure information table and a first repair data table, wherein an entry in the first failure information table is used to indicate a failed first address in the memory, and an entry in the first repair data table is used to indicate a repair storage resource corresponding to the failed first address.
- The apparatus of claim 30, wherein the first failure information table is stored in a Content Addressable Memory (CAM) and the first repair data table is stored in a Static Random Access Memory (SRAM).
- The apparatus of claim 31 wherein entries in the CAM are used to hold the invalidated first address, the locations of the entries in the CAM corresponding to address information of the repair storage resource.
- The apparatus of claim 30, wherein the first failure information table and the first repair data table are maintained in SRAM.
- The apparatus according to claim 33, wherein the processing unit is specifically configured to:converting the destination address into a reference address by adopting a preset algorithm, wherein the address length of the reference address corresponds to the size of the first failure information table;and inquiring the first failure information table based on the reference address.
- The apparatus of claim 34, wherein the predetermined algorithm is a hash algorithm, a double hash algorithm, or a multi-hash bucket algorithm.
- The apparatus of any of claims 33-35, wherein the failure repair information table further comprises a second failure information table and a second repair data table, wherein entries in the second failure information table are used to indicate failed second addresses in memory, and entries in the second repair data table are used to indicate repair storage resources corresponding to the failed second addresses.
- The apparatus of claim 36, wherein the second failure information table and the second repair data table are saved in registers.
- The apparatus according to claim 36 or 37, wherein the processing unit is further configured to:and if the destination address is not hit in the first failure information table, inquiring the second failure information table based on the destination address.
- The apparatus as claimed in any one of claims 27-38, wherein the repair granularity of the repair memory resource is less than or equal to 2 times the size of the bit Width DQ Width of the data bus, or N bytes, where N is greater than or equal to 1.
- A failure recovery device of a memory is characterized by comprising a Logic die, wherein the Logic die comprises a failure recovery control module and a recovery storage resource;the failure recovery control module is used for:acquiring an access request, wherein the access request comprises a read-write instruction and a destination address of a data unit which is requested to be accessed;and inquiring a failure recovery information table based on the destination address, if the destination address has table entry hit in the failure recovery information table, executing a read-write instruction in the access request to a recovery storage resource corresponding to the hit table entry, wherein the failure recovery information table is used for indicating a failed address in a memory and the recovery storage resource corresponding to the failed address.
- The apparatus of claim 40, wherein the logic die further comprises a read-write data repair module, wherein when the read-write command is a write command,the failure recovery control module is specifically configured to send a first recovery instruction to the read-write data recovery module, where the first recovery instruction includes the destination address and the write instruction;the read-write data restoration module is used for receiving the first restoration instruction and sending write data and the destination address to the failure restoration control module;the failure recovery control module is specifically further configured to receive the write data and the destination address from the read-write data recovery module, and store the write data in a recovery storage resource corresponding to the hit table entry.
- The apparatus of claim 40, wherein the logic die further comprises a read-write data repair module, wherein when the read-write command is a read command,the failure recovery control module is specifically configured to read data stored in a recovery storage resource corresponding to the hit table entry, and send a second recovery instruction to the read-write data recovery module, where the second recovery instruction includes the destination address, the read data, and the read instruction;And the read-write data repairing module is used for receiving the second repairing instruction from the failure repairing control module.
- The apparatus of any of claims 40-42, wherein the failure repair information table comprises a first failure information table and a first repair data table, wherein an entry in the first failure information table is used to indicate a failed first address in memory, and an entry in the first repair data table is used to indicate a repair storage resource corresponding to the failed first address.
- The apparatus of claim 43, wherein the first failure information table is stored in a Content Addressable Memory (CAM) and the first repair data table is stored in a Static Random Access Memory (SRAM).
- The apparatus of claim 44 wherein entries in the CAM are configured to hold the first address that is invalidated, the locations of the entries in the CAM corresponding to address information of the repair storage resource.
- The apparatus of claim 43, wherein the first failure information table and the first repair data table are maintained in SRAM.
- The apparatus of claim 46, wherein the failure recovery control module is specifically configured to:Converting the destination address into a reference address by adopting a preset algorithm, wherein the address length of the reference address corresponds to the size of the first failure information table;and inquiring the first failure information table based on the reference address.
- The apparatus of claim 47, wherein the predetermined algorithm is a hash algorithm, a double hash algorithm, or a multi-Hill-bucket algorithm.
- The apparatus of any of claims 46-48, wherein the failure repair information table further comprises a second failure information table and a second repair data table, wherein entries in the second failure information table are used to indicate failed second addresses in memory, and wherein entries in the second repair data table are used to indicate repair storage resources to which the failed second addresses correspond.
- The apparatus of claim 49, wherein the second failure information table and the second repair data table are saved in registers.
- The apparatus of claim 49 or 50, wherein the failure recovery control module is further configured to:and if the destination address is not hit in the first failure information table, inquiring the second failure information table based on the destination address.
- The apparatus of any of claims 40-51, wherein a repair granularity of the repair memory resource is less than or equal to 2 times a size of a bit Width, DQ Width, of the data bus, or N bytes, and wherein N is greater than or equal to 1.
- The apparatus according to any of claims 40-52, wherein the Logic die further comprises a self-test module, a controller and an address registration module, and the self-test module is respectively connected with the controller, the address registration module and the failover control module;the self-checking module is used for sending a self-checking request to the controller;the controller is used for receiving the self-checking request;the self-checking module is also used for sending the address to be detected to the address registering module;the self-checking module is further configured to determine that the address to be detected is a failed address based on a preset self-checking algorithm.
- The apparatus of claim 53,the self-checking module is further configured to send the failed address to the failure recovery control module;the failure repair control module is further configured to receive a failed address from the self-checking module, and store the failed address in the failure repair information table.
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| Application Number | Priority Date | Filing Date | Title |
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| PCT/CN2019/130840 WO2021134628A1 (en) | 2019-12-31 | 2019-12-31 | Failure repair method and device for memory |
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| CN114830241A true CN114830241A (en) | 2022-07-29 |
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Cited By (2)
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| CN115757196A (en) * | 2022-11-09 | 2023-03-07 | 超聚变数字技术有限公司 | Memory, memory access method and computing equipment |
| CN115881202A (en) * | 2023-02-09 | 2023-03-31 | 长鑫存储技术有限公司 | Repair circuit and method, memory and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN118295838A (en) * | 2022-07-08 | 2024-07-05 | 超聚变数字技术有限公司 | Method and device for determining repair resource granularity of memory failure |
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| US9099165B1 (en) * | 2012-05-02 | 2015-08-04 | Inphi Corporation | Single chip mixed memory for dynamic replacement of DRAM bad cell |
| US9449720B1 (en) * | 2015-11-17 | 2016-09-20 | Macronix International Co., Ltd. | Dynamic redundancy repair |
| KR101805028B1 (en) * | 2016-06-28 | 2017-12-06 | 고려대학교 산학협력단 | Memory apparatus for applying fault repair based on physical region and virtual region and control method thereof |
| US10636511B2 (en) * | 2017-07-27 | 2020-04-28 | Taiwan Semiconductor Manufacturing Company Limited | Memory repair scheme |
| CN109698008B (en) * | 2017-10-23 | 2021-01-15 | 北京兆易创新科技股份有限公司 | Method and device for repairing NOR type memory bit line fault |
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| CN115757196A (en) * | 2022-11-09 | 2023-03-07 | 超聚变数字技术有限公司 | Memory, memory access method and computing equipment |
| CN115757196B (en) * | 2022-11-09 | 2023-09-01 | 超聚变数字技术有限公司 | Memory, memory access method and computing device |
| CN115881202A (en) * | 2023-02-09 | 2023-03-31 | 长鑫存储技术有限公司 | Repair circuit and method, memory and electronic equipment |
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