CN115877190A - PROM reliability test system realized based on FPGA - Google Patents

Abstract

The invention aims to provide a rapid and reliable test system test scheme for the circulating read-write test of PROM, and particularly relates to a PROM reliability test system realized based on FPGA. The invention changes the division of labor of the lower computer of the upper computer of the traditional test system, particularly, the statistical treatment of results generated by multiple tests in the cyclic read-write test, such as calculating the proportion of single Bit errors in all errors, is completed in the lower computer, and finally the FPGA only sends the final test result to the upper computer; in addition, in the aspect of PCB design of the test board, the PROM socket is separately connected with the test board base, so that the adaptability of the test system to different test items is improved.

Description

PROM reliability test system realized based on FPGA

Technical Field

The invention relates to an external test device design of a static memory, in particular to a PROM reliability test system design scheme realized based on an FPGA.

Background

Electronic equipment running in space is inevitably interfered by high-energy particles, the temperature and voltage environment of a spacecraft can be in a severe condition, and the environmental factors can cause the error of a storage chip in the spacecraft, so that the whole system is in error or even fails, and therefore the storage chip running on the equipment has the reliability of space level. An antifuse PROM (Programmable Read-on-ly Memory) as a high-reliability Memory with radiation resistance has important research significance in aerospace application, and for an antifuse PROM product, before the antifuse PROM product is actually applied to a spacecraft, the reliability of the antifuse PROM product must be evaluated by a plurality of methods, such as high-temperature aging test, PROM bottom layer device time-lapse breakdown test, high-low temperature function test, cyclic reading test and the like. For some test contents of PROM such as cyclic read test, the traditional test method has certain defects: the traditional function test is generally that an upper computer is matched with a lower computer, the lower computer is responsible for basic read-write functions, statistical processing of test data is handed to the upper computer, communication connection is established between the upper computer and the lower computer through a certain method, the method inevitably brings high communication cost, and once the number of test rounds of the cyclic read test is high or the time of single read of PROM is long, the test is difficult to complete by the method.

Disclosure of Invention

Aiming at the problems or the defects, the invention provides a PROM reliability testing system realized based on an FPGA (field programmable gate array) in order to solve the problem of high communication cost of a cyclic reading testing system. The invention completes all logic processing and data processing by using FPGA hardware, and the upper computer is only used for sending a test starting signal and receiving a test result to greatly reduce the communication cost of the whole test system, thereby improving the test speed and efficiency.

A PROM reliability test system based on FPGA, FPGA program includes communication serial port module, circulation logic control module, PROM interface module, all data processing are accomplished in FPGA but not host computer in addition, the connection mode of testing board bottom plate and PROM is the detachable connection.

The communication serial port module realizes a UART serial port communication protocol, input signals of the communication serial port module are a bit signal UART _ rx and a bit signal UART _ tx, wherein the UART _ rx is a UART communication receiving signal, the UART _ tx is a UART communication sending signal, an output signal is a START signal, the function of the START signal is to indicate the whole test system to START working, and the condition for generating START is that the UART _ rx receives a specific single byte signal sent by an upper computer, such as hexadecimal number 55. The whole module is used for realizing serial port communication with an upper computer PC;

the circulation logic control module is used for realizing the test function of a core, STARTs circulation test logic after receiving a START signal from a communication serial port, utilizes a BRAM memory of an FPGA, the circulation process is that all data of the whole PROM are stored in a BRAM which is as large as the PROM, then one million rounds of PROMs are circularly read, the value of the PROM is compared with the initial value of the PROM stored in the BRAM when each round of PROM is read, if errors occur, the error condition and the error type are recorded, after 100 ten thousand rounds of PROMs are circularly read, the recorded error statistical result is sent to an upper computer through a serial port, the generation and calculation of the result data (such as the occupation ratio of single bit errors in all errors) are finished in the FPGA, and the original data are not sent to the upper computer and then calculated by the upper computer.

The PROM interface module is a port communication module of the FPGA and the PROM, the communication between the PROM and the FPGA needs to be processed by chips such as level conversion, DAC, operational amplifier and the like, and the processing is finished at the PROM interface module.

Furthermore, in the whole PROM reliability test system, after an upper computer PC sends an initial signal, all test flows and intermediate information storage are completed in the FPGA, so that the communication cost between the FPGA and the PC is greatly reduced, and the running speed of the whole test system is improved.

Further, the communication serial port module can be completed by using a UART serial port, and under a simple condition, only three DuPont wires are needed for realizing UART communication between the upper computer PC and the FPGA, one receiving wire UART _ rx, one sending wire UART _ tx and one grounding wire are needed, so that the communication cost of the whole test system is reduced under the condition of meeting the communication requirement.

Furthermore, the circulating logic control module completely realizes the testing algorithm of the whole PROM, during the whole testing process, the number of rounds of the PROM circulating, the number of the address pointer, if errors occur, how to record error data and carry out subsequent processing are all solved in the module.

Furthermore, the PROM interface module mainly processes relevant signals of peripheral functional chips such as a DAC, an ADC, an operational amplifier, and a level conversion chip.

Furthermore, the FPGA, the PROM, and some functional chips related to the test, such as the DAC, the op-amp, etc., may be integrated on a PCB, and the PCB is a test system board.

Furthermore, only after the test is completed, the test board PCB sends the test result report to the PC through the serial port communication module, and the FPGA can send information to the upper computer without the serial port outside the time.

Furthermore, the power supply part of the PCB of the test board needs an external direct current power supply to ensure the normal operation of the FPGA, the PROM and the peripheral chip, and meanwhile, the external direct current power supply is used for supplying power, so that the power supply voltage can be conveniently changed in some test items.

Furthermore, the connection between the PROM and the test board PCB is completed through the PROM socket instead of directly welding the PROM on the test board PCB, so that the connection between the PROM and the test board PCB obtains certain flexibility, and the test board PCB and the PROM socket can be separately connected under the environments of high and low temperature test and the like.

Furthermore, the test algorithm specifically adopted in the cyclic logic control module can be changed, so that the test system is determined to have strong extensibility and expandability. For an antifuse PROM, the memory can only be written once, and is characterized in that all storage nodes store logic 0 at the initial condition, and the logic 0 can be changed into logic 1 through one-time writing subsequently, but the logic 1 can not be changed into logic 0 any more, so the reliability test of the memory is mainly a cyclic reading test, the maximum number of reading rounds can be tested without error, or the error type of the memory is counted after the error, the ratio of single Bit errors to all errors is calculated, and the like; for some memories, the cyclic read can be changed into cyclic read and write or other types of tests, and the changes can be realized in the cyclic logic control module.

In summary, the invention greatly reduces the communication cost and improves the working efficiency of the whole test system by completing the test work and data processing in the FPGA, and in addition, because the core logic of the test system can be changed in the FPGA soft code, the system has strong expandability and can be conveniently applied to PROMs of different models and different test items. Meanwhile, in terms of hardware design, the method for detachably connecting the PROM and the test board PCB is adopted, so that the PROM and the test board can be conveniently in different environments in some special projects such as high-low temperature test.

Drawings

FIG. 1 is a logic block diagram of a loop logic control module of an embodiment;

FIG. 2 is a diagram of an embodiment FPGA code state machine transition;

FIG. 3 is a layout of a PCB test board according to an embodiment;

FIG. 4 is a sample diagram of a PROM and PCB test board separation connection of an embodiment;

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.

In the embodiment, the FPGA core logic is shown as figure 1, the state machine transition diagram of the FPGA core logic is shown as figure 2, and the example PCB layout is shown as figure 3.

As shown in fig. 2, in the whole test process, the FPGA logic is in an I DLE state after being powered on, after receiving a start instruction sent by an upper computer PC through a UART serial port, the state machine starts to jump, first jumps to an INI TIAL state to complete power-on initialization of the PROM, and then enters a CI RCLE state, that is, a core loop part, the specific logic of the CI RCLE state is as shown in fig. 1, specifically, one round of PROM is read first, all data of the PROM is stored in a BRAM which is as large as the PROM, then when the PROM is read from the PROM for the second time to the first million times, data is read from the BRAM and compared with the two, and when the data of the PROM is different, an error condition and an error type (for example, a single Bit error or a multiple Bit error) are recorded, and the condition of jumping out of the rcci state is that the number of PROM slice reading reaches one million times. And after the PCI RCLE state is tripped out, the PCI RCLE state enters a FINISH state, and test result information, namely the whole error condition and the most error types, is sent to the PC (personal computer) through a serial port in the FINISH state. Specifically, in terms of time sequence, when a first round of PROM is read circularly, a counter is designed at the bottom layer, the clock period of the counter is 20ns, when the counter is 0, the PROM address is changed and a read time sequence is initiated, when the counter is 3, namely 60ns, the PROM storage data is obtained, at the moment, a BRAM write time sequence is initiated, when the counter reaches 5, namely 100ns, the BRAM is written successfully, the address is changed until the whole PROM is traversed, at the moment, the PROM is circularly added by one, and the next round of PROM reading is repeatedly carried out; when the second million rounds of reading circulation are reached, when the counter is 0, the address of the PROM is changed and a reading time sequence is initiated, the counter is 3, namely 60ns time, the memory data of the PROM is obtained, at the moment, the BRAM reading time sequence is initiated, when the counter is 5, namely 100ns time, the BRAM data is obtained, at the moment, the BRAM and the PROM data are compared, if the two are not consistent, the address of the PROM at the moment, the data stored by the PROM before and after the address is wrong and the error type of the PROM data failure are also stored in the BRAM, thus changing the address until the whole PROM is traversed, at the moment, the number of rounds of PROM circulation is increased by one, and the next round of PROM reading is repeated. After 100 ten thousand rounds of reading are finished, the required result is sent back to the upper computer through the serial port, the generation and calculation of the data (such as the proportion of single bit errors in all errors) are finished in the FPGA, and the original data is not sent to the upper computer and then calculated by the upper computer.

In summary, in the whole cycle test process, the communication between the upper computer and the FPGA only sends the initial signal and receives the final test result, the communication cost is low, the time utilization rate in the test process is high, and the method is an efficient test method.

In this test example, the requirements stated in the claims are met:

1. an example of a PROM reliability test system realized based on FPGA, the FPGA program comprises a communication serial port module, a circulation logic control module and a PROM interface module, all data processing is completed in FPGA instead of an upper computer, and the connection mode of FPGA and PROM is a detachable connection; specifically, UART communication based on a CP2102 chip is adopted for communication of the lower computer of the upper computer. The condition for starting the test is that the PC sends a 16-system number 55 to the FPGA through the serial assistant and the UART line; the testing process is to read a round of PROM first, store all data of PROM in a BRAM with the same size as PROM, then when reading PROM from the second to the first million times, read data from BRAM and compare them each time, if there is error, record the specific error condition, end the testing condition is that the whole PROM reading frequency reaches one million times, at this time, send the specific testing result such as the proportion of single bit error in all error conditions to the upper computer through the serial port, through this method, can finish the whole test with the minimum communication cost and needn't send data to the upper computer once for each round of testing.

2. In the embodiment, in the test process, the whole communication data volume is very low, and the data returned by the test can be changed and customized through the FPGA code to adapt to different test requirements. For example, in this embodiment, the ratio of the return single-bit error in all error conditions may be actually changed into some other data, and the calculation may be implemented by modifying FPGA codes of the loop logic control portion.

3. In this embodiment, the physical connection between the FPGA and the upper computer PC is only 3 dupont lines, where one uart _ rx, one uart _ tx, one ground line, and the onboard communication chip is the CP2102, and the overall physical communication cost is very low.

4. In the embodiment, the whole cycle logic and the control algorithm are completed in the FPGA, and in the cycle process, the related process information is not sent to an upper computer, such as PROM cycle, an error address, data of the address before and after the error, and what logic operation needs to be performed next step, etc., are processed in the FPGA.

5. In this embodiment, in order to complete the interaction between the FPGA and the PROM, the FPGA completes signal connection with the DAC, the operational amplifier, the level conversion chip, the power chip, and the like through pin constraint.

6. In the embodiment, in order to ensure the stability of the interaction between the FPGA and the PROM, a plurality of peripheral chips including a DAC, an operational amplifier, a level conversion chip and a power supply chip are welded on a PCB.

7. In this embodiment, the PC is only responsible for sending the test start signal and receiving the test result. After the test is started, the register, the operation and the logic control of related data are all finished in the FPGA, so that no communication cost is generated, and only a small amount of communication data is generated after the test is finished, so that the communication data volume of the whole system is very low.

8. In this embodiment, the power supply chip on the test board is for stepping up and down, and whole power supply still needs outside direct current regulated voltage power supply, with the power with survey test board integration together can increase substantially and survey test board area to also be convenient for follow-up change supply voltage value simultaneously. The design of the embodiment makes it very easy to modify the supply voltage later if desired.

9. In this embodiment, two PCB layouts are specially designed, as shown in fig. 3, where the upper half of fig. 3 is a test board base board on which an FPGA core board, a peripheral chip DAC, and the like, and a PROM socket are placed; the lower part of fig. 3 is a PCB diagram of PROM socket, which is connected to the test board bottom board shown in fig. 3 through pins, or connected through dupont lines, and is very flexible, and if dupont lines are selected for connection, the test board bottom board and the PROM socket can be separated by one meter during actual test, which is very useful during some special tests such as high and low temperature tests, as shown in fig. 4, the PROM socket and the test board bottom board are separated during high and low temperature tests.

10. In this embodiment, the cyclic logic control module has strong expansibility and extensibility, and changing the module can make the PCB test board suitable for PROM tests of different models or change test contents, such as changing from a cyclic read test to a cyclic read-write test. In addition, if different PROMs are tested and the number of PROM pins changes, small modifications on the PCB layout of FIG. 3 can be completed. Generally, by changing the PCB layout of fig. 3 and the core loop logic (i.e., FPGA code in the embodiment) of fig. 1, the test board can be adapted to PROM and test items of different models.

In summary, the application provides a PROM reliability test system design method based on FPGA. The FPGA code design module is obviously divided, the low-cost communication of a lower computer of an upper computer is realized through the communication serial port module, the test algorithm of the PROM is designed through the circulating logic control module, the test result of the PROM is calculated and generated, and the data interaction of the FPGA and the PROM is completed through the PROM interface module. The advantage of FPGA code modularization is that some part of the FPGA code can be conveniently changed, for example, PROM signals, PROM test algorithms and communication algorithms are changed, and only specific module FPGA codes need to be changed. In terms of practical effects, the PROM reliability testing system design scheme based on FPGA completes the data processing process in FPGA, so the communication cost is very low, the generation speed of the circular test result is very fast, the logic resource of FPGA is utilized more efficiently, and the testing efficiency is improved; in addition, in terms of PCB design, the design of separating the PROM socket and the test board bottom plate also enables the reliability test system to be widely applied to various different test scenes. In summary, the PROM reliability testing system realized based on the FPGA has the advantages of strong universality, high reliability and lower implementation cost.

It is to be understood that the present invention has been described with reference to certain embodiments, and that various changes in the features and embodiments, or equivalent substitutions may be made therein by those skilled in the art without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (9)

1. A PROM reliability test system realized based on FPGA is basically characterized in that: the FPGA program comprises a communication serial port module, a circulating logic control module and a PROM interface module, all intermediate data processing is completed in the FPGA instead of an upper computer in the testing process, and the connection mode of the test board bottom board and the PROM is in separable connection.

The communication serial port module realizes a UART serial port communication protocol, input signals of the communication serial port module are a bit signal UART _ rx and a bit signal UART _ tx, wherein the UART _ rx is a UART communication receiving signal, the UART _ tx is a UART communication sending signal, and an output signal is a START signal which is used for indicating the whole test system to START working and generating START under the condition that the UART _ rx receives a specific single byte signal sent by an upper computer, such as a hexadecimal number of 55. The whole module is used for realizing serial port communication with an upper computer PC;

the circulation logic control module is used for realizing the test function of a core, STARTs circulation test logic after receiving a START signal from a communication serial port, utilizes a BRAM memory of an FPGA, and the circulation process comprises the steps of firstly storing all data of the whole PROM into a BRAM which is as large as the PROM, then circularly reading one million rounds of PROM, comparing the value of the PROM with an initial value of the PROM stored in the BRAM when reading the PROM in each round, recording error conditions and error types and carrying out error analysis on the FPGA if errors occur, and after circularly reading 100 ten thousand rounds of PROMs, sending recorded error statistical results to an upper computer through a serial port;

the PROM interface module is a port communication module of the FPGA and the PROM, the communication between the PROM and the FPGA needs to be processed by chips such as level conversion, DAC, operational amplifier and the like, and the processing is finished at the PROM interface module.

2. A PROM reliability test system implemented based on an FPGA as recited in claim 1, wherein:

in the whole PROM reliability test system, after an upper computer PC sends an initial signal, all test flows and intermediate information storage are finished in the FPGA, so that the communication cost between the FPGA and the PC is greatly reduced, and the running speed of the whole test system is improved.

3. A PROM reliability test system implemented based on an FPGA as recited in claim 1, wherein:

the communication serial port module is completed by using a UART serial port, and under a simple condition, only three DuPont wires, one receiving wire UART _ rx, one sending wire UART _ tx and one grounding wire are needed for realizing UART communication by the upper computer PC and the FPGA so as to reduce the communication cost of the whole test system under the condition of meeting the communication requirement.

4. A PROM reliability testing system realized based on FPGA according to claim 1, characterized in that:

the circulating logic control module completely realizes the testing algorithm of the whole PROM, and in the whole testing process, the number of rounds of the PROM and the number of the address pointer are reached, if errors occur, how to record error data and carry out subsequent processing are solved in the module.

5. A PROM reliability testing system realized based on FPGA according to claim 1, characterized in that:

the PROM interface module is mainly used for processing related signals of a DAC, an ADC, an operational amplifier and a level conversion chip, and data interaction between the FPGA and the PROM is completed through the chips.

6. A PROM reliability test system implemented based on an FPGA as recited in claim 1, wherein:

the FPGA, the PROM and some functional chips related to the test such as DAC, operational amplifier and so on are all integrated on a PCB board, and the PCB board is a test system board.

7. A PROM reliability test system implemented based on an FPGA as recited in claim 1, wherein:

and only after the test is completed, the test board PCB sends a result report of the test to the PC through the serial port communication module.

8. A PROM reliability test system implemented based on an FPGA as recited in claim 1, wherein:

the PCB of the test board needs to be supplied with power by an external direct current power supply so as to ensure the normal operation of the FPGA, the PROM and the peripheral chip, and in addition, the external direct current power supply is used for supplying power, so that the power supply voltage can be conveniently changed in certain test items.

9. A PROM reliability test system implemented based on an FPGA as recited in claim 1, wherein:

the PROM and test board PCB are connected through the PROM socket and test board bottom plate are connected in a separable way, so that the PROM and test board PCB are physically connected in a certain flexibility, and the test board PCB and the PROM socket can be separated and processed in high and low temperature test and other environments.

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