CN115877189A - Circuit fault self-checking method, device, equipment and storage medium - Google Patents
Circuit fault self-checking method, device, equipment and storage medium Download PDFInfo
- Publication number
- CN115877189A CN115877189A CN202111143571.7A CN202111143571A CN115877189A CN 115877189 A CN115877189 A CN 115877189A CN 202111143571 A CN202111143571 A CN 202111143571A CN 115877189 A CN115877189 A CN 115877189A
- Authority
- CN
- China
- Prior art keywords
- fault
- node
- self
- analog
- voltage value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a circuit fault self-checking method, which comprises the following steps: acquiring actual voltage values of all nodes in an analog sampling circuit to be detected in a self-checking mode; acquiring a theoretical voltage value of each node in the analog sampling circuit; and comparing the actual voltage value of each node with the theoretical voltage value of each node to detect the fault device in the analog sampling circuit. Therefore, when the scheme carries out fault self-checking on the analog sampling circuit, the actual voltage value of each node in the analog sampling circuit can be acquired and compared with the corresponding theoretical value to detect a fault device in the analog sampling circuit, so that fault positioning is realized; in addition, after the actual voltage waveform of each node is input into the fault diagnosis model, the fault mode of a fault device can be determined through the fault diagnosis model, so that the fault diagnosis of the circuit is realized; the invention also discloses a circuit fault self-checking device, equipment and a storage medium, and the technical effects can be realized.
Description
Technical Field
The present invention relates to the field of fault location technologies, and in particular, to a circuit fault self-checking method, apparatus, device, and storage medium.
Background
At present, in an analog sampling self-checking scheme, a digital-to-analog conversion circuit or a voltage reference source generally provides a self-checking reference voltage, a channel selection device such as a relay switches a signal source between a self-checking reference signal and an external signal, and the signal is sent to an analog-to-digital converter after being conditioned and then enters a processor for operation and judgment. In the conventional analog sampling self-checking circuit, the self-checking is usually only performed on a link from a signal input port to an output end of an analog-to-digital converter, and the fault position cannot be located more specifically.
Disclosure of Invention
The invention aims to provide a circuit fault self-checking method, a circuit fault self-checking device and a storage medium, so that fault positioning is realized when an analog sampling circuit performs fault self-checking.
In order to achieve the above object, the present invention provides a circuit fault self-checking method, including:
acquiring actual voltage values of all nodes in an analog sampling circuit to be detected in a self-checking mode;
obtaining theoretical voltage values of all nodes in the analog sampling circuit;
and comparing the actual voltage value of each node with the theoretical voltage value of each node to detect the fault device in the analog sampling circuit.
After a fault device is detected to exist in the analog sampling circuit, the circuit fault self-checking method further comprises the following steps:
and setting the analog sampling circuit to be in a fault shutdown mode, and stopping outputting data.
Wherein the analog sampling circuit comprises: the interface protection unit, the analog channel selection unit, the operational amplifier conditioning unit and the analog-to-digital conversion unit are connected in sequence; each node in the analog sampling circuit is as follows: the first node at the front end of the analog channel selection unit, the second node at the front end of the operational amplifier conditioning unit and the third node at the front end of the analog-to-digital conversion unit.
Wherein, the comparing the actual voltage value of each node with the theoretical voltage value of each node to detect the fault device in the analog sampling circuit includes:
judging whether the error between the actual voltage value of the third node and the corresponding theoretical voltage value is within a preset range or not; if so, judging that no fault device exists in the analog sampling circuit;
if not, judging whether the error between the actual voltage value of the first node and the corresponding theoretical voltage value is within a preset range; if not, judging that the voltage reference unit generating the self-checking voltage has a fault;
if yes, judging whether the error between the actual voltage value of the second node and the corresponding theoretical voltage value is within a preset range; if not, judging that the operational amplifier conditioning unit has a fault; and if so, judging that the operational amplifier conditioning unit has no fault.
The collecting actual voltage values of all nodes in the analog sampling circuit to be detected comprises the following steps:
and respectively acquiring the actual voltage value of each node in the analog sampling circuit to be detected through a working conversion unit and a standby conversion unit in the analog-to-digital conversion unit.
Wherein, if after said judging that the operational amplifier conditioning unit has no fault, further comprising:
judging whether the error between the actual voltage value of the third node converted by the standby conversion unit and the corresponding theoretical voltage value is within a preset range;
if yes, judging that a working conversion unit of the analog-digital conversion unit is in fault; and if not, judging that the working conversion unit and the standby conversion unit both have faults.
If the working conversion unit of the analog-to-digital conversion unit is judged to be in fault, the circuit fault self-detection method further comprises the following steps:
and replacing the working conversion unit by the standby conversion unit.
After a fault device is detected to exist in the analog sampling circuit, the circuit fault self-checking method further comprises the following steps:
and inputting the actual voltage waveform of each node into a fault diagnosis model, and outputting a fault diagnosis result through the fault diagnosis model, wherein the fault diagnosis result comprises a fault mode of the fault device.
The generation method of the fault diagnosis model comprises the following steps:
determining a schematic circuit diagram of the analog sampling circuit;
carrying out fault simulation and fault simulation on the principle circuit diagram to obtain a fault characteristic vector;
preprocessing the fault feature vector to generate a training set and a test set;
and training an initial fault diagnosis model through the training set and the testing set to generate the fault diagnosis model.
Wherein, the training an initial fault diagnosis model through the training set and the testing set to generate the fault diagnosis model comprises:
training the initial fault diagnosis model by using the training set, and verifying whether the performance of the trained initial fault diagnosis model reaches the standard or not through the test set after the training is finished;
if so, taking the trained initial fault diagnosis model as the fault diagnosis model; and if not, increasing the training data of the training set, and continuing to train the initial fault diagnosis model.
To achieve the above object, the present invention further provides a circuit fault self-checking device, comprising:
the acquisition module is used for acquiring the actual voltage value of each node in the analog sampling circuit to be detected in a self-checking mode;
the acquisition module is used for acquiring the theoretical voltage value of each node in the analog sampling circuit;
and the detection module is used for comparing the actual voltage value of each node with the theoretical voltage value of each node so as to detect the fault device in the analog sampling circuit.
To achieve the above object, the present invention further provides an electronic device comprising:
an analog sampling circuit and a processor unit;
the processor unit is used for realizing the steps of the circuit fault self-checking method when executing a computer program.
Wherein the analog sampling circuit comprises: the interface protection unit, the analog channel selection unit, the operational amplifier conditioning unit and the analog-to-digital conversion unit are connected in sequence.
Wherein the analog-to-digital conversion unit includes: the working conversion unit and the standby conversion unit.
To achieve the above object, the present invention further provides a computer-readable storage medium having a computer program stored thereon, where the computer program is executed by a processor unit to implement the steps of the circuit fault self-checking method.
According to the above scheme, the circuit fault self-checking method provided by the embodiment of the invention comprises the following steps: acquiring actual voltage values of all nodes in an analog sampling circuit to be detected in a self-checking mode; obtaining theoretical voltage values of all nodes in the analog sampling circuit; and comparing the actual voltage value of each node with the theoretical voltage value of each node to detect the fault device in the analog sampling circuit. Therefore, when the scheme carries out fault self-checking on the analog sampling circuit, the actual voltage value of each node in the analog sampling circuit can be acquired, and the fault device in the analog sampling circuit is detected in a mode of comparing the actual voltage value with the corresponding theoretical value, so that fault positioning is realized; the invention also discloses a circuit fault self-checking device, equipment and a storage medium, and the technical effects can be realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic overall circuit diagram disclosed in an embodiment of the present invention;
fig. 2 is a schematic flow chart of a circuit fault self-checking method disclosed in the embodiment of the present invention;
FIG. 3 is a schematic diagram of a model training process disclosed in an embodiment of the present invention;
fig. 4 is a schematic view of an overall self-inspection process disclosed in the embodiment of the present invention;
fig. 5 is a schematic diagram of an output branch structure of a voltage reference unit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a circuit fault self-checking device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
The embodiment of the invention discloses a circuit fault self-checking method, a circuit fault self-checking device and a storage medium, which are used for realizing fault positioning when an analog sampling circuit performs fault self-checking. For clarity of description of the present solution, an electronic device provided in the present application is described herein, and the electronic device includes: an analog sampling circuit and a processor unit; wherein, this analog sampling circuit includes: the interface protection unit, the analog channel selection unit, the operational amplifier conditioning unit and the analog-to-digital conversion unit are connected in sequence. The analog-to-digital conversion unit includes: the working conversion unit and the standby conversion unit. The processor unit is configured to implement the steps of the circuit fault self-checking method according to the following method embodiments when executing the computer program.
Referring to fig. 1, an overall circuit diagram provided in an embodiment of the present invention is shown; as can be seen from fig. 1, the overall circuit diagram includes: the device comprises a voltage reference unit, an analog sampling circuit (an interface protection unit, an analog channel selection unit, an operational amplifier conditioning unit and an analog-to-digital conversion unit), a digital isolation unit, a processor unit and an isolation power supply unit. In the working mode, the interface protection unit acquires an analog quantity signal from the external sensor, and if the analog quantity transmitted by the external sensor is interfered to generate overvoltage, the interface protection unit can realize the protection of the rear-end analog channel selection unit; the signal input by the external sensor may be a voltage value or a current value, if the signal is a current value, the current value is a voltage value through a resistor in the interface protection unit, if the signal is a voltage value, the interface protection unit does not need to add a resistor, and the voltage signal can be directly sent to the analog channel selection unit.
In the self-test mode, the voltage reference unit can provide a self-test voltage as a reference input during self-test; the analog channel selection unit can switch a signal source entering the rear-end operational amplifier conditioning unit under the control of the processor unit, and the selectable signal source comprises: the analog quantity signal input by the external sensor and the self-checking signal generated by the voltage reference unit select the analog quantity signal in the working mode and select the self-checking signal in the self-checking mode; the operational amplifier conditioning unit is used for conditioning signals, such as: scaling the signal and completing impedance matching of the front end and the rear end of the operational amplifier conditioning unit; the analog-to-digital conversion unit is used for completing conversion between analog quantity and digital quantity so as to send information contained in the signal to the rear-end processor unit in a digital quantity form for processing, and comprises a work conversion unit AD1 (analog-to-digital conversion) and a standby conversion unit AD2; the digital isolation unit is used for realizing the current isolation between the front-end analog quantity sampling and analog-to-digital conversion unit and the rear-end processor and realizing the electric stress protection on the processor unit; the processor unit is used for finishing the processing of information and realizing the functions of fault diagnosis and safety; the isolation power supply unit is used for supplying power to an external sensor and providing power for a voltage reference unit and the like after isolating a power supply, and the isolation power supply unit realizes the isolation of the interface circuit part and the rear-end processor unit so as to protect the processor unit by important components in a hardware isolation scheme.
Referring to fig. 2, a schematic diagram of a circuit fault self-checking method provided by an embodiment of the present invention includes:
s101, collecting actual voltage values of all nodes in an analog sampling circuit to be detected in a self-checking mode;
it should be noted that the operation modes of the analog sampling circuit described in this embodiment include three states, namely, an operation mode, a self-test mode, and a fault shutdown mode. In the working mode, the processor unit controls the analog channel selection unit to switch the switch to the external sensor signal input, and the analog quantity signal input by the external sensor unit is conditioned and subjected to AD1 analog-to-digital conversion and then is transmitted to the processor unit for storage and processing. Under a self-checking mode, acquiring an actual voltage value of each node in the analog sampling circuit, and comparing the actual voltage value with a corresponding theoretical voltage value so as to position a fault; it should be noted that the actual voltage value collected in the self-checking mode in the present solution is the reference voltage, not the voltage collected by the external sensor; in addition, in this embodiment, the self-checking result may be stored in a self-checking log, or sent to a screen to display the self-checking result, where the self-checking result may be: the analog sampling circuit is not limited in particular, and may be a failure of the analog sampling circuit, a failure of some device in the analog sampling circuit, or the like.
Further, after the analog sampling circuit is detected to have a fault device, the analog sampling circuit needs to be set to a fault shutdown mode, and data output is stopped. Specifically, because the data output by the analog sampling circuit needs to be sent to other circuits for processing, the analog sampling circuit needs to be stopped from collecting analog quantity signals and outputting data in a fault shutdown mode, and error data are prevented from being output to other circuits; the analog sampling circuit is set to be in a fault shutdown mode, and the process of outputting data is stopped, and the method belongs to the function of safety guidance.
Specifically, if the analog sampling circuit in this embodiment includes: the interface protection unit, the analog channel selection unit, the operational amplifier conditioning unit and the analog-to-digital conversion unit which are connected in sequence, and each node in the analog sampling circuit is as follows: the first node at the front end of the analog channel selection unit, the second node at the front end of the operational amplifier conditioning unit and the third node at the front end of the analog-to-digital conversion unit. It should be noted that, in the present embodiment, only the analog sampling circuit includes the above units to describe the number and the positions of the nodes, and if the number of devices of the actual circuit is more, the positions and the numbers of the nodes may be set according to the actual situation, and the present invention is not limited in particular.
S102, obtaining theoretical voltage values of all nodes in the analog sampling circuit;
and S103, comparing the actual voltage value of each node with the theoretical voltage value of each node to detect a fault device in the analog sampling circuit.
It should be noted that, when fault location is performed through the actual voltage values of the nodes at each level, the theoretical voltage values of the nodes in the analog sampling circuit need to be calculated in advance according to the reference voltage values; the theoretical voltage value is the theoretical voltage value when all devices in the analog sampling circuit are not in fault, and if the error between the actual voltage value and the theoretical voltage value exceeds a preset range, the device is indicated to be in fault. The theoretical voltage values of the nodes can be different, for example, in the scheme, the operational amplifier conditioning unit can adjust the amplitude of the voltage, so that the voltage values of the nodes before and after the operational amplifier conditioning unit are different; the reference voltage may have a small amount of divided voltage (depending on the electrical characteristics of the analog channel selection unit) passing through the analog channel selection unit, and thus the node voltages before and after the analog channel selection unit may be different.
In this embodiment, the present disclosure is described by taking an example in which the analog sampling circuit includes an interface protection unit, an analog channel selection unit, an operational amplifier conditioning unit, and an analog-to-digital conversion unit. Specifically, if the analog-to-digital conversion unit includes the working conversion unit AD1, the processor unit needs to control the analog channel selection unit to switch the switch to the voltage reference unit in the self-test mode. The actual voltage value UZ1_1 of the first node is specifically: the voltage reference unit outputs a self-checking voltage, the AD1 performs analog-to-digital conversion on the voltage value read by the processor unit, and the actual voltage value UZ2_1 of the second node is specifically as follows: the voltage reference unit outputs a self-checking voltage which is output by the analog channel selection unit, the AD1 performs analog-to-digital conversion, and then the voltage value read by the processor unit, wherein the actual voltage value UZ3_1 of the third node is specifically as follows: the voltage reference unit outputs a self-checking voltage, the self-checking voltage is output by the operational amplifier conditioning unit, and the AD1 performs analog-to-digital conversion on the self-checking voltage to obtain a voltage value read by the processor unit.
Further, the process of comparing the actual voltage value of each node with the theoretical voltage value of each node to detect a faulty device in the analog sampling circuit specifically includes:
1. the first-level self-checking process: judging whether the error between the actual voltage value of the third node and the corresponding theoretical voltage value is within a preset range or not; if yes, judging that no fault device exists in the analog sampling circuit; if not, entering a second-level self-checking process;
specifically, in the first-stage self-test process, the UZ3_1 read by the processor unit is compared with a corresponding theoretical voltage value for judgment, and if the error is in a reasonable range, the self-test is qualified, which indicates that the analog sampling circuit has no problem. And if the error is larger, entering a second-stage self-test.
2. And (3) a second-level self-checking process: judging whether the error between the actual voltage value of the first node and the corresponding theoretical voltage value is within a preset range or not; if not, judging that the voltage reference unit generating the self-checking voltage has a fault; if yes, judging whether the error between the actual voltage value of the second node and the corresponding theoretical voltage value is within a preset range; if not, judging that the operational amplifier conditioning unit has a fault; if so, judging that the operational amplifier conditioning unit has no fault.
Specifically, the second-stage self-test process includes the following self-test processes:
2.1 level of self-test: judging whether the voltage reference unit has a fault, wherein the process specifically comprises the following steps: and comparing and judging the actual voltage value UZ1_1 of the first node acquired by the processor unit with a threshold, if the error is within a reasonable range, judging that the voltage reference unit has no fault, and entering 2.2-level self-test. And if the error is not reasonable, judging that the voltage reference has a fault.
2.2 level self-test: judging whether the operational amplifier conditioning unit breaks down, wherein the process specifically comprises the following steps: and comparing and judging the actual voltage value UZ2_1 of the second node acquired by the processor unit with a threshold, if the error is in a reasonable range, judging that the operational amplifier conditioning unit has no fault, and entering 2.3-level self-detection. And if the error is not reasonable, judging that the operational amplifier conditioning circuit has a fault.
2.3 level of self-test: judging whether the working conversion unit AD1 has a fault, wherein the process specifically comprises the following steps: and comparing and judging the actual voltage value UZ3_2 of the third node acquired by the processor unit with a threshold, if the error is in a reasonable range, judging that the working conversion unit AD1 has a fault, and replacing the working conversion unit AD1 by the standby conversion unit AD2 to finish the functions of first-stage self-detection, 2.1-stage self-detection and 2.2-stage self-detection in the operation mode and the subsequent self-detection mode. If the error is not within the reasonable range, it is determined that the conversion unit AD1 and the spare conversion unit AD2 are malfunctioning, and the output is stopped.
It should be noted that, in a currently common analog sampling self-checking scheme, analog-to-digital conversion processing of an acquired signal and a self-checking reference signal is performed in the same analog-to-digital conversion unit, and a fault of the analog-to-digital conversion unit cannot be determined, so in the scheme, a working conversion unit AD1 and a standby conversion unit AD2 are arranged in the analog-to-digital conversion unit, in a working mode, signal conversion is performed only through the working conversion unit, and in a self-checking mode, actual voltage values of nodes in an analog sampling circuit to be detected need to be respectively acquired through the working conversion unit and the standby conversion unit in the analog-to-digital conversion unit. As described above, the actual voltage values of the nodes at each level collected by the work conversion unit are respectively: the actual voltage value UZ1_1 of the first node, the actual voltage value UZ2_1 of the second node, and the actual voltage value UZ3_1 of the third node, and correspondingly, the actual voltage values of the nodes at each level collected by the standby conversion unit in the self-test mode are respectively: an actual voltage value UZ1_2 of the first node, an actual voltage value UZ2_2 of the second node, and an actual voltage value UZ3_2 of the third node, where the actual voltage value UZ1_2 of the first node is specifically: the voltage reference unit outputs a self-checking voltage, the AD2 performs analog-to-digital conversion on the voltage value read by the processor unit, and the actual voltage value UZ2_2 of the second node is specifically as follows: the voltage reference unit outputs a self-checking voltage which is output by the analog channel selection unit, the AD2 performs analog-to-digital conversion, and then the voltage value read by the processor unit, wherein the actual voltage value UZ3_2 of the third node is specifically as follows: the voltage reference unit outputs a self-checking voltage, the self-checking voltage is output by the operational amplifier conditioning unit, and the AD2 performs analog-to-digital conversion to obtain a voltage value read by the processor unit.
Therefore, in this embodiment, after determining that the operational amplifier conditioning unit has no fault, it may also be determined whether an error between the actual voltage value of the third node converted by the standby converting unit and the corresponding theoretical voltage value is within a predetermined range; if yes, judging that a working conversion unit of the analog-digital conversion unit is in fault, and replacing the working conversion unit by a standby conversion unit; if not, the working conversion unit and the standby conversion unit are judged to be in failure.
In conclusion, when the scheme is used for carrying out fault self-checking on the analog sampling circuit, the actual voltage value of each node in the analog sampling circuit can be collected, and the fault device in the analog sampling circuit is detected in a mode of comparing the actual voltage value with the corresponding theoretical value, so that the multilayer self-checking on the analog sampling circuit is realized, the fault is found in time, the output data is blocked, and the safety function is realized.
Based on the foregoing embodiment, in this embodiment, after detecting that a faulty device exists in the analog sampling circuit, the circuit fault self-checking method further includes: and inputting the actual voltage waveform of each node into a fault diagnosis model, and outputting a fault diagnosis result through the fault diagnosis model, wherein the fault diagnosis result comprises a fault mode of the fault device.
Specifically, the fault device can be positioned in the self-checking process, and further, the actual voltage waveform of each node can be subjected to fault diagnosis through a pre-trained fault diagnosis model, so that the specific fault mode of the fault device can be determined, and the fault mode can be understood as a fault reason, such as capacitor short circuit, resistance parameter drift and the like. The method for generating the fault diagnosis model comprises the following steps: determining a schematic circuit diagram of an analog sampling circuit, and performing fault simulation and fault simulation on the schematic circuit diagram to obtain a fault characteristic vector; preprocessing the fault characteristic vector to generate a training set and a testing set; and training the initial fault diagnosis model through a training set and a testing set to generate a fault diagnosis model. The process of training the initial fault diagnosis model through the training set and the testing set to generate the fault diagnosis model specifically comprises the following steps: training the initial fault diagnosis model by using a training set, and verifying whether the performance of the trained initial fault diagnosis model reaches the standard or not through a test set after the training is finished; if so, taking the trained initial fault diagnosis model as the fault diagnosis model; if not, increasing the training data of the training set, and continuing to train the initial fault diagnosis model.
Referring to fig. 3, a schematic diagram of a model training process according to an embodiment of the present invention is provided. As can be seen from fig. 3, in order to implement fault diagnosis of a circuit, supervised learning modeling is required to be performed on a circuit fault. Firstly, a schematic diagram is designed, and fault mode influence analysis is carried out aiming at the schematic diagram to obtain a common fault set and qualitative fault influence thereof. It should be noted that, when the fault diagnosis result is output by the fault diagnosis model, the fault diagnosis result is only the occurrence position of the fault, so in the present application, the fault that may occur in each link in the circuit, the information such as the influence caused by the fault, and the like can be obtained through fault mode influence analysis (FMEA), so as to prepare for the subsequent fault diagnosis, for example: the failure cause is poor welding and the failure mode is open circuit.
Further, the scheme also needs to perform fault simulation on the principle circuit diagram, such as: monte Carlo simulation of fault injection is carried out on the circuit, and voltage values of all nodes are obtained for direct current signals. For alternating current signals, the voltage of each node of the circuit under a certain frequency during frequency scanning can be obtained, and the characteristic vector representing the circuit fault is acquired. In order to further guarantee the accuracy of the data, the scheme also needs to perform fault simulation on the principle circuit diagram, such as: and carrying out individual fault injection test in the actual circuit board, and acquiring the voltage value of each node to obtain a real fault characteristic vector. In the scheme, data obtained by fault simulation and fault simulation are subjected to fusion processing, and data preprocessing such as normalization and principal component analysis is performed; the principal component analysis is to use the obtained numerous data to obtain some irrelevant comprehensive indexes through linear combination, and sort by taking variance in the comprehensive indexes as a measurement basis to find out principal components, thereby finding out data which can represent most information of the original data, reducing dimensionality of data analysis and simplifying analysis process. And then dividing the preprocessed data into a training set and a test set, and performing model training by using the training set until the test performance of the test set meets the requirement, so as to obtain a fault diagnosis model.
It can be understood that, in the present solution, circuit fault self-checking is specifically implemented by a processor unit, and the self-checking mode in the present solution includes power-on self-checking and operation self-checking, and if a fault is found in the circuit by comparing the actual voltage value of each node with the theoretical voltage value as described in the previous embodiment, fault diagnosis is continued by using a fault diagnosis model. Referring to fig. 4, it can be seen from fig. 4 that, when the power-on self-test process fails, the power-on self-test process is set to the fault shutdown mode, the output of data is stopped, fault diagnosis is performed through the fault diagnosis model, and a fault is outputA diagnostic result; after the power-on self-checking process is passed, every interval is a self-checking period T Self-test And if the operation self-check is not passed, setting the operation self-check to be in a fault shutdown mode, stopping outputting data, performing fault diagnosis through a fault diagnosis model, and outputting a fault diagnosis result.
It should be noted that, in this embodiment, in order to improve the self-checking accuracy and increase the information amount during fault diagnosis, two branches may be provided at the output end of the voltage reference unit, see fig. 5, which is a schematic structural diagram of the output branch of the voltage reference unit provided in the embodiment of the present invention; as can be seen from fig. 5, the output terminal of the voltage reference unit comprises two branches, one of which directly outputs the reference voltage U Z0 To the input port 1 of the analog channel selection unit, the other is divided into
And then output to the input port 2 of the analog channel selecting unit. In the self-checking mode, a self-checking source control signal can be output through the processor unit, and the self-checking signal is selected to be U Z0 Or (R)>
Selecting the self-test signal as U Z0 Then, a first self-check can be carried out, and a self-check signal is selected as->
And then carrying out a second self-inspection.
In conclusion, the scheme relates to a safety guide signal acquisition processing method based on machine learning, and can carry out multilayer self-checking on an analog sampling circuit, so that a fault device is found in time, output data is blocked, a safety function is realized, and after a model is established based on a fault diagnosis modeling method, a fault is diagnosed by acquiring multilayer signal data.
The following describes a self-testing apparatus provided in an embodiment of the present invention, and the self-testing apparatus described below and the self-testing method described above may be referred to each other.
Referring to fig. 6, a schematic structural diagram of a circuit fault self-checking device provided in an embodiment of the present invention includes:
the acquisition module 11 is configured to acquire an actual voltage value of each node in the analog sampling circuit to be detected in a self-check mode;
an obtaining module 12, configured to obtain a theoretical voltage value of each node in the analog sampling circuit;
and the detection module 13 is configured to compare the actual voltage value of each node with the theoretical voltage value of each node, so as to detect a faulty device in the analog sampling circuit.
Wherein the apparatus further comprises:
and the setting module is used for setting the analog sampling circuit into a fault shutdown mode and stopping outputting data after detecting that a fault device exists in the analog sampling circuit.
Wherein, analog sampling circuit includes: the interface protection unit, the analog channel selection unit, the operational amplifier conditioning unit and the analog-to-digital conversion unit are connected in sequence; each node in the analog sampling circuit is as follows: the first node at the front end of the analog channel selection unit, the second node at the front end of the operational amplifier conditioning unit and the third node at the front end of the analog-to-digital conversion unit.
Wherein, the detection module includes:
the first judgment unit is used for judging whether an error between the actual voltage value of the third node and the corresponding theoretical voltage value is within a preset range or not; if yes, triggering a first judging unit; if not, triggering a second judgment unit;
a first determination unit configured to determine that a faulty device is not present in the analog sampling circuit;
the second judging unit is used for judging whether the error between the actual voltage value of the first node and the corresponding theoretical voltage value is within a preset range or not; if not, triggering a second judging unit; if yes, triggering a third judging unit;
a second determination unit for determining a fault of the voltage reference unit generating the self-test voltage;
a third judging unit, configured to judge whether an error between an actual voltage value of the second node and a corresponding theoretical voltage value is within a predetermined range; if not, triggering a third judging unit; if yes, triggering a fourth judging unit;
the third judging unit is used for judging the fault of the operational amplifier conditioning unit;
and the fourth judging unit is used for judging that the operational amplifier conditioning unit has no fault.
Wherein, the collection module is specifically configured to: and respectively acquiring the actual voltage value of each node in the analog sampling circuit to be detected through a working conversion unit and a standby conversion unit in the analog-to-digital conversion unit.
Wherein, the detection module still includes:
the fourth judging unit is used for judging whether the error between the actual voltage value of the third node converted by the standby converting unit and the corresponding theoretical voltage value is within a preset range or not after judging that the operational amplifier conditioning unit has no fault; if yes, triggering a fifth judging unit; if not, triggering a sixth judging unit;
a fifth judging unit for judging a failure of a working converting unit of the analog-to-digital converting unit;
and the sixth judging unit is used for judging that the working converting unit and the standby converting unit both have faults.
Wherein the apparatus further comprises:
and the replacing module is used for replacing the working conversion unit by the standby conversion unit when judging that the working conversion unit of the analog-digital conversion unit fails.
Wherein the apparatus further comprises:
and the diagnosis module is used for inputting the actual voltage waveform of each node into a fault diagnosis model after detecting that a fault device exists in the analog sampling circuit, and outputting a fault diagnosis result through the fault diagnosis model, wherein the fault diagnosis result comprises a fault mode of the fault device.
Wherein the apparatus further comprises a generation module comprising:
the determining unit is used for determining a schematic circuit diagram of the analog sampling circuit;
the fault simulation and simulation unit is used for carrying out fault simulation and fault simulation on the principle circuit diagram to obtain a fault characteristic vector;
the preprocessing unit is used for preprocessing the fault characteristic vector to generate a training set and a test set;
and the training unit is used for training an initial fault diagnosis model through the training set and the test set to generate the fault diagnosis model.
Wherein the training unit is specifically configured to: training an initial fault diagnosis model by using the training set, and verifying whether the performance of the trained initial fault diagnosis model reaches the standard or not by using the test set after the training is finished; if so, taking the trained initial fault diagnosis model as the fault diagnosis model; if not, increasing the training data of the training set, and continuing to train the initial fault diagnosis model.
An embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor unit, the steps of the circuit fault self-checking method described in any of the above-mentioned method embodiments are implemented.
Wherein the storage medium may include: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (15)
1. A circuit fault self-checking method, comprising:
acquiring the actual voltage value of each node in the analog sampling circuit to be detected in a self-checking mode;
obtaining theoretical voltage values of all nodes in the analog sampling circuit;
and comparing the actual voltage value of each node with the theoretical voltage value of each node to detect the fault device in the analog sampling circuit.
2. The circuit fault self-test method of claim 1, wherein after detecting the presence of a faulty device in the analog sampling circuit, the circuit fault self-test method further comprises:
and setting the analog sampling circuit to be in a fault shutdown mode, and stopping outputting data.
3. The circuit fault self-checking method of claim 1, wherein the analog sampling circuit comprises: the interface protection unit, the analog channel selection unit, the operational amplifier conditioning unit and the analog-to-digital conversion unit are connected in sequence; each node in the analog sampling circuit is as follows: the first node at the front end of the analog channel selection unit, the second node at the front end of the operational amplifier conditioning unit and the third node at the front end of the analog-to-digital conversion unit.
4. The circuit fault self-checking method according to claim 3, wherein comparing the actual voltage value of each node with the theoretical voltage value of each node to detect the faulty device in the analog sampling circuit comprises:
judging whether the error between the actual voltage value of the third node and the corresponding theoretical voltage value is within a preset range or not; if yes, judging that no fault device exists in the analog sampling circuit;
if not, judging whether the error between the actual voltage value of the first node and the corresponding theoretical voltage value is within a preset range; if not, judging that the voltage reference unit generating the self-checking voltage has a fault;
if yes, judging whether the error between the actual voltage value of the second node and the corresponding theoretical voltage value is within a preset range; if not, judging that the operational amplifier conditioning unit has a fault; and if so, judging that the operational amplifier conditioning unit has no fault.
5. The circuit fault self-checking method according to claim 4, wherein the acquiring actual voltage values of nodes in the analog sampling circuit to be detected comprises:
and respectively acquiring the actual voltage value of each node in the analog sampling circuit to be detected through a working conversion unit and a standby conversion unit in the analog-to-digital conversion unit.
6. The method of claim 5, wherein if the operational amplifier conditioning unit is determined to be fault-free, the method further comprises:
judging whether the error between the actual voltage value of the third node converted by the standby conversion unit and the corresponding theoretical voltage value is within a preset range;
if yes, judging that a working conversion unit of the analog-digital conversion unit is in fault; if not, the working conversion unit and the standby conversion unit are judged to be in failure.
7. The circuit fault self-checking method according to claim 6, wherein if it is determined that the working conversion unit of the analog-to-digital conversion unit is faulty, the circuit fault self-checking method further comprises:
and replacing the working conversion unit by the standby conversion unit.
8. The circuit fault self-checking method according to any one of claims 1 to 7, wherein after detecting the presence of a faulty device in the analog sampling circuit, the circuit fault self-checking method further comprises:
and inputting the actual voltage waveform of each node into a fault diagnosis model, and outputting a fault diagnosis result through the fault diagnosis model, wherein the fault diagnosis result comprises a fault mode of the fault device.
9. The circuit fault self-checking method according to claim 8, wherein the method for generating the fault diagnosis model comprises:
determining a schematic circuit diagram of the analog sampling circuit;
carrying out fault simulation and fault simulation on the principle circuit diagram to obtain a fault characteristic vector;
preprocessing the fault feature vector to generate a training set and a test set;
and training an initial fault diagnosis model through the training set and the testing set to generate the fault diagnosis model.
10. The circuit fault self-test method of claim 9, wherein the training an initial fault diagnosis model through the training set and the testing set to generate the fault diagnosis model comprises:
training the initial fault diagnosis model by using the training set, and verifying whether the performance of the trained initial fault diagnosis model reaches the standard or not through the test set after the training is finished;
if so, taking the trained initial fault diagnosis model as the fault diagnosis model; and if not, increasing the training data of the training set, and continuing to train the initial fault diagnosis model.
11. A circuit fault self-test device, comprising:
the acquisition module is used for acquiring the actual voltage value of each node in the analog sampling circuit to be detected in a self-checking mode;
the acquisition module is used for acquiring the theoretical voltage value of each node in the analog sampling circuit;
and the detection module is used for comparing the actual voltage value of each node with the theoretical voltage value of each node so as to detect the fault device in the analog sampling circuit.
12. An electronic device, comprising:
an analog sampling circuit and a processor unit;
the processor unit, when executing a computer program, is configured to implement the steps of the circuit fault self-checking method according to any of claims 1 to 10.
13. The electronic device of claim 12, wherein the analog sampling circuit comprises: the interface protection unit, the analog channel selection unit, the operational amplifier conditioning unit and the analog-to-digital conversion unit are connected in sequence.
14. The electronic device of claim 13, wherein the analog-to-digital conversion unit comprises: a working conversion unit and a standby conversion unit.
15. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor unit, carries out the steps of the circuit fault self-checking method according to any one of claims 1 to 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111143571.7A CN115877189A (en) | 2021-09-28 | 2021-09-28 | Circuit fault self-checking method, device, equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111143571.7A CN115877189A (en) | 2021-09-28 | 2021-09-28 | Circuit fault self-checking method, device, equipment and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115877189A true CN115877189A (en) | 2023-03-31 |
Family
ID=85763490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111143571.7A Pending CN115877189A (en) | 2021-09-28 | 2021-09-28 | Circuit fault self-checking method, device, equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115877189A (en) |
-
2021
- 2021-09-28 CN CN202111143571.7A patent/CN115877189A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7395479B2 (en) | Over-voltage test for automatic test equipment | |
| US5404304A (en) | Vehicle control system for determining verified wheel speed signals | |
| US5459732A (en) | Method and apparatus for anti-lock brake single channel wheel speed processing with diagnosis | |
| CN106324385A (en) | Testing system and method for battery management system | |
| CN205122203U (en) | Nuclear power station out -pile neutron measurement system's detector verification, strike -machine device | |
| JP4096340B2 (en) | Electrical facility diagnostic system | |
| CN108241114B (en) | Online fault detection method and device for hybrid circuit chip and fault detection circuit | |
| CN103163398A (en) | System and method of nuclear power station Berea panel reliability detection | |
| CN112557966A (en) | Transformer winding looseness identification method based on local mean decomposition and support vector machine | |
| CN106772069B (en) | Method and device for detecting battery short circuit | |
| CN107171893A (en) | Automatic test platform and its method of testing based on CAN network | |
| CN115877189A (en) | Circuit fault self-checking method, device, equipment and storage medium | |
| CN113705637B (en) | Method, system, equipment and readable storage medium for detecting mechanical faults of circuit breaker | |
| CN109100671B (en) | Monitoring method and monitoring system for testing system in integrated circuit electronic component testing | |
| CN110929673A (en) | Transformer winding vibration signal identification method based on ITD (inverse discrete cosine transformation) permutation entropy and CGWO-SVM (Carrier-support vector machine) | |
| CN113068449B (en) | General detection equipment for Soviet aircraft photoelectric radar | |
| CN114487652A (en) | Fault verification method for long-term power-on equipment | |
| RU2605277C2 (en) | Method of testing electromagnetic compatibility of electric propulsion system with information onboard systems of space object, system of recording and playback of characteristics of discharge current of electric propulsion engines of electric propulsion system for implementing said method | |
| CN113573227A (en) | Microphone fault detection system, microphone fault detection method, electronic device and storage medium | |
| Anijärv et al. | Requirements to data acquisition and signal analysis for electrical grid condition monitoring | |
| CN110895976A (en) | Dynamic card detection device and method | |
| CN111090037A (en) | Reliability detection method for instrument control card | |
| CN113391141A (en) | Noise testing device and testing method | |
| CN113607992B (en) | Detection wave generation method of direct current power distribution protection device and related device | |
| CN113341251B (en) | Power transmission and transformation field construction monitoring system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |